d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi// Memory addresses on the BAR for the IGU Sub Block
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PATH - 1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_CMD_E2_PROD_UPD_UPPER (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PATH - 1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Fields of IGU PF CONFIGRATION REGISTER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* Fields of IGU VF CONFIGRATION REGISTER */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi/* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; [5:2] = 0; [1:0] = PF number) */
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
d14abf155341d55053c76eeec58b787a456b753bRobert Mustacchi#endif //IGU_DEFS_H