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2fcbc377041d659446ded306a92901b4b0753b68yt * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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2fcbc377041d659446ded306a92901b4b0753b68yt * information: Portions Copyright [yyyy] [name of copyright owner]
2fcbc377041d659446ded306a92901b4b0753b68yt * CDDL HEADER END
0a4c4cec315123d3aa1d87ee8ea976c5501de577Xiao-Yu Zhang * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
2fcbc377041d659446ded306a92901b4b0753b68yt * Use is subject to license terms.
2ac302890e472bf0c11db192dd18f12ded6043f6Marcel Telka * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
2fcbc377041d659446ded306a92901b4b0753b68ytextern "C" {
2fcbc377041d659446ded306a92901b4b0753b68yt * In AHCI spec, command table contains a list of 0 (no data transfer)
2fcbc377041d659446ded306a92901b4b0753b68yt * to up to 65,535 scatter/gather entries for the data transfer.
2fcbc377041d659446ded306a92901b4b0753b68yt * The default value of s/g entrie is 257, at least 1MB (4KB/pg * 256) + 1
2fcbc377041d659446ded306a92901b4b0753b68yt * if misaligned, and it's tuable by setting ahci_dma_prdt_number in
95c11c1f0a327937bf49e1fc3b7529ca70ffb34dyt/* PCI header offset for AHCI Base Address */
2fcbc377041d659446ded306a92901b4b0753b68yt/* various global HBA capability bits */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_EMS (0x1 << 6) /* enclosure management */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_CCCS (0x1 << 7) /* command completed coalescing */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_NCS (0x1f << 8) /* number of command slots */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_PSC (0x1 << 13) /* partial state capable */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_SSC (0x1 << 14) /* slumber state capable */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_PMD (0x1 << 15) /* PIO multiple DRQ block */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_FBSS (0x1 << 16) /* FIS-based switching */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_SPM (0x1 << 17) /* port multiplier */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_SNZO (0x1 << 19) /* non-zero DMA offsets */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_ISS (0xf << 20) /* interface speed support */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_SCLO (0x1 << 24) /* command list override */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_SALP (0x1 << 26) /* aggressive link power mgmt */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_SSS (0x1 << 27) /* staggered spin-up */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_SMPS (0x1 << 28) /* mechanical presence switch */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_SSNTF (0x1 << 29) /* Snotification register */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_SNCQ (0x1 << 30) /* Native Command Queuing */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_S64A ((uint32_t)0x1 << 31) /* 64-bit addressing */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_NCS_SHIFT 8 /* Number of command slots */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CAP_ISS_SHIFT 20 /* Interface speed support */
2fcbc377041d659446ded306a92901b4b0753b68yt/* various global HBA control bits */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_GHC_MRSM (0x1 << 2) /* MSI Revert to Single Message */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_GHC_AE ((uint32_t)0x1 << 31) /* AHCI Enable */
2fcbc377041d659446ded306a92901b4b0753b68yt/* various global HBA Command Completion Coalescing (CCC) control bits */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CCC_CTL_INT_MASK (0x1f << 3) /* Interrupt */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CCC_CTL_CC_MASK 0x0000ff00 /* Command Completions */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_CCC_CTL_TV_MASK 0xffff0000 /* Timeout Value */
2fcbc377041d659446ded306a92901b4b0753b68yt/* global HBA Enclosure Management Location (EM_LOC) */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_LOC_SZ_MASK 0x0000ffff /* Buffer Size */
2fcbc377041d659446ded306a92901b4b0753b68yt/* global HBA Enclosure Management Control (EM_CTL) bits */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_STS_MR (0x1 << 0) /* Message Received */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_CTL_TM (0x1 << 8) /* Transmit Message */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_SUPP_LED (0x1 << 16) /* LED Message Types */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_SUPP_SAFTE (0x1 << 17) /* SAF-TE EM Messages */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_SUPP_SES2 (0x1 << 18) /* SES-2 EM Messages */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_SUPP_SGPIO (0x1 << 19) /* SGPIO EM Messages */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_ATTR_SMB (0x1 << 24) /* Single Message Buffer */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_ATTR_XMT (0x1 << 25) /* Transmit Only */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_ATTR_ALHD (0x1 << 26) /* Activity LED HW Driven */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_HBA_EM_CTL_ATTR_PM (0x1 << 27) /* PM Support */
2fcbc377041d659446ded306a92901b4b0753b68yt/* global HBA registers definitions */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_GLOBAL_OFFSET(ahci_ctlp) (ahci_ctlp->ahcictl_ahci_addr)
2fcbc377041d659446ded306a92901b4b0753b68yt /* HBA Capabilities */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_GLOBAL_CAP(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x00)
2fcbc377041d659446ded306a92901b4b0753b68yt /* Global HBA Control */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_GLOBAL_GHC(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x04)
2fcbc377041d659446ded306a92901b4b0753b68yt /* Interrupt Status Register */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_GLOBAL_IS(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x08)
2fcbc377041d659446ded306a92901b4b0753b68yt /* Ports Implemented */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_GLOBAL_PI(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x0c)
2fcbc377041d659446ded306a92901b4b0753b68yt /* AHCI Version */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_GLOBAL_VS(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x10)
2fcbc377041d659446ded306a92901b4b0753b68yt /* Command Completion Coalescing Control */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_GLOBAL_CCC_CTL(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x14)
2fcbc377041d659446ded306a92901b4b0753b68yt /* Command Completion Coalescing Ports */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Enclosure Management Location */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_GLOBAL_EM_LOC(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x1c)
2fcbc377041d659446ded306a92901b4b0753b68yt /* Enclosure Management Control */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_GLOBAL_EM_CTL(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x20)
2ac302890e472bf0c11db192dd18f12ded6043f6Marcel Telka /* HBA Capabilities Extended (AHCI spec 1.2) */
2ac302890e472bf0c11db192dd18f12ded6043f6Marcel Telka#define AHCI_GLOBAL_CAP2(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x24)
2ac302890e472bf0c11db192dd18f12ded6043f6Marcel Telka /* BIOS/OS Handoff Control and Status (AHCI spec 1.2) */
2ac302890e472bf0c11db192dd18f12ded6043f6Marcel Telka#define AHCI_GLOBAL_BOHC(ahci_ctlp) (AHCI_GLOBAL_OFFSET(ahci_ctlp) + 0x28)
2fcbc377041d659446ded306a92901b4b0753b68yt/* various port interrupt bits */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Device to Host Register FIS Interrupt */
2fcbc377041d659446ded306a92901b4b0753b68yt /* PIO Setup FIS Interrupt */
2fcbc377041d659446ded306a92901b4b0753b68yt /* DMA Setup FIS Interrupt */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Set Device Bits Interrupt */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Unknown FIS Interrupt */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Descriptor Processed */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Port Connect Change Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Device Mechanical Presence Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* PhyRdy Change Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Incorrect Port Multiplier Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Overflow Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Interface Non-fatal Error Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Interface Fatal Error Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Host Bus Data Error Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Host Bus Fatal Error Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Task File Error Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Cold Port Detect Status */
2fcbc377041d659446ded306a92901b4b0753b68yt/* port command and status bits */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_SUD (0x1 << 1) /* Spin-up device */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_POD (0x1 << 2) /* Power on device */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_CLO (0x1 << 3) /* Command list override */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_FRE (0x1 << 4) /* FIS receive enable */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_CCS (0x1f << 8) /* Current command slot */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Mechanical presence switch state */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_FR (0x1 << 14) /* FIS receiving running */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_CR (0x1 << 15) /* Command list running */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_CPS (0x1 << 16) /* Cold presence state */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_PMA (0x1 << 17) /* Port multiplier attached */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_HPCP (0x1 << 18) /* Hot plug capable port */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Mechanical presence switch attached to port */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_CPD (0x1 << 20) /* Cold presence detection */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_ESP (0x1 << 21) /* External SATA port */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_ATAPI (0x1 << 24) /* Device is ATAPI */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_DLAE (0x1 << 25) /* Drive LED on ATAPI enable */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Aggressive link power magament enable */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMD_STATUS_ASP (0x1 << 27) /* Aggressive slumber/partial */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Interface communication control */
2fcbc377041d659446ded306a92901b4b0753b68yt/* port task file data bits */
0a4c4cec315123d3aa1d87ee8ea976c5501de577Xiao-Yu Zhang#define AHCI_TFD_ERR_SGS (0x1 << 0) /* DDR1: Send_good_status */
8aa6aadbbfba50077655c6a46a5e269c880e4ab4Xiao-Yu Zhang/* FIS-Based Switching Control Register */
8aa6aadbbfba50077655c6a46a5e269c880e4ab4Xiao-Yu Zhang#define AHCI_FBS_SWE_MASK (0xf << 16) /* Device With Error */
8aa6aadbbfba50077655c6a46a5e269c880e4ab4Xiao-Yu Zhang#define AHCI_FBS_ADO_MASK (0xf << 12) /* Active Device Optimization */
8aa6aadbbfba50077655c6a46a5e269c880e4ab4Xiao-Yu Zhang#define AHCI_FBS_DEV_MASK (0xf << 8) /* Device To Issue */
8aa6aadbbfba50077655c6a46a5e269c880e4ab4Xiao-Yu Zhang#define AHCI_FBS_SDE (0x1 << 2) /* Single Device Error */
8aa6aadbbfba50077655c6a46a5e269c880e4ab4Xiao-Yu Zhang#define AHCI_FBS_DEC (0x1 << 1) /* Device Error Clear */
8aa6aadbbfba50077655c6a46a5e269c880e4ab4Xiao-Yu Zhang/* Sxxx Registers */
2fcbc377041d659446ded306a92901b4b0753b68yt/* per port registers offset */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Command List Base Address */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Command List Base Address Upper 32-Bits */
2fcbc377041d659446ded306a92901b4b0753b68yt /* FIS Base Address */
2fcbc377041d659446ded306a92901b4b0753b68yt /* FIS Base Address Upper 32-Bits */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Interrupt Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Interrupt Enable */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Command and Status */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Task File Data */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Signature */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Serial ATA Status (SCR0:SStatus) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Serial ATA Control (SCR2:SControl) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Serial ATA Error (SCR1:SError) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Serial ATA Active (SCR3:SActive) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* Command Issue */
2fcbc377041d659446ded306a92901b4b0753b68yt /* SNotification */
8aa6aadbbfba50077655c6a46a5e269c880e4ab4Xiao-Yu Zhang /* FIS-Based Switching Control */
2fcbc377041d659446ded306a92901b4b0753b68yt ((ahci_ctlp->ahcictl_num_cmd_slots == AHCI_PORT_MAX_CMD_SLOTS) ? \
2fcbc377041d659446ded306a92901b4b0753b68yt 0xffffffff : ((0x1 << ahci_ctlp->ahcictl_num_cmd_slots) - 1))
82263d52a84b4a969aa53f8ededddff841646ad9yt ((ahci_portp->ahciport_max_ncq_tags == AHCI_PORT_MAX_CMD_SLOTS) ? \
82263d52a84b4a969aa53f8ededddff841646ad9yt 0xffffffff : ((0x1 << ahci_portp->ahciport_max_ncq_tags) - 1))
8aa6aadbbfba50077655c6a46a5e269c880e4ab4Xiao-Yu Zhang ((0x1 << ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports) - 1)
2fcbc377041d659446ded306a92901b4b0753b68yt/* Device signatures */
68d33a2562b5b41e4606c8b0f50f32fd26b05302yt#define AHCI_CMDHEAD_ATAPI 0x1 /* set to 1 for ATAPI command */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMDHEAD_DATA_WRITE 0x1 /* From system memory to device */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMDHEAD_DATA_READ 0x0 /* From device to system memory */
2fcbc377041d659446ded306a92901b4b0753b68yt#define AHCI_CMDHEAD_PREFETCHABLE 0x1 /* if set, HBA prefetch PRDs */
2fcbc377041d659446ded306a92901b4b0753b68yt/* Register - Host to Device FIS (from SATA spec) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x00 */
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= (type & 0xff))
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 16) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features >> 24) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x04 */
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((sector & 0xff)))
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_low & 0xff) << 8))
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 16) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((cyl_hi & 0xff) << 16))
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifhr_sector_cyllow_cylhi_devhead >> 24) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_sector_cyllow_cylhi_devhead |= ((dev_head & 0xff) << 24))
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x08 */
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 8) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp >> 16) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \
2fcbc377041d659446ded306a92901b4b0753b68yt (fis->ahcifhr_sectexp_cyllowexp_cylhiexp_featuresexp |= \
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x0c */
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl >> 8) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x10 */
2fcbc377041d659446ded306a92901b4b0753b68yt/* Register - Device to Host FIS (from SATA spec) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x00 */
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifdr_type_intr_rsvd_status_error >> 16) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifdr_type_intr_rsvd_status_error >> 24) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x04 */
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 16) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifdr_sector_cyllow_cylhi_devhead >> 24) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x08 */
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 8) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt ((fis->ahcifdr_sectexp_cyllowexp_cylhiexp_rsvd >> 16) & 0xff)
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x0c */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x10 */
2fcbc377041d659446ded306a92901b4b0753b68yt/* Set Device Bits - Device to Host FIS (from SATA spec) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x00 */
68d33a2562b5b41e4606c8b0f50f32fd26b05302yt ((fis->ahcifsdb_type_rsvd_intr_status_error >> 15) & 0x1)
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x04 */
2fcbc377041d659446ded306a92901b4b0753b68yt/* DMA Setup - Device to Host or Host to Device (from SATA spec) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x00 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x04 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x08 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x0c */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x10 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x14 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x18 */
2fcbc377041d659446ded306a92901b4b0753b68yt/* PIO Setup - Device to Host FIS (from SATA spec) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x00 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x04 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x08 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x0c */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x10 */
2fcbc377041d659446ded306a92901b4b0753b68yt/* BIST Active - Host to Device or Device to Host (from SATA spec) */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x00 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x04 */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x08 */
2fcbc377041d659446ded306a92901b4b0753b68yt/* Up to 64 bytes */
2fcbc377041d659446ded306a92901b4b0753b68yt * This is a software constructed FIS. For data transfer,
2fcbc377041d659446ded306a92901b4b0753b68yt * this is the H2D Register FIS format as specified in
2fcbc377041d659446ded306a92901b4b0753b68yt * the Serial ATA 1.0a specification. Valid Command FIS
2fcbc377041d659446ded306a92901b4b0753b68yt * length are 2 to 16 Dwords.
2fcbc377041d659446ded306a92901b4b0753b68yt/* Received FISes structure - size 100h */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x00 - DMA Setup FIS */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x20 - PIO Setup FIS */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x40 - D2H Register FIS */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x58 - Set Device Bits FIS */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x60 - Unknown FIS */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0xa0h - Reserved */
2fcbc377041d659446ded306a92901b4b0753b68yt/* physical region description table (PRDT) item structure */
2fcbc377041d659446ded306a92901b4b0753b68yt /* DW 0 - Data Base Address */
2fcbc377041d659446ded306a92901b4b0753b68yt /* DW 1 - Data Base Address Upper */
2fcbc377041d659446ded306a92901b4b0753b68yt /* DW 2 - Reserved */
2fcbc377041d659446ded306a92901b4b0753b68yt /* DW 3 - Description Information */
2fcbc377041d659446ded306a92901b4b0753b68yt/* command table structure */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x00 - Command FIS */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x40 - ATAPI Command */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x50 - Reserved */
2fcbc377041d659446ded306a92901b4b0753b68yt /* offset 0x80 - Physical Region Description Table */
2fcbc377041d659446ded306a92901b4b0753b68yt/* command head structure - size 20h */
2fcbc377041d659446ded306a92901b4b0753b68yt /* DW 0 - Description Information */
2fcbc377041d659446ded306a92901b4b0753b68yt (cmd_header->ahcich_descr_info |= ((length & 0xffff) << 16))
2fcbc377041d659446ded306a92901b4b0753b68yt (cmd_header->ahcich_descr_info |= ((flags & 0x0f) << 12))
2fcbc377041d659446ded306a92901b4b0753b68yt (cmd_header->ahcich_descr_info |= ((flags & 0x01) << 10))
2fcbc377041d659446ded306a92901b4b0753b68yt (cmd_header->ahcich_descr_info |= ((features_exp & 0x01) << 8))
2fcbc377041d659446ded306a92901b4b0753b68yt /* DW 1 - Physical Region Descriptor Byte Count */
2fcbc377041d659446ded306a92901b4b0753b68yt /* DW 2 - Command Table Base Address */
2fcbc377041d659446ded306a92901b4b0753b68yt#define SET_COMMAND_TABLE_BASE_ADDR(cmd_header, base_address) \
2fcbc377041d659446ded306a92901b4b0753b68yt /* DW 3 - Command Table Base Address Upper */
2fcbc377041d659446ded306a92901b4b0753b68yt#define SET_COMMAND_TABLE_BASE_ADDR_UPPER(cmd_header, base_address) \
2fcbc377041d659446ded306a92901b4b0753b68yt (cmd_header->ahcich_cmd_tab_base_addr_upper = base_address)
2fcbc377041d659446ded306a92901b4b0753b68yt /* DW 4-7 - Reserved */
2fcbc377041d659446ded306a92901b4b0753b68yt#endif /* _AHCIREG_H */