Searched refs:t4_read_reg (Results 1 - 6 of 6) sorted by relevance

/illumos-gate/usr/src/uts/common/io/cxgbe/common/
H A Dt4_hw.c52 u32 val = t4_read_reg(adapter, reg);
84 u32 v = t4_read_reg(adapter, addr) & ~mask;
87 (void) t4_read_reg(adapter, addr); /* flush */
109 *vals++ = t4_read_reg(adap, data_reg);
208 v = G_MBOWNER(t4_read_reg(adap, ctl_reg));
210 v = G_MBOWNER(t4_read_reg(adap, ctl_reg));
219 (void) t4_read_reg(adap, ctl_reg); /* flush write */
233 v = t4_read_reg(adap, ctl_reg);
275 if (t4_read_reg(adap, A_MC_BIST_CMD) & F_START_BIST)
289 *data++ = htonl(t4_read_reg(ada
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/illumos-gate/usr/src/uts/common/io/cxgbe/t4nex/
H A Dadapter.c26 t4_read_reg(struct adapter *sc, uint32_t reg) function
H A Dt4_ioctl.c134 r.value = t4_read_reg(sc, r.reg);
150 *p++ = t4_read_reg(sc, start);
500 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
502 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
511 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
520 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
548 (void) t4_read_reg(sc,
555 *b++ = t4_read_reg(sc, MEMWIN2_BASE + off + i);
H A Dt4_nexus.c1115 val = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
1121 bar = t4_read_reg(sc, A_MA_EDRAM0_BAR);
1128 bar = t4_read_reg(sc, A_MA_EDRAM1_BAR);
1135 bar = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
1154 (void) t4_read_reg(sc,
1357 val[0] = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
H A Dadapter.h568 uint32_t t4_read_reg(struct adapter *sc, uint32_t reg);
H A Dt4_sge.c263 v = t4_read_reg(sc, A_SGE_CONM_CTRL);
3207 bgmap = G_NUMPORTS(t4_read_reg(pi->adapter, A_MPS_CMN_CTL));

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