56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * This file and its contents are supplied under the terms of the
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * Common Development and Distribution License ("CDDL"), version 1.0.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * You may only use this file in accordance with the terms of version
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * 1.0 of the CDDL.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * A full copy of the text of the CDDL should have accompanied this
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * source. A copy of the CDDL is also available via the Internet at
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * This file is part of the Chelsio T4 support code.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * This program is distributed in the hope that it will be useful, but WITHOUT
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * release for licensing terms and conditions.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana EQ_ESIZE = 64, /* All egres queues use this entry size */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana RX_FL_ESIZE = 64, /* 8 64bit addresses */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* adapter flags */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* port flags */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* Features */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define IS_DOOMED(pi) (pi->flags & DOOMED)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define SET_DOOMED(pi) do { pi->flags |= DOOMED; } while (0)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define IS_BUSY(sc) (sc->flags & CXGBE_BUSY)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define SET_BUSY(sc) do { sc->flags |= CXGBE_BUSY; } while (0)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define CLR_BUSY(sc) do { sc->flags &= ~CXGBE_BUSY; } while (0)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana int16_t xact_addr_filt; /* index of exact MAC address filter */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t rss_size; /* size of VI's RSS table slice */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t first_txq; /* index of first tx queue */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t first_rxq; /* index of first rx queue */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t nofldtxq; /* # of offload tx queues */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t first_ofld_txq; /* index of first offload tx queue */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t nofldrxq; /* # of offload rx queues */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t first_ofld_rxq; /* index of first offload rx queue */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint8_t lport; /* associated offload logical port */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint8_t instance; /* Associated adapter instance */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint8_t child_inst; /* Associated child instance */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana/* DMA maps used for tx */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t map_total; /* # of DMA maps */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t map_pidx; /* next map to be used */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t map_cidx; /* reclaimed up to this index */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t map_avail; /* # of available maps */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t txb_used; /* # of bytes of tx copy buffer used */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t hdls_used; /* # of dma handles used */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t desc_used; /* # of hardware descriptors used */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* iq flags */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana IQ_INTR = (1 << 1), /* iq takes direct interrupt */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* iq state */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * Ingress Queue: T4 is producer, driver is consumer.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana __be64 *desc; /* KVA of descriptor ring */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t ba; /* bus address of descriptor ring */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana const __be64 *cdesc; /* current descriptor */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct adapter *adapter; /* associated adapter */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint8_t intr_params; /* interrupt holdoff parameters */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana int8_t intr_pktc_idx; /* packet count threshold index */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint8_t intr_next; /* holdoff for next interrupt */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint8_t esize; /* size (bytes) of each entry in the queue */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t qsize; /* size (# of entries) of the queue */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t pending; /* # of descs processed since last doorbell */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t cntxt_id; /* SGE context id for the iq */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t abs_id; /* absolute SGE id for the iq */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* eq flags */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana EQ_TYPEMASK = 7, /* 3 lsbits hold the type */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana EQ_DOOMED = (1 << 4), /* about to be destroyed */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana EQ_MTX = (1 << 7), /* mutex has been initialized */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * Egress Queue: driver is producer, T4 is consumer.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * Note: A free list is an egress queue (driver produces the buffers and T4
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * consumes them) but it's special enough to have its own struct (see sge_fl).
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct tx_desc *desc; /* KVA of descriptor ring */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t ba; /* bus address of descriptor ring */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_qstat *spg; /* status page, for convenience */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t cap; /* max # of desc, for convenience */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t avail; /* available descriptors, for convenience */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t qsize; /* size (# of entries) of the queue */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t cidx; /* consumer idx (desc idx) */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t pidx; /* producer idx (desc idx) */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t pending; /* # of descriptors used since last doorbell */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t iqid; /* iq that gets egr_update for the eq */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint8_t tx_chan; /* tx channel used by the eq */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t cntxt_id; /* SGE context id for the eq */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* fl flags */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana FL_MTX = (1 << 0), /* mutex has been initialized */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana FL_STARVING = (1 << 1), /* on the list of starving fl's */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana FL_DOOMED = (1 << 2), /* about to be destroyed */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t ba; /* bus address of descriptor ring */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t cap; /* max # of buffers, for convenience */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t qsize; /* size (# of entries) of the queue */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t cntxt_id; /* SGE context id for the freelist */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t needed; /* # of buffers needed to fill up fl. */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t lowat; /* # of buffers <= this means fl needs help */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t pending; /* # of bufs allocated since last doorbell */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t offset; /* current packet within the larger buffer */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t copy_threshold; /* anything this size or less is copied up */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t copied_up; /* # of frames copied into mblk and handed up */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t passed_up; /* # of frames wrapped in mblk and handed up */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana/* txq: SGE egress queue + miscellaneous items */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct port_info *port; /* the port this txq belongs to */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* DMA handles used for tx */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t tx_dhdl_total; /* Total # of handles */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t tx_dhdl_pidx; /* next handle to be used */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t tx_dhdl_cidx; /* reclaimed up to this index */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t tx_dhdl_avail; /* # of available handles */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* Copy buffers for tx */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana caddr_t txb_va; /* KVA of copy buffers area */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t txb_ba; /* bus address of copy buffers area */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t txb_next; /* offset of next useable area in the buffer */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t txb_avail; /* # of bytes available */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint16_t copy_threshold; /* anything this size or less is copied up */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* stats for common events first */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t txcsum; /* # of times hardware assisted with checksum */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t tso_wrs; /* # of IPv4 TSO work requests */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t imm_wrs; /* # of work requests with immediate data */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t sgl_wrs; /* # of work requests with direct SGL */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t txpkts_wrs; /* # of coalesced tx work requests */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t txb_used; /* # of tx copy buffers used (64 byte each) */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t hdl_used; /* # of DMA handles used */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* stats for not-that-common events */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t txb_full; /* txb ran out of space */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t dma_map_failed; /* couldn't obtain DMA mapping */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t qfull; /* out of hardware descriptors */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t qflush; /* # of SGE_EGR_UPDATE notifications for txq */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t pullup_early; /* # of pullups before starting frame's SGL */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t pullup_late; /* # of pullups while building frame's SGL */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t pullup_failed; /* # of failed pullups */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana/* rxq: SGE ingress queue + SGE free list + miscellaneous items */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct port_info *port; /* the port this rxq belongs to */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* stats for common events first */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t rxcsum; /* # of times hardware assisted with checksum */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* stats for not-that-common events */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t nomem; /* mblk allocation during rx failed */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * wrq: SGE egress queue that is given prebuilt work requests. Both the control
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana * and offload tx queues are of this type.
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* List of WRs held up due to lack of tx descriptors */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* stats for common events first */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint64_t tx_wrs; /* # of tx work requests */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* stats for not-that-common events */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint32_t no_desc; /* out of hardware descriptors */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana int nrxq; /* total rx queues (all ports and the rest) */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana int ntxq; /* total tx queues (all ports and the rest) */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana int nofldrxq; /* total # of TOE rx queues */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana int nofldtxq; /* total # of TOE tx queues */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_iq fwq; /* Firmware event queue */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_wrq mgmtq; /* Management queue (Control queue) */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_txq *txq; /* NIC tx queues */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_rxq *rxq; /* NIC rx queues */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_wrq *ctrlq; /* Control queues */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_wrq *ofld_txq; /* TOE tx queues */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* Device access and DMA attributes for all the descriptor rings */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* Device access and DMA attributes for tx buffers */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* Device access and DMA attributes for rx buffers are in rxb_params */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* There is a driver.conf variable for each of these */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanatypedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana uint_t open; /* character device is open */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* PCI config space access handle */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* MMIO register access handle */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* Interrupt information */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana /* Starving free lists */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana kmutex_t sfl_lock; /* same cache-line as sc_lock? but that's ok */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define ADAPTER_LOCK(sc) mutex_enter(&(sc)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define ADAPTER_UNLOCK(sc) mutex_exit(&(sc)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define ADAPTER_LOCK_ASSERT_OWNED(sc) ASSERT(mutex_owned(&(sc)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define PORT_LOCK(pi) mutex_enter(&(pi)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define PORT_UNLOCK(pi) mutex_exit(&(pi)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define PORT_LOCK_ASSERT_OWNED(pi) ASSERT(mutex_owned(&(pi)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define PORT_LOCK_ASSERT_NOTOWNED(pi) ASSERT(!mutex_owned(&(pi)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define IQ_LOCK(iq) mutex_enter(&(iq)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define IQ_UNLOCK(iq) mutex_exit(&(iq)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define IQ_LOCK_ASSERT_OWNED(iq) ASSERT(mutex_owned(&(iq)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define IQ_LOCK_ASSERT_NOTOWNED(iq) ASSERT(!mutex_owned(&(iq)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define FL_LOCK(fl) mutex_enter(&(fl)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define FL_UNLOCK(fl) mutex_exit(&(fl)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define FL_LOCK_ASSERT_OWNED(fl) ASSERT(mutex_owned(&(fl)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define FL_LOCK_ASSERT_NOTOWNED(fl) ASSERT(!mutex_owned(&(fl)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define EQ_LOCK(eq) mutex_enter(&(eq)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define EQ_UNLOCK(eq) mutex_exit(&(eq)->lock)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define EQ_LOCK_ASSERT_OWNED(eq) ASSERT(mutex_owned(&(eq)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define EQ_LOCK_ASSERT_NOTOWNED(eq) ASSERT(!mutex_owned(&(eq)->lock))
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana txq = &pi->adapter->sge.txq[pi->first_txq]; \
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana for (iter = 0; iter < pi->ntxq; ++iter, ++txq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana for (iter = 0; iter < pi->nrxq; ++iter, ++rxq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define for_each_ofld_txq(pi, iter, ofld_txq) \
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define for_each_ofld_rxq(pi, iter, ofld_rxq) \
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1)
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana/* One for errors, one for firmware events */
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanauint32_t t4_read_reg(struct adapter *sc, uint32_t reg);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanauint64_t t4_read_reg64(struct adapter *sc, uint32_t reg);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanastruct port_info *adap2pinfo(struct adapter *sc, int idx);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanabool is_10G_port(const struct port_info *pi);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanastruct sge_rxq *iq_to_rxq(struct sge_iq *iq);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_os_find_pci_capability(struct adapter *sc, int cap);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_os_portmod_changed(const struct adapter *sc, int idx);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint adapter_full_init(struct adapter *sc);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint adapter_full_uninit(struct adapter *sc);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint port_full_init(struct port_info *pi);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint port_full_uninit(struct port_info *pi);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid enable_port_queues(struct port_info *pi);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid disable_port_queues(struct port_info *pi);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_iterate(void (*func)(int, void *), void *arg);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_setup_adapter_queues(struct adapter *sc);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_teardown_adapter_queues(struct adapter *sc);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_setup_port_queues(struct port_info *pi);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_teardown_port_queues(struct port_info *pi);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanauint_t t4_intr_all(caddr_t arg1, caddr_t arg2);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanauint_t t4_intr(caddr_t arg1, caddr_t arg2);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanauint_t t4_intr_err(caddr_t arg1, caddr_t arg2);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_mgmt_tx(struct adapter *sc, mblk_t *m);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanamblk_t *t4_eth_tx(struct port_info *pi, struct sge_txq *txq, mblk_t *frame);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps, int count,
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_os_link_changed(struct adapter *sc, int idx, int link_stat);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanavoid t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanaint t4_ioctl(struct adapter *sc, int cmd, void *data, int mode);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushanastruct l2t_data *t4_init_l2t(struct adapter *sc);
56b2bdd1f04d465cfe4a95b88ae5cba5884154e4Gireesh Nagabhushana#endif /* __CXGBE_ADAPTER_H */