Searched refs:reg (Results 1 - 25 of 729) sorted by relevance

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/illumos-gate/usr/src/lib/libc/sparc/gen/
H A Dgetctxt.c42 greg_t *reg; local
55 reg = ucp->uc_mcontext.gregs;
56 reg[REG_SP] = getfp();
57 reg[REG_O7] = caller();
58 reg[REG_PC] = reg[REG_O7] + 8;
59 reg[REG_nPC] = reg[REG_PC] + 4;
60 reg[REG_O0] = 0;
H A Dswapctxt.c42 greg_t *reg; local
54 reg = oucp->uc_mcontext.gregs;
55 reg[REG_SP] = getfp();
56 reg[REG_O7] = caller();
57 reg[REG_PC] = reg[REG_O7] + 8;
58 reg[REG_nPC] = reg[REG_PC] + 4;
59 reg[REG_O0] = 0;
/illumos-gate/usr/src/lib/libc/sparcv9/gen/
H A Dgetctxt.c42 greg_t *reg; local
55 reg = ucp->uc_mcontext.gregs;
56 reg[REG_SP] = getfp();
57 reg[REG_O7] = caller();
58 reg[REG_PC] = reg[REG_O7] + 8;
59 reg[REG_nPC] = reg[REG_PC] + 4;
60 reg[REG_O0] = 0;
H A Dswapctxt.c42 greg_t *reg; local
54 reg = oucp->uc_mcontext.gregs;
55 reg[REG_SP] = getfp();
56 reg[REG_O7] = caller();
57 reg[REG_PC] = reg[REG_O7] + 8;
58 reg[REG_nPC] = reg[REG_PC] + 4;
59 reg[REG_O0] = 0;
/illumos-gate/usr/src/lib/libast/common/sfio/
H A D_sfputc.c27 int sfputc(reg Sfio_t* f, reg int c)
30 reg Sfio_t* f;
31 reg int c;
H A D_sfclrerr.c27 int sfclrerr(reg Sfio_t* f)
30 reg Sfio_t* f;
H A D_sfdlen.c27 int sfdlen(reg Sfdouble_t v)
30 reg Sfdouble_t v;
H A D_sfeof.c27 int sfeof(reg Sfio_t* f)
30 reg Sfio_t* f;
H A D_sferror.c27 int sferror(reg Sfio_t* f)
30 reg Sfio_t* f;
H A D_sffileno.c27 int sffileno(reg Sfio_t* f)
30 reg Sfio_t* f;
H A D_sfgetc.c27 int sfgetc(reg Sfio_t* f)
30 reg Sfio_t* f;
H A D_sfllen.c27 int sfllen(reg Sflong_t v)
30 reg Sflong_t v;
H A D_sfstacked.c27 int sfstacked(reg Sfio_t* f)
30 reg Sfio_t* f;
H A D_sfulen.c27 int sfulen(reg Sfulong_t v)
30 reg Sfulong_t v;
H A D_sfvalue.c27 ssize_t sfvalue(reg Sfio_t* f)
30 reg Sfio_t* f;
H A Dsfputd.c27 int sfputd(reg Sfio_t* f, Sfdouble_t d)
30 reg Sfio_t* f;
31 reg Sfdouble_t d;
/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Dintel_nhm.h62 #define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \
63 0x4c, reg);
65 #define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \
66 reg);
102 #define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \
103 ((reg) & (1 << (8 + (channel))) != 0)
104 #define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1)
105 #define MC_CONTROL_CLOSED_PAGE(reg) ((reg)
[all...]
/illumos-gate/usr/src/uts/i86pc/io/xsvc/
H A Dxsvc.conf30 # The reg property defines the physical range that the xsvc driver can
33 name="xsvc" class="root" reg=0x0,0,0xffffffff;
/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_dcb_82598.c121 u32 reg = 0; local
126 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
127 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
129 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
131 reg &= ~IXGBE_RMCS_ARBDIS;
133 reg |= IXGBE_RMCS_RRM;
135 reg |= IXGBE_RMCS_DFP;
137 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
144 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
147 reg |
177 u32 reg, max_credits; local
221 u32 reg; local
264 u32 fcrtl, reg; local
316 u32 reg = 0; local
[all...]
H A Dixgbe_dcb_82599.c121 u32 reg = 0; local
130 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
131 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
139 reg = 0;
141 reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
143 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
149 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
151 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
154 reg |= IXGBE_RTRPT4C_LSP;
156 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
179 u32 reg, max_credits; local
225 u32 reg; local
285 u32 i, j, fcrtl, reg; local
372 u32 reg = 0; local
498 u32 reg; local
[all...]
/illumos-gate/usr/src/uts/common/sys/
H A Dvgasubr.h42 extern int vga_get_reg(struct vgaregmap *reg, int i);
43 extern void vga_set_reg(struct vgaregmap *reg, int i, int v);
44 extern int vga_get_crtc(struct vgaregmap *reg, int i);
45 extern void vga_set_crtc(struct vgaregmap *reg, int i, int v);
46 extern int vga_get_seq(struct vgaregmap *reg, int i);
47 extern void vga_set_seq(struct vgaregmap *reg, int i, int v);
48 extern int vga_get_grc(struct vgaregmap *reg, int i);
49 extern void vga_set_grc(struct vgaregmap *reg, int i, int v);
50 extern int vga_get_atr(struct vgaregmap *reg, int i);
51 extern void vga_set_atr(struct vgaregmap *reg, in
[all...]
/illumos-gate/usr/src/uts/common/io/ixgbe/
H A Dixgbe_osdep.c33 ixgbe_read_pci_cfg(struct ixgbe_hw *hw, uint32_t reg) argument
35 return (pci_config_get16(OS_DEP(hw)->cfg_handle, reg));
39 ixgbe_write_pci_cfg(struct ixgbe_hw *hw, uint32_t reg, uint32_t val) argument
41 pci_config_put16(OS_DEP(hw)->cfg_handle, reg, val);
/illumos-gate/usr/src/uts/intel/sys/
H A Dreg.h34 #include <ia32/sys/reg.h>
H A Dpci_cfgspace.h45 extern uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
46 extern uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
47 extern uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
48 extern void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
49 extern void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
50 extern void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
/illumos-gate/usr/src/uts/sun/io/
H A Dzs.conf28 reg=0x210,0xf1000000,0x4 interrupts=12;
31 reg=0x210,0xf0000000,0x4 interrupts=12;
36 reg=0x210,0xe0000004,0x4 interrupts=12;

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