ixgbe/core/ixgbe_dcb_82598.c

dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/******************************************************************************
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  Copyright (c) 2001-2015, Intel Corporation
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  All rights reserved.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  Redistribution and use in source and binary forms, with or without
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  modification, are permitted provided that the following conditions are met:
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent   1. Redistributions of source code must retain the above copyright notice,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent      this list of conditions and the following disclaimer.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent   2. Redistributions in binary form must reproduce the above copyright
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent      notice, this list of conditions and the following disclaimer in the
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent      documentation and/or other materials provided with the distribution.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent   3. Neither the name of the Intel Corporation nor the names of its
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent      contributors may be used to endorse or promote products derived from
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent      this software without specific prior written permission.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent  POSSIBILITY OF SUCH DAMAGE.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent******************************************************************************/
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/*$FreeBSD$*/
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#include "ixgbe_type.h"
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#include "ixgbe_dcb.h"
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#include "ixgbe_dcb_82598.h"
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/**
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @stats: pointer to statistics structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @tc_count:  Number of elements in bwg_array.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent *
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * This function returns the status data for each of the Traffic Classes in use.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                 struct ixgbe_hw_stats *stats,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                 u8 tc_count)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent{
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    int tc;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    DEBUGFUNC("dcb_get_tc_stats");
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        return IXGBE_ERR_PARAM;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Statistics pertaining to each traffic class */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    for (tc = 0; tc < tc_count; tc++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        /* Transmitted Packets */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        /* Transmitted Bytes */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        /* Received Packets */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        /* Received Bytes */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if 0
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        /* Can we get rid of these??  Consequently, getting rid
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent         * of the tc_stats structure.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent         */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        tc_stats_array[up]->in_overflow_discards = 0;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        tc_stats_array[up]->out_overflow_discards = 0;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#endif
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    }
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    return IXGBE_SUCCESS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent}
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/**
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @stats: pointer to statistics structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @tc_count:  Number of elements in bwg_array.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent *
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * This function returns the CBFC status data for each of the Traffic Classes.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                  struct ixgbe_hw_stats *stats,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                  u8 tc_count)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent{
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    int tc;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    DEBUGFUNC("dcb_get_pfc_stats");
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        return IXGBE_ERR_PARAM;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    for (tc = 0; tc < tc_count; tc++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        /* Priority XOFF Transmitted */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        /* Priority XOFF Received */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    }
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    return IXGBE_SUCCESS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent}
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/**
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent *
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure Rx Data Arbiter and credits for each traffic class.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                      u16 *max, u8 *tsa)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent{
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u32 reg = 0;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u32 credit_refill = 0;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u32 credit_max = 0;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u8 i = 0;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Enable Arbiter */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg &= ~IXGBE_RMCS_ARBDIS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Enable Receive Recycle within the BWG */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= IXGBE_RMCS_RRM;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Enable Deficit Fixed Priority arbitration*/
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= IXGBE_RMCS_DFP;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Configure traffic class credits and priority */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        credit_refill = refill[i];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        credit_max = max[i];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        if (tsa[i] == ixgbe_dcb_tsa_strict)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent            reg |= IXGBE_RT2CR_LSP;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    }
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= IXGBE_RDRXCTL_RDMTS_1_2;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= IXGBE_RDRXCTL_MPBEN;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= IXGBE_RDRXCTL_MCEN;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Make sure there is enough descriptors before arbitration */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg &= ~IXGBE_RXCTRL_DMBYPS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    return IXGBE_SUCCESS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent}
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/**
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent *
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure Tx Descriptor Arbiter and credits for each traffic class.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                       u16 *refill, u16 *max, u8 *bwg_id,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                       u8 *tsa)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent{
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u32 reg, max_credits;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u8 i;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Enable arbiter */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg &= ~IXGBE_DPMCS_ARBDIS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= IXGBE_DPMCS_TSOEF;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Configure Max TSO packet size 34KB including payload and headers */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Configure traffic class credits and priority */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        max_credits = max[i];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg |= refill[i];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent            reg |= IXGBE_TDTQ2TCCR_GSP;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        if (tsa[i] == ixgbe_dcb_tsa_strict)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent            reg |= IXGBE_TDTQ2TCCR_LSP;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    }
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    return IXGBE_SUCCESS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent}
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/**
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent *
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure Tx Data Arbiter and credits for each traffic class.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                       u16 *refill, u16 *max, u8 *bwg_id,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                       u8 *tsa)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent{
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u32 reg;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u8 i;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Enable Data Plane Arbiter */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg &= ~IXGBE_PDPMCS_ARBDIS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Enable DFP and Transmit Recycle Mode */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Configure traffic class credits and priority */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg = refill[i];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent            reg |= IXGBE_TDPT2TCCR_GSP;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        if (tsa[i] == ixgbe_dcb_tsa_strict)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent            reg |= IXGBE_TDPT2TCCR_LSP;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    }
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Enable Tx packet buffer division */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= IXGBE_DTXCTL_ENDBUBD;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    return IXGBE_SUCCESS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent}
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/**
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_pfc_82598 - Config priority flow control
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent *
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure Priority Flow Control for each traffic class.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent{
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u32 fcrtl, reg;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u8 i;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Enable Transmit Priority Flow Control */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg &= ~IXGBE_RMCS_TFCE_802_3X;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg |= IXGBE_RMCS_TFCE_PRIORITY;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Enable Receive Priority Flow Control */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    if (pfc_en)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg |= IXGBE_FCTRL_RPFCE;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Configure PFC Tx thresholds per TC */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        if (!(pfc_en & (1 << i))) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent            IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent            IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent            continue;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        }
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    }
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Configure pause time */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Configure flow control refresh threshold value */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    return IXGBE_SUCCESS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent}
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/**
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent *
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure queue statistics registers, all queues belonging to same traffic
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * class uses a single set of queue statistics counters.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent{
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u32 reg = 0;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u8 i = 0;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    u8 j = 0;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Receive Queues stats setting -  8 queues per statistics reg */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg |= ((0x1010101) * j);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg |= ((0x1010101) * j);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    }
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    /* Transmit Queues stats setting -  4 queues per statistics reg*/
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    for (i = 0; i < 8; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        reg |= ((0x1010101) * i);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent        IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    }
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    return IXGBE_SUCCESS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent}
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/**
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_hw_config_82598 - Config and enable DCB
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent *
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure dcb settings and enable dcb mode.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                  u16 *refill, u16 *max, u8 *bwg_id,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                  u8 *tsa)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent{
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    UNREFERENCED_1PARAMETER(link_speed);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                           tsa);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent                           tsa);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    ixgbe_dcb_config_tc_stats_82598(hw);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent    return IXGBE_SUCCESS;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent}