Searched refs:dev_hdl (Results 1 - 23 of 23) sorted by relevance

/illumos-gate/usr/src/uts/sun4v/io/px/
H A Dpx_lib4v.h129 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid,
132 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid,
134 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid,
136 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra,
138 extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra,
145 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id,
147 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id,
149 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
151 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
153 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_
[all...]
H A Dpx_libhv.c48 static uint64_t hvio_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps,
52 hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps_cap) argument
54 return (hvio_rp_mps(dev_hdl, bdf, mps_cap, MPS_GET));
58 hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t mps) argument
60 return (hvio_rp_mps(dev_hdl, bdf, &mps, MPS_SET));
64 hvio_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, int32_t *mps, int op) argument
71 if ((hvio_config_get(dev_hdl, bdf, PCI_CONF_VENID, 4,
78 if ((hvio_config_get(dev_hdl, bdf, PCI_CONF_COMM, 4,
85 (void) hvio_config_get(dev_hdl, bdf, PCI_CONF_CAP_PTR, 4,
99 (void) hvio_config_get(dev_hdl, bd
[all...]
H A Dpx_hcall.s41 hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
48 hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
54 hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p,
60 hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr,
66 hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status,
72 hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data,
78 hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes,
84 hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra,
90 hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p,
96 hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_
[all...]
H A Dpx_lib4v.c87 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) argument
125 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK);
136 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl);
/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.h305 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p,
307 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino,
309 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino,
311 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino,
313 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino,
315 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p,
317 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p,
320 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid,
323 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p,
325 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_
[all...]
H A Dpx_hlib.c169 static uint64_t msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p);
170 static void msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p);
1787 hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, pages_t pages, argument
1819 CSR_XS(dev_hdl,
1839 CSR_XS(dev_hdl,
1853 hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, argument
1869 CSR_XS(dev_hdl,
1882 hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, argument
2026 hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, r_addr_t ra, argument
2047 hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_ argument
2065 hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, intr_valid_state_t *intr_valid_state) argument
2084 hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, intr_valid_state_t intr_valid_state) argument
2108 hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, intr_state_t *intr_state) argument
2142 hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, intr_state_t intr_state) argument
2172 hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino, cpuid_t *cpuid) argument
2198 hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, sysino_t sysino, cpuid_t cpuid) argument
2246 hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p) argument
2265 hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, pci_msiq_valid_state_t *msiq_valid_state) argument
2291 hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, pci_msiq_valid_state_t msiq_valid_state) argument
2314 hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, pci_msiq_state_t *msiq_state) argument
2339 hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, pci_msiq_state_t msiq_state) argument
2375 hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, msiqhead_t *msiq_head) argument
2385 hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, msiqhead_t msiq_head) argument
2395 hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, msiqtail_t *msiq_tail) argument
2408 hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, uint64_t addr64) argument
2426 hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, msiqid_t *msiq_id) argument
2436 hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, msiqid_t msiq_id) argument
2446 hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, pci_msi_valid_state_t *msi_valid_state) argument
2456 hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, pci_msi_valid_state_t msi_valid_state) argument
2478 hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, pci_msi_state_t *msi_state) argument
2488 hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, pci_msi_state_t msi_state) argument
2511 hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, msiqid_t *msiq_id) argument
2543 hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, msiqid_t msiq_id) argument
2573 hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, pcie_msg_valid_state_t *msg_valid_state) argument
2606 hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, pcie_msg_valid_state_t msg_valid_state) argument
2671 hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) argument
2732 hvio_resume(devhandle_t dev_hdl, devino_t devino, pxu_t *pxu_p) argument
2809 hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) argument
2912 msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) argument
2940 msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p) argument
[all...]
H A Dpx_lib4u.c179 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) argument
280 *dev_hdl = (devhandle_t)csr_base;
282 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl);
1327 devhandle_t dev_hdl, xbus_dev_hdl; local
1332 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR];
1335 if ((ret = hvio_suspend(dev_hdl, pxu_p)) != H_EOK)
1355 devhandle_t dev_hdl, xbus_dev_hdl; local
1361 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR];
1365 hvio_cb_resume(dev_hdl, xbus_dev_hd
[all...]
/illumos-gate/usr/src/uts/sun4v/io/fpc/
H A Dfpc-impl-4v.h42 extern int fpc_get_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t *data);
43 extern int fpc_set_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t data);
H A Dfpc-asm-4v.s47 fpc_get_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t *data)
52 fpc_set_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t data)
58 * fpc_get_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t *data)
70 * fpc_set_fire_perfreg(devhandle_t dev_hdl, int regid, uint64_t data)
H A Dfpc-impl-4v.c122 devhandle_t dev_hdl; local
152 dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK);
178 (fire_perfreg_handle_t)dev_hdl, jbc, &dummy_data, IS_READ) ==
181 (fire_perfreg_handle_t)dev_hdl, imu, &dummy_data, IS_READ) ==
200 (void) fpc_set_platform_data_by_number(index, (void *)dev_hdl);
243 devhandle_t dev_hdl = (devhandle_t)handle; local
246 rval = fpc_set_fire_perfreg(dev_hdl, hv_if_index, *reg_data);
248 rval = fpc_get_fire_perfreg(dev_hdl, hv_if_index, reg_data);
/illumos-gate/usr/src/uts/sun4v/io/pciex/
H A Dpci_cfgacc_asm.s42 hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off,
48 hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off,
/illumos-gate/usr/src/uts/intel/io/acpica/
H A Dacpica_ec.c404 ACPI_HANDLE dev_hdl; local
428 status = AcpiGetHandle(NULL, (char *)ecdt->Id, &dev_hdl);
439 ec.ec_dev_hdl = dev_hdl;
469 ACPI_HANDLE dev_hdl; local
478 dev_hdl = NULL;
479 (void) AcpiGetDevices("PNP0C09", &ec_find, (void *)&dev_hdl, NULL);
480 if (dev_hdl == NULL) {
493 status = AcpiEvaluateObjectTyped(dev_hdl, "_CRS", NULL, &crs,
537 status = AcpiEvaluateObject(dev_hdl, "_GPE", NULL, &buf);
578 ec.ec_dev_hdl = dev_hdl;
[all...]
/illumos-gate/usr/src/uts/sun4v/sys/
H A Dhypervisor_api.h396 extern uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino,
442 extern uint64_t hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino,
444 extern uint64_t hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino,
446 extern uint64_t hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino,
448 extern uint64_t hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino,
450 extern uint64_t hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino,
452 extern uint64_t hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino,
454 extern uint64_t hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino,
456 extern uint64_t hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino,
/illumos-gate/usr/src/cmd/devctl/
H A Ddevctl.c447 devctl_hdl_t dev_hdl = NULL; local
460 if (devctl_bus_dev_create(bus_dcp, ddef_hdl, 0, &dev_hdl)) {
464 } else if (devctl_get_pathname(dev_hdl, devctl_device, MAXPATHLEN)
475 if (dev_hdl)
476 devctl_release(dev_hdl);
/illumos-gate/usr/src/uts/sun4v/ml/
H A Dhcall.s120 hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino)
272 hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie)
277 hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie)
282 hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state)
287 hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state)
292 hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state)
297 hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state)
302 hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid)
307 hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid)
1066 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_
[all...]
/illumos-gate/usr/src/cmd/picl/plugins/sun4u/cherrystone/psvcpolicy/
H A Dpsvcpolicy.c232 devctl_hdl_t dev_hdl = NULL; local
248 if (devctl_bus_dev_create(bus_hdl, ddef_hdl, 0, &dev_hdl))
251 if (devctl_get_pathname(dev_hdl, dev_path, MAXPATHLEN) == NULL)
260 if (dev_hdl) devctl_release(dev_hdl);
273 devctl_hdl_t dev_hdl; local
275 dev_hdl = devctl_device_acquire(nd, 0);
276 if (dev_hdl == NULL) {
280 rv = devctl_device_remove(dev_hdl);
287 devctl_release(dev_hdl);
[all...]
/illumos-gate/usr/src/cmd/zoneadmd/
H A Dzcons.c334 devctl_hdl_t dev_hdl = NULL; local
394 if (devctl_bus_dev_create(bus_hdl, ddef_hdl, 0, &dev_hdl) == -1) {
454 if (dev_hdl)
455 devctl_release(dev_hdl);
/illumos-gate/usr/src/cmd/picl/plugins/sun4u/mpxu/frudr/
H A Dpiclfrudr.c2853 devctl_hdl_t dev_hdl; local
2887 if (devctl_bus_dev_create(bus_hdl, ddef_hdl, 0, &dev_hdl))
2890 if (devctl_get_pathname(dev_hdl, dev_path, MAXPATHLEN) == NULL)
2893 devctl_release(dev_hdl);
2905 devctl_hdl_t dev_hdl; local
2921 dev_hdl = devctl_device_acquire(buf, 0);
2922 if (dev_hdl == NULL) {
2930 if (devctl_device_remove(dev_hdl)) {
2932 devctl_device_remove(dev_hdl);
2934 devctl_release(dev_hdl);
[all...]
/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_lib.h57 extern int px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl);
H A Dpx.c229 devhandle_t dev_hdl = NULL; local
268 if (px_lib_dev_init(dip, &dev_hdl) != DDI_SUCCESS)
272 px_p->px_dev_hdl = dev_hdl;
/illumos-gate/usr/src/lib/cfgadm_plugins/fp/common/
H A Dcfga_cs.c70 devctl_hdl_t bus_hdl, dev_hdl; local
102 if (devctl_bus_dev_create(bus_hdl, ddef_hdl, 0, &dev_hdl)) {
124 devctl_get_pathname(dev_hdl, dev_path, pathlen);
125 devctl_release(dev_hdl);
/illumos-gate/usr/src/uts/sun4v/io/
H A Dvnet_gen.c1717 mdeg_handle_t dev_hdl = NULL; local
1749 rv = mdeg_register(parentp, &vdev_match, vgen_mdeg_cb, vgenp, &dev_hdl);
1764 vgenp->mdeg_dev_hdl = dev_hdl;
1770 if (dev_hdl != NULL) {
1771 (void) mdeg_unregister(dev_hdl);
/illumos-gate/usr/src/uts/common/io/scsi/adapters/mpt_sas/
H A Dmptsas.c856 uint16_t dev_hdl; local
1018 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
15030 uint16_t dev_hdl; local
15215 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
15228 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15378 uint16_t dev_hdl; local
15521 &dev_hdl, &dev_sas_wwn, &dev_info,
15535 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15774 uint16_t dev_hdl; local
15853 &dev_hdl,
[all...]

Completed in 184 milliseconds