Searched refs:chnl (Results 1 - 7 of 7) sorted by relevance

/illumos-gate/usr/src/uts/common/io/
H A Ddma_engine.c85 int chnl; local
90 for (chnl = 0; chnl < NCHANS; chnl++) {
91 sema_init(&dmae_stat[chnl].dch_lock, 1, NULL, SEMA_DRIVER,
107 i_dmae_acquire(dev_info_t *dip, int chnl, int (*dmae_waitfp)(), caddr_t arg) argument
113 chnl, (void *)dmae_waitfp));
115 if (!d37A_dma_valid(chnl))
119 sema_p(&dmae_stat[chnl].dch_lock);
120 } else if (sema_tryp(&dmae_stat[chnl]
147 i_dmae_free(dev_info_t *dip, int chnl) argument
190 _dmae_nxcookie(int chnl) argument
222 i_dmae_prog(dev_info_t *dip, struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl) argument
261 i_dmae_swsetup(dev_info_t *dip, struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl) argument
294 i_dmae_swstart(dev_info_t *dip, int chnl) argument
314 i_dmae_stop(dev_info_t *dip, int chnl) argument
338 i_dmae_enable(dev_info_t *dip, int chnl) argument
358 i_dmae_disable(dev_info_t *dip, int chnl) argument
379 i_dmae_get_chan_stat(dev_info_t *dip, int chnl, ulong_t *addressp, int *countp) argument
[all...]
H A Di8237A.c115 static void dEISA_setchain(ddi_dma_cookie_t *cp, int chnl);
156 d37A_dma_valid(int chnl) argument
159 if (chnl == 4)
173 d37A_dma_release(int chnl) argument
176 if (chnl == 4)
179 d37A_chnl_mode[chnl] = DMAE_TRANS_SNGL;
190 d37A_dma_disable(int chnl) argument
192 dprintf(("d37A_dma_disable: chnl=%d mask_reg=0x%x\n",
193 chnl, chan_addr[chnl]
208 d37A_dma_enable(int chnl) argument
243 int chnl, istate, nstate; local
290 dEISA_setchain(ddi_dma_cookie_t *cp, int chnl) argument
318 d37A_prog_chan(struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl) argument
410 d37A_dma_swsetup(struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cp, int chnl) argument
490 d37A_dma_swstart(int chnl) argument
509 d37A_dma_stop(int chnl) argument
528 d37A_get_chan_stat(int chnl, ulong_t *addressp, int *countp) argument
555 d37A_set_mode(struct ddi_dmae_req *dmaereqp, int chnl) argument
663 d37A_write_addr(ulong_t paddress, int chnl) argument
713 d37A_read_addr(int chnl) argument
765 d37A_write_count(long count, int chnl) argument
812 d37A_read_count(int chnl) argument
[all...]
/illumos-gate/usr/src/uts/common/sys/
H A Ddma_engine.h92 #define DMAE_PATH_8 1 /* ISA default for chnl 0..3 */
93 #define DMAE_PATH_16 2 /* ISA default for chnl 5..7 */
121 extern void i_dmae_get_chan_stat(dev_info_t *dip, int chnl,
162 * chnl - a DMA channel number.
188 int ddi_dmae_alloc(dev_info_t *dip, int chnl, int (*dmae_waitfp)(),
198 int ddi_dmae_release(dev_info_t *dip, int chnl);
207 int ddi_dmae_1stparty(dev_info_t *dip, int chnl);
233 ddi_dma_cookie_t *cookiep, int chnl);
236 ddi_dma_cookie_t *cookiep, int chnl);
238 int ddi_dmae_swstart(dev_info_t *dip, int chnl);
[all...]
/illumos-gate/usr/src/uts/intel/ia32/os/
H A Dddi_i86.c47 ddi_dmae_alloc(dev_info_t *dip, int chnl, int (*dmae_waitfp)(), caddr_t arg) argument
51 (caddr_t *)(uintptr_t)chnl, 0));
55 ddi_dmae_release(dev_info_t *dip, int chnl) argument
58 (caddr_t *)(uintptr_t)chnl, 0));
69 ddi_dmae_1stparty(dev_info_t *dip, int chnl) argument
72 (caddr_t *)(uintptr_t)chnl, 0));
77 ddi_dma_cookie_t *cookiep, int chnl)
80 (size_t *)cookiep, (caddr_t *)(uintptr_t)chnl, 0));
85 ddi_dma_cookie_t *cookiep, int chnl)
88 (size_t *)cookiep, (caddr_t *)(uintptr_t)chnl,
76 ddi_dmae_prog(dev_info_t *dip, struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cookiep, int chnl) argument
84 ddi_dmae_swsetup(dev_info_t *dip, struct ddi_dmae_req *dmaereqp, ddi_dma_cookie_t *cookiep, int chnl) argument
92 ddi_dmae_swstart(dev_info_t *dip, int chnl) argument
99 ddi_dmae_stop(dev_info_t *dip, int chnl) argument
106 ddi_dmae_enable(dev_info_t *dip, int chnl) argument
113 ddi_dmae_disable(dev_info_t *dip, int chnl) argument
120 ddi_dmae_getcnt(dev_info_t *dip, int chnl, int *countp) argument
[all...]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/mcp/
H A Dncsi_basic_types.h535 u32_t chnl : 8; member in struct:SrcMacAddr
/illumos-gate/usr/src/uts/common/io/iwn/
H A Dif_iwn.c7289 int error, chnl, qid; local
7358 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
7359 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
7404 int chnl, qid, ntries; local
7426 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
7427 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
[all...]
H A Dif_iwnreg.h314 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16))

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