fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* $NetBSD: if_iwnreg.h,v 1.15 2014/11/09 14:40:54 nonaka Exp $ */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* $OpenBSD: if_iwnreg.h,v 1.49 2014/09/09 18:56:24 sthen Exp $ */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Copyright (c) 2007, 2008
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Damien Bergamini <damien.bergamini@free.fr>
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Permission to use, copy, modify, and distribute this software for any
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * purpose with or without fee is hereby granted, provided that the above
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * copyright notice and this permission notice appear in all copies.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Copyright 2016 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* XXX Added for NetBSD */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t))
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Maximum number of DMA segments for TX. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* RX buffers must be large enough to hold a full 4K A-MPDU. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* HW supports 36-bit DMA addresses. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Base Address Register. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Control and status registers.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Flow-Handler registers.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * TX scheduler registers.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Offsets in TX scheduler's SRAM.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * NIC internal memory offsets.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_HW_IF_CONFIG. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible values for register IWN_INT_PERIODIC. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible values for IWN_BSM_WR_MEM_DST. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_RESET. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_GP_CNTRL. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_HW_REV. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Types 6030 and 6035 also return 11 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_GIO_CHICKEN. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_GIO. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_GP_DRIVER. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_GP_DRIVER_RADIO_IQ_INVERT (1 << 7)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_UCODE_GP1_CLR. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags/values for register IWN_LED. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_DRAM_INT_TBL. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible values for register IWN_ANA_PLL. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_FH_RX_STATUS. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_BSM_WR_CTRL. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_INT. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Shortcut. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_FH_INT. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16))
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Shortcuts for the above. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags/values for register IWN_FH_TX_CONFIG. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1U << 20)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_FH_TX_CHICKEN. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_FH_TX_STATUS. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16))
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_FH_RX_CONFIG. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_RX_CONFIG_RB_SIZE_8K (1U << 16)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_RX_CONFIG_SINGLE_FRAME (1U << 15)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1U << 12)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1U << 2)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_FH_TX_CONFIG. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1U << 3)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_EEPROM. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_EEPROM_GP. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_OTP_GP. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_SCHED_QUEUE_STATUS. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for registers IWN_APMG_CLK_*. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_APMG_PS. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_APMG_DIGITAL_SVR. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for IWN_APMG_PCI_STT. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* Pad to 128 bytes. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible RX status flags. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Shortcut for the above. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Antenna flags, used in various commands. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Shortcuts. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_RXON. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* The following fields are for >=5000 Series only. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN5000_RXONSZ (sizeof (struct iwn_rxon))
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_ASSOCIATE. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_EDCA_PARAMS. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_TIMING. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_ADD_NODE. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* The following 3 fields are for 5000 Series only. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_TX_DATA. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_LINK_QUALITY. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_SET_LED. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN5000_CMD_WIMAX_COEX. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structures for command IWN5000_CMD_CALIB_CONFIG. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_SET_POWER_MODE. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structures for command IWN_CMD_SCAN. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* Followed by a struct iwn_cmd_data. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* Followed by an array of 20 structs iwn_scan_essid. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* Followed by probe request body. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* Followed by an array of ``nchan'' structs iwn_scan_chan. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Maximum size of a scan command. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * sending probe req. This should be set long enough to hear probe responses
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * from more than one AP.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Must be set longer than active dwell time.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * For the most reliable scan, set > AP beacon interval (typically 100msec).
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * If active scanning is requested but a certain channel is
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * marked passive, we can do active scanning if we detect
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * transmissions.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * There is an issue with some firmware versions that triggers
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * a sysassert on a "good CRC threshold" of zero (== disabled),
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * on a radar channel even though this means that we should NOT
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * send probes.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * The "good CRC threshold" is the number of frames that we
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * need to receive during our dwell time on a channel before
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * sending out probes -- setting this to a huge value will
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * mean we never reach it, but at the same time work around
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * here instead of IWN_GOOD_CRC_TH_DISABLED.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * This was fixed in later versions along with some other
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * scan changes, and the threshold behaves as a flag in those
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_BT_COEX. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_COEX_ENABLE (IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_KILL_ACK_MASK_DEF htole32(0xffff0000)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_KILL_CTS_MASK_DEF htole32(0xffff0000)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_BASIC_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5))
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * The original code causes problems with lint. These declarations
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * could be fixed with lint tags, but the assignment to
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * reduce_txpower in iwn_config_bt_coex_adv_config() cannot.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * For reference it remains here but is ifdef'ed out.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_VALID_ENABLE_FLAGS htole16(1 << 0)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_VALID_3W_TIMERS htole16(1 << 3)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_VALID_KILL_ACK_MASK htole16(1 << 4)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_VALID_KILL_CTS_MASK htole16(1 << 5)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_VALID_REDUCED_TX_PWR htole16(1 << 6)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_BT_ALL_VALID_MASK (IWN_BT_VALID_ENABLE_FLAGS | \
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_BT_COEX_PRIOTABLE */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_BT_COEX_PROT */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* degK <-> degC conversion macros. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_CTOMUK(c) (((c) * 1000000) + 273150000)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structures for command IWN_CMD_SET_SENSITIVITY. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* "Enhanced" part. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structures for command IWN_CMD_PHY_CALIB. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for IWN_UC_READY notification. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* The following fields are for UCODE_INIT only. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structures for IWN_TX_DONE notification. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for IWN_BEACON_MISSED notification. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for IWN_MPDU_RX_DONE notification. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for IWN_RX_COMPRESSED_BA notification. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for IWN_START_SCAN notification. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for IWN_STOP_SCAN notification. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structure for IWN_SPECTRUM_MEASUREMENT notification. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Structures for IWN_{RX,BEACON}_STATISTICS notification. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Firmware error dump. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* TLV firmware header. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld uint32_t zero; /* Always 0, to differentiate from legacy. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* TLV header. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * enum iwn_ucode_tlv_flag - ucode API flags
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * was a separate TLV but moved here to save space.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * treats good CRC threshold as a boolean
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * offload profile config command.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * (rather than two) IPv6 addresses
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * from the probe request template.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * connection when going back to D0
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * containing CAM (Continuous Active Mode) indication.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Offsets into EEPROM.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Indirect offsets. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for IWN_EEPROM_SKU_CAP. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Possible flags for IWN_EEPROM_RFCFG. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Offsets of channels descriptions in EEPROM.
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* 20MHz channels, 2GHz band. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } },
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* 20MHz channels, 5GHz band. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } },
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } },
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* 40MHz channels (primary channels), 2GHz band. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* 40MHz channels (primary channels), 5GHz band. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } }
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* HW rate indices. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * RF Tx gain values from highest to lowest power (values obtained from
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * the reference driver.)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * DSP pre-DAC gain values from highest to lowest power (values obtained
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * from the reference driver.)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * Power saving settings (values obtained from the reference driver.)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld} iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* DTIM <= 2 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* 3 <= DTIM <= 10 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld /* DTIM >= 11 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld * RX sensitivity limits (values obtained from the reference driver.)
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 120, 120, /* min = max for performance bug in DSP. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 240, 240, /* min = max for performance bug in DSP. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 105, 105, /* min = max for performance bug in DSP. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 220, 220, /* min = max for performance bug in DSP. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const struct iwn_sensitivity_limits iwn2000_sensitivity_limits = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Map TID to TX scheduler's FIFO. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* WiFi/WiMAX coexist event priority table for 6050. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeldstatic const struct iwn5000_wimax_event iwn6050_wimax_events[] = {
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Firmware errors. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "BAD_CHECKSUM",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "NMI_INTERRUPT_WDG",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "FATAL_ERROR",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "BAD_COMMAND",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "HW_ERROR_TUNE_LOCK",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "HW_ERROR_TEMPERATURE",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "ILLEGAL_CHAN_FREQ",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "VCC_NOT_STABLE",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "NMI_INTERRUPT_HOST",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "NMI_INTERRUPT_ACTION_PT",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "NMI_INTERRUPT_UNKNOWN",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "UCODE_VERSION_MISMATCH",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "HW_ERROR_ABS_LOCK",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "HW_ERROR_CAL_LOCK_FAIL",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "NMI_INTERRUPT_INST_ACTION_PT",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "NMI_INTERRUPT_DATA_ACTION_PT",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "NMI_TRM_HW_ER",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "NMI_INTERRUPT_TRM",
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "NMI_INTERRUPT_BREAKPOINT"
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld "ADVANCED_SYSASSERT"
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld/* Find least significant bit that is set. */
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
fd43cf6ea90d0f421f98ca45675340de695681acHans Rosenfeld#endif /* _IF_IWNREG_H */