Searched refs:I915_WRITE (Results 1 - 4 of 4) sorted by relevance

/illumos-gate/usr/src/uts/intel/io/drm/
H A Di915_irq.c70 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
74 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
85 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
89 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
100 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
111 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
122 I915_WRITE(IMR, dev_priv->irq_mask_reg);
132 I915_WRITE(IMR, dev_priv->irq_mask_reg);
155 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
167 I915_WRITE(re
[all...]
H A Di915_dma.c102 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
118 I915_WRITE(HWS_PGA, 0x1ffff000);
125 I915_WRITE(HWS_PGA, 0x1ffff000);
255 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
257 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
899 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
H A Di915_gem.c859 I915_WRITE(PRB0_CTL, 0);
860 I915_WRITE(PRB0_TAIL, 0);
861 I915_WRITE(PRB0_HEAD, 0);
864 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
865 I915_WRITE(PRB0_CTL,
2688 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
2715 I915_WRITE(HWS_PGA, 0x1ffff000);
2769 I915_WRITE(PRB0_CTL, 0);
2770 I915_WRITE(PRB0_HEAD, 0);
2771 I915_WRITE(PRB0_TAI
[all...]
H A Di915_drv.h573 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) macro
651 I915_WRITE(PRB0_TAIL, outring); \
658 I915_WRITE(PRB0_TAIL, outring); \

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