/* BEGIN CSTYLED */
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
*/
/*
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* Copyright (c) 2009, Intel Corporation.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _I915_DRV_H
#define _I915_DRV_H
/* General customization:
*/
#endif
/* Interface history:
*
* 1.1: Original.
* 1.2: Add Power Management
* 1.3: Add vblank support
* 1.4: Fix cmdbuffer path, add heap destroy
* 1.5: Add vblank pipe configuration
* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
* - Support vertical blank on secondary display pipe
*/
#define DRIVER_PATCHLEVEL 0
#if defined(__linux__)
#define I915_HAVE_FENCE
#define I915_HAVE_BUFFER
#endif
typedef struct _drm_i915_ring_buffer {
int tail_mask;
unsigned long Size;
int head;
int tail;
int space;
struct mem_block {
int start;
int size;
};
typedef struct _drm_i915_vbl_swap {
unsigned int plane;
unsigned int sequence;
int flip;
typedef struct s3_i915_private {
struct drm_i915_error_state {
};
typedef struct drm_i915_private {
void *hw_status_page;
unsigned int status_gfx_addr;
unsigned int cpp;
int back_offset;
int front_offset;
int current_page;
int page_flipping;
/** Protects user_irq_refcount and irq_mask_reg */
/** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
int user_irq_refcount;
/** Cached value of IMR to avoid reads in updating the bitfield */
int irq_mask_reg;
/** splitted irq regs for graphics and display engine on IGDNG,
irq_mask_reg is still used for display irq. */
int allow_batchbuffer;
int vblank_pipe;
struct {
/**
* List of objects currently involved in rendering from the
* ringbuffer.
*
* A reference is held on the buffer while on this list.
*/
/**
* List of objects which are not in the ringbuffer but which
* still have a write_domain which needs to be flushed before
* unbinding.
*
* A reference is held on the buffer while on this list.
*/
/**
* LRU list of objects which are not in the ringbuffer and
* are ready to unbind, but are still in the GTT.
*
* A reference is not held on the buffer while on this list,
* as merely being GTT-bound shouldn't prevent its being
* freed, and we'll pull it off the list in the free path.
*/
/**
* List of breadcrumbs associated with GPU requests currently
* outstanding.
*/
/**
* Waiting sequence number, if any
*/
/**
* Last seq seen at irq time
*/
/**
* Flag if the X Server, and thus DRM, is not currently in
* control of the device.
*
* This is set between LeaveVT and EnterVT. It needs to be
* replaced with a semaphore. It also needs to be
* transitioned away from for kernel modesetting.
*/
int suspended;
/**
* Flag if the hardware appears to be wedged.
*
* This is set when attempts to idle the device timeout.
* It prevents command submission from occuring and makes
* every pending request fail
*/
int wedged;
/** Bit 6 swizzling required for X tiling */
/** Bit 6 swizzling required for Y tiling */
} mm;
struct drm_track {
};
/** driver private structure attached to each drm_gem_object */
struct drm_i915_gem_object {
/** Current space allocated to this object in the GTT, if any. */
/**
* This is set if the object is on the active or flushing lists
* (has pending rendering), and is not set if it's on inactive (ready
* to be unbound).
*/
int active;
/**
* This is set if the object has been written to since last bound
* to the GTT
*/
int dirty;
/** AGP memory structure for our GTT binding. */
int agp_mem;
/**
* Current offset of the object in GTT space.
*
* This is the same as gtt_space->start
*/
/** Boolean whether this object has a valid gtt offset. */
int gtt_bound;
/** How many users have pinned this object in GTT space */
int pin_count;
/** Breadcrumb of last rendering to the buffer. */
/** Current tiling mode for the object. */
/**
* Flagging of which individual pages are valid in GEM_DOMAIN_CPU when
* GEM_DOMAIN_CPU is not in the object's read domain.
*/
/** User space pin count and filp owning the pin */
/**
* Used for checking the object doesn't appear more than once
* in an execbuffer object list.
*/
int in_execbuffer;
};
/**
* Request queue structure.
*
* The request queue allows us to note sequence numbers that have been emitted
* and may be associated with active buffers to be retired.
*
* By keeping this list, we can avoid having to do questionable
* sequence-number comparisons on buffer last_rendering_seqnos, and associate
* an emission time with seqnos for tracking how far ahead of the GPU we are.
*/
struct drm_i915_gem_request {
/** GEM sequence number associated with this request. */
/** Time at which this request was emitted, in jiffies. */
unsigned long emitted_jiffies;
/** Cache domains that were flushed at the start of the request. */
};
struct drm_i915_file_private {
struct {
} mm;
};
enum intel_chip_family {
};
extern drm_ioctl_desc_t i915_ioctls[];
extern int i915_max_ioctl;
/* i915_dma.c */
unsigned long arg);
/* i915_irq.c */
extern int i915_irq_emit(DRM_IOCTL_ARGS);
extern int i915_irq_wait(DRM_IOCTL_ARGS);
extern int i915_vblank_swap(DRM_IOCTL_ARGS);
extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS);
extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS);
/* i915_mem.c */
extern int i915_mem_alloc(DRM_IOCTL_ARGS);
extern int i915_mem_free(DRM_IOCTL_ARGS);
extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);
extern void free_block(struct mem_block *);
/* i915_gem.c */
void i915_gem_retire_work_handler(void *dev);
/* i915_gem_tiling.c */
/* i915_gem_debug.c */
/* i915_gem_regdump.c */
#ifdef I915_HAVE_FENCE
/* i915_fence.c */
#endif
#ifdef I915_HAVE_BUFFER
/* i915_buffer.c */
#endif
#define I915_VERBOSE 0
#define I915_RING_VALIDATE 0
#else
#endif
volatile unsigned char *virt;
#define I915_RING_VALIDATE 0
#else
#endif
#if I915_VERBOSE
#define BEGIN_LP_RING(n) do { \
DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
outcount = 0; \
} while (*"\0")
#else
#define BEGIN_LP_RING(n) do { \
outcount = 0; \
} while (*"\0")
#endif
#if I915_VERBOSE
#define OUT_RING(n) do { \
DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
outcount++; \
outring += 4; \
} while (*"\0")
#else
#define OUT_RING(n) do { \
outcount++; \
outring += 4; \
} while (*"\0")
#endif
#if I915_VERBOSE
#define ADVANCE_LP_RING() do { \
} while (*"\0")
#else
#define ADVANCE_LP_RING() do { \
} while (*"\0")
#endif
/* Extended config space */
/* VGA stuff */
/* GR05 */
/* GR06 */
#define VGA_GR_MEM_A0000_AFFFF 0
#define BB1_UNPROTECTED (0<<0)
#ifdef NOPID
#endif
/**
* Reads a dword out of the status page, which is written to from the command
* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
* MI_STORE_DATA_IMM.
*
* The following dwords have a reserved meaning:
* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
* 0x04: ring 0 head pointer
* 0x05: ring 1 head pointer (915-class)
* 0x06: ring 2 head pointer (915-class)
* 0x10-0x1b: Context status DWords (GM45)
* 0x1f: Last written status offset. (GM45)
*
* The area from dword 0x20 to 0x3ff is available for driver usage.
*/
/*
* add here for S3 support
*/
/**
* bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
*/
/**
* The i830 generation, in LVDS mode, defines P1 as the bit number set within
* this field (only one bit may be set).
*/
/* IGDNG */
#define DPLL_FPA1_P1_POST_DIV_SHIFT 0
/*
* Parallel to Serial Load Pulse phase selection.
* Selects the phase for the 10X DPLL clock for the PCIe
* digital display port. The range is 4 to 13; 10 or more
* is just a flip delay. The default is 6
*/
/**
*
* \sa DPLL_MD_UDI_MULTIPLIER_MASK
*/
# define SDVO_MULTIPLIER_SHIFT_VGA 0
/** @defgroup DPLL_MD
* @{
*/
/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
/**
* UDI pixel divider, controlling how many pixels are stuffed into a packet.
*
* Value is pixels minus 1. Must be set to 1 pixel for SDVO.
*/
/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
/**
*
* SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
* clock rate is 10 times the DPLL clock. At low resolution/refresh rate
* modes, the bus rate would be below the limits, so SDVO allows for stuffing
* dummy bytes in the datastream at an increased clock rate, with both sides of
* the link knowing how many bytes are fill.
*
* So, for a mode with a dotclock of 65Mhz, we would want to double the clock
* rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
* set to 130Mhz, and the SDVO multiplier set to 2x in this register and
* through an SDVO command.
*
* This register field has values of multiplication factor minus 1, with
* a maximum multiplier of 5 for SDVO.
*/
* This best be set to the default value (3) or the CRT won't work. No,
* I don't entirely understand what this does...
*/
# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
/** @} */
/*
* Palette registers
*/
/* MCH MMIO space */
/*
* MCHBAR mirror.
*
* This mirrors the MCHBAR MMIO space whose location is determined by
* device 0 function 0's pci config register 0x44 or 0x48 and matches it in
* every way. It is not accessible from the CP register read instructions.
*
*/
/** 915-945 and GM965 MCH register controlling DRAM channel access */
#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
/** 965 MCH register controlling DRAM channel configuration */
/** GM965 GM45 render standby register */
/*
* Cache mode 0 reg.
* - Manipulating render cache behaviour is central
* to the concept of zone rendering, tuning this reg can help avoid
* at beginning and end of scene.
*
* - To change a bit, write to this reg with a mask bit set and the
* bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
*/
/* I830 CRTC registers */
#define DISPLAY_PLANE_DISABLE 0
#define DISPPLANE_GAMMA_DISABLE 0
#define DISPPLANE_STEREO_DISABLE 0
#define DISPPLANE_SEL_PIPE_A 0
#define DISPPLANE_SRC_KEY_DISABLE 0
#define DISPPLANE_NO_LINE_DOUBLE 0
#define DISPPLANE_STEREO_POLARITY_FIRST 0
/* plane B only */
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
#define PIPEACONF_DISABLE 0
#define PIPEACONF_SINGLE_WIDE 0
#define PIPEACONF_PIPE_UNLOCKED 0
#define PIPEACONF_PALETTE 0
#define PIPEBCONF_DISABLE 0
#define PIPEBCONF_DISABLE 0
#define PIPEBCONF_PALETTE 0
/**
* Indicates that all dependencies of the panel are on:
*
* - PLL enabled
* - pipe enabled
*/
/* Framebuffer compression */
/* Framebuffer compression */
#define FBC_CTL_PLANEA (0<<0)
#define PIPE_FRAME_HIGH_SHIFT 0
/* Interrupt bits:
*/
/* GM45+ just has to be different */
/*
* Some BIOS scratch area registers. The 845 (and 830?) store the amount
* of video memory available to the BIOS in SWF1.
*/
/*
* 855 scratch registers.
*/
/* IGDNG */
#define DIGITAL_PORTA_NO_DETECT (0 << 0)
/* refresh rate hardware control */
#define PIPEA_DATA_M1_OFFSET 0
#define PIPEA_DATA_N1_OFFSET 0
#define PIPEA_DATA_M2_OFFSET 0
#define PIPEA_DATA_N2_OFFSET 0
#define PIPEA_LINK_M1_OFFSET 0
#define PIPEA_LINK_N1_OFFSET 0
#define PIPEA_LINK_M2_OFFSET 0
#define PIPEA_LINK_N2_OFFSET 0
/* PIPEB timing regs are same start from 0x61000 */
#define PIPEB_DATA_M1_OFFSET 0
#define PIPEB_DATA_N1_OFFSET 0
#define PIPEB_DATA_M2_OFFSET 0
#define PIPEB_DATA_N2_OFFSET 0
#define PIPEB_LINK_M1_OFFSET 0
#define PIPEB_LINK_N1_OFFSET 0
#define PIPEB_LINK_M2_OFFSET 0
#define PIPEB_LINK_N2_OFFSET 0
/* CPU panel fitter */
/* legacy palette */
/* interrupts */
/* GT interrupt */
/* PCH */
/* south display engine interrupt */
/* digital port hotplug */
#define PORTD_PULSE_DURATION_2ms (0)
#define PORTD_HOTPLUG_NO_DETECT (0)
#define PORTC_PULSE_DURATION_2ms (0)
#define PORTC_HOTPLUG_NO_DETECT (0)
#define PORTB_PULSE_DURATION_2ms (0)
#define PORTB_HOTPLUG_NO_DETECT (0)
#define DREF_SSC4_DISABLE (0)
/* transcoder */
#define TRANS_HACTIVE_SHIFT 0
#define TRANS_HBLANK_START_SHIFT 0
#define TRANS_HSYNC_START_SHIFT 0
#define TRANS_VACTIVE_SHIFT 0
#define TRANS_VBLANK_START_SHIFT 0
#define TRANS_VSYNC_START_SHIFT 0
/* CPU: FDI_TX */
/* IGDNG: hardwired to 1 */
/* both Tx and Rx */
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
/* train, dp width same as FDI_TX */
/* FDI_RX interrupt register format */
/* CRT */
#define ADPA_TRANS_A_SELECT 0
/* or SDVOB */
#define TRANSCODER_A (0)
#define COLOR_FORMAT_8bpc (0)
#define SDVO_ENCODING (0)
#define PANEL_POWER_OFF (0 << 0)
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
*/
#endif /* _I915_DRV_H */