/illumos-gate/usr/src/uts/sun4u/io/pci/ |
H A D | pci_sc.c | 70 DEBUG3(DBG_ATTACH, dip, "sc_create: ctrl=%x, invl=%x, sync=%x\n", 73 DEBUG2(DBG_ATTACH, dip, "sc_create: ctx_invl=%x ctx_match=%x\n", 75 DEBUG3(DBG_ATTACH, dip, 94 DEBUG2(DBG_ATTACH, dip, "sc_create: sync buffer - vaddr=%x paddr=%x\n", 149 DEBUG0(DBG_ATTACH, dip, "sc_configure:\n"); 173 DEBUG1(DBG_ATTACH, dip,
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H A D | pci_iommu.c | 119 DEBUG2(DBG_ATTACH, dip, "iommu_create: ctrl=%p, tsb=%p\n", 121 DEBUG2(DBG_ATTACH, dip, "iommu_create: page_flush=%p, ctx_flush=%p\n", 123 DEBUG2(DBG_ATTACH, dip, "iommu_create: tsb vaddr=%p tsb_paddr=%p\n", 125 DEBUG1(DBG_ATTACH, dip, "iommu_create: allocated size=%x\n", 127 DEBUG2(DBG_ATTACH, dip, "iommu_create: fast tsb tte addr: %x + %x\n", 130 DEBUG3(DBG_ATTACH, dip, 134 DEBUG2(DBG_ATTACH, dip, 238 DEBUG2(DBG_ATTACH, dip, "iommu_configure: iommu_ctl=%08x.%08x\n", 488 DEBUG3(DBG_ATTACH, dip, 507 DEBUG3(DBG_ATTACH, di [all...] |
H A D | pci_debug.c | 44 {DBG_ATTACH, "attach"},
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H A D | pcipsy.c | 360 DEBUG3(DBG_ATTACH, dip, "address (%p,%p,%p)\n", 840 DEBUG2(DBG_ATTACH, dip, "cb_create: ver=%d, mask=%x\n", l, mask); 845 DEBUG0(DBG_ATTACH, dip, "cb_create: psycho pass 1\n"); 897 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s); 899 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg==%x\n", 903 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg==%llx\n", l); 919 DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n", 988 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 996 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg==%llx\n", l); 1009 DEBUG1(DBG_ATTACH, di [all...] |
H A D | pci_ecc.c | 90 DEBUG1(DBG_ATTACH, dip, "ecc_create: csr=%x\n", ecc_p->ecc_csr_pa); 91 DEBUG2(DBG_ATTACH, dip, "ecc_create: ue_afsr=%x, ue_afar=%x\n", 93 DEBUG2(DBG_ATTACH, dip, "ecc_create: ce_afsr=%x, ce_afar=%x\n", 165 DEBUG0(DBG_ATTACH, dip, "ecc_configure: clearing UE and CE errors\n"); 177 DEBUG0(DBG_ATTACH, dip, "ecc_configure: enabling UE CE detection\n");
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H A D | pci.c | 284 DEBUG0(DBG_ATTACH, dip, "DDI_ATTACH\n"); 344 DEBUG0(DBG_ATTACH, dip, "attach success\n"); 365 DEBUG0(DBG_ATTACH, dip, "DDI_RESUME\n"); 378 DEBUG0(DBG_ATTACH, dip, "instance NOT suspended\n"); 391 DEBUG0(DBG_ATTACH, dip, "unsupported attach op\n"); 411 DEBUG0(DBG_ATTACH, dip, "failed - instance not attached\n"); 1393 DEBUG2(DBG_ATTACH, dip, "%s%d hotplug enabled",
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H A D | pci_pbm.c | 111 DEBUG4(DBG_ATTACH, dip, 115 DEBUG1(DBG_ATTACH, dip, "pbm_create: conf=%x\n",
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H A D | pci_ib.c | 89 DEBUG2(DBG_ATTACH, dip, "ib_create: slot_imr=%x, slot_cir=%x\n", 91 DEBUG2(DBG_ATTACH, dip, "ib_create: obio_imr=%x, obio_cir=%x\n", 93 DEBUG2(DBG_ATTACH, dip, "ib_create: upa0_imr=%x, upa1_imr=%x\n", 95 DEBUG3(DBG_ATTACH, dip, 105 DEBUG1(DBG_ATTACH, dip, "ib_create: numproxy=%x\n",
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H A D | pci_util.c | 84 DEBUG2(DBG_ATTACH, dip, "get_pci_properties: bus-range (%x,%x)\n", 115 DEBUG1(DBG_ATTACH, dip, "get_pci_properties: numproxy=%d\n", 121 DEBUG1(DBG_ATTACH, dip, "get_pci_properties: thermal_interrupt=%d\n",
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H A D | pcisch.c | 516 DEBUG4(DBG_ATTACH, dip, "address (%p,%p,%p,%p)\n", 723 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 739 DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n", 850 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 895 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 921 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 930 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg=%x\n", s); 939 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s); 950 DEBUG1(DBG_ATTACH, dip, 972 DEBUG1(DBG_ATTACH, di [all...] |
H A D | pci_pci.c | 471 DEBUG1(DBG_ATTACH, devi,
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/illumos-gate/usr/src/uts/sun4/io/px/ |
H A D | px_debug.h | 37 /* 0 */ DBG_ATTACH, enumerator in enum:__anon9730
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H A D | px_debug.c | 273 DBG(DBG_ATTACH, dip,
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H A D | px.c | 235 DBG(DBG_ATTACH, dip, "DDI_ATTACH\n"); 379 DBG(DBG_ATTACH, dip, "attach success\n"); 403 DBG(DBG_ATTACH, dip, "px_lib_dev_fini failed\n"); 417 DBG(DBG_ATTACH, dip, "DDI_RESUME\n"); 425 DBG(DBG_ATTACH, px_p->px_dip, 440 DBG(DBG_ATTACH, dip, "unsupported attach op\n");
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H A D | px_mmu.c | 71 DBG(DBG_ATTACH, dip, "Getting virtual-dma failed\n");
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H A D | px_util.c | 71 DBG(DBG_ATTACH, dip, "get_px_properties: bus-range (%x,%x)\n",
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/illumos-gate/usr/src/uts/common/io/pciex/ |
H A D | pcieb.c | 384 PCIEB_DEBUG(DBG_ATTACH, devi, "This is not a switch or" 407 PCIEB_DEBUG(DBG_ATTACH, devi, "Failed in pcieb_fm_init\n"); 948 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_supported_types" 958 PCIEB_DEBUG(DBG_ATTACH, dip, "Unable to attach MSI" 976 PCIEB_DEBUG(DBG_ATTACH, dip, 1011 PCIEB_DEBUG(DBG_ATTACH, dip, "pcieb_intr_init: Attaching %s handler\n", 1052 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_nintrs ret:%d" 1057 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0x%x: ddi_intr_get_nintrs: nintrs %d", 1072 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_alloc() ret: %d ask: %d" 1081 PCIEB_DEBUG(DBG_ATTACH, di [all...] |
H A D | pcieb.h | 40 /* 0 */ DBG_ATTACH, enumerator in enum:__anon6440
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/illumos-gate/usr/src/uts/sun4u/sys/pci/ |
H A D | pci_debug.h | 42 #define DBG_ATTACH 0x1ull macro
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/illumos-gate/usr/src/uts/sun4v/io/px/ |
H A D | px_lib4v.c | 96 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 115 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 136 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 144 DBG(DBG_ATTACH, dip, "px_lib_dev_init: " 182 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 191 DBG(DBG_ATTACH, dip, "%s: cannot negotiate hypervisor " 198 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated SDIO API" 209 DBG(DBG_ATTACH, dip, "%s: cannot negotiate SDIO ERR hypervisor " 216 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated SDIO ERR API " 226 DBG(DBG_ATTACH, di [all...] |
/illumos-gate/usr/src/uts/intel/io/pciex/ |
H A D | pcieb_x86.c | 476 PCIEB_DEBUG(DBG_ATTACH, dip, "VID:0x%x DID:0x%x RID:0x%x bdf=0x%x\n", 530 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf:%x mcheck:%d size:%d "
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/illumos-gate/usr/src/uts/sun4u/io/px/ |
H A D | px_lib4u.c | 111 DBG(DBG_ATTACH, dip, "px_lib_map_regs: pxu_p:0x%p, dip 0x%p\n", 140 DBG(DBG_ATTACH, dip, "reg_bank 0x%x address 0x%p\n", 189 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p", dip); 282 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 1359 DBG(DBG_ATTACH, dip, "px_lib_resume: dip 0x%p\n", dip); 2076 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 2086 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 2093 DBG(DBG_ATTACH, dip, "%s%d: Unknown PCI Express Host bridge %s %x\n",
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H A D | px_err.c | 755 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", reg_desc_p->msg, 757 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", reg_desc_p->msg, 759 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", reg_desc_p->msg, 762 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", reg_desc_p->msg,
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/illumos-gate/usr/src/uts/sparc/io/pciex/ |
H A D | pcieb_sparc.c | 359 PCIEB_DEBUG(DBG_ATTACH, dip, "PLX RO Disable : bdf=0x%x port=%d\n",
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