/illumos-gate/usr/src/uts/sun4/os/ |
H A D | machdep.c | 430 * Create interrupt kstats for this CPU. 472 * Delete interrupt kstats for this CPU. 481 * Convert interrupt statistics from CPU ticks to nanoseconds and 554 cpu = CPU; 730 * Because the microstate is only updated when the CPU's state 752 * cpu_intracct[] is used to identify time spent in each CPU 773 * of (now - cpu_mstate_start) by a change in CPU mstate that
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/illumos-gate/usr/src/uts/sun4u/cpu/ |
H A D | opl_olympus_asm.s | 122 SFMMU_CPU_CNUM(%o1, %g1, %g2) ! %g1 = sfmmu cnum on this CPU 210 SFMMU_CPU_CNUM(%g2, %g6, %g3) ! %g6 = sfmmu cnum on this CPU 288 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU 2042 * This function is called for each (enabled) CPU. We use it to 2062 ! initialize CPU registers
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H A D | us3_common_asm.s | 230 SFMMU_CPU_CNUM(%o1, %g1, %g2) ! %g1 = sfmmu cnum on this CPU 317 SFMMU_CPU_CNUM(%g2, %g6, %g3) ! %g6 = sfmmu cnum on this CPU 395 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU 766 * For certain CPU implementations, we have to flush the L2 cache 1139 * interrupt is generated by the CPU to indicate a performance 1195 * the CPU, External Cache, Cheetah Data Switch and system bus. Error 1228 * CPU logout. 1230 * 5) If CPU logout structure is not being used, then: 1232 * 7) Capture Ecache, Dcache and Icache lines in "CPU log out" structure. 1238 * 6) Otherwise, if CPU logou [all...] |
/illumos-gate/usr/src/uts/sun4u/io/pci/ |
H A D | pci_ecc.c | 243 * about the error from the CPU(via ecc_cpu_call(), ecc.c), attempt to 348 ecc_err_p->ecc_aflt.flt_inst = CPU->cpu_id;
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/illumos-gate/usr/src/lib/libumem/common/ |
H A D | umem.c | 55 * * CPU handling 148 * 3. CPU handling 150 * kmem uses the CPU's sequence number to determine which "cpu cache" to 157 * The mechanics of this is all in the CPU(mask) macro. 382 * Time may be an illusion, but CPU cycles aren't. While libumem is designed 385 * a per-CPU lock for each allocation. When contention is low and malloc(3C) 692 uint32_t umem_max_ncpus; /* # of CPU caches. */ 703 size_t umem_failure_log_size; /* failure log [4 pages per CPU] */ 704 size_t umem_slab_log_size; /* slab create log [4 pages per CPU] */ 757 #define CPU(mas macro [all...] |
/illumos-gate/usr/src/uts/sun4/vm/ |
H A D | vm_dep.c | 84 #define CPUSETSIZE() (cpunodes[CPU->cpu_id].ecache_setsize)
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/illumos-gate/usr/src/uts/common/os/ |
H A D | msg.c | 677 CPU_STATS_ADDQ(CPU, sys, msg, 1); /* bump msg send/rcv count */ 1105 CPU_STATS_ADDQ(CPU, sys, msg, 1); /* bump msg send/rcv count */
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H A D | modctl.c | 376 CPU_STATS_ADDQ(CPU, sys, modload, 1); 2691 CPU_STATS_ADDQ(CPU, sys, modload, 1); 2846 CPU_STATS_ADDQ(CPU, sys, modunload, 1); 3840 CPU_STATS_ADDQ(CPU, sys, modunload, 1); 4229 CPU_STATS_ADDQ(CPU, sys, modunload, 1);
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H A D | lwp.c | 1135 } else if (t->t_state == TS_ONPROC && t->t_cpu != CPU) { 1606 if (t->t_cpu != CPU)
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H A D | taskq.c | 111 * number of threads in the taskq in response to CPU online 347 * We register taskq_cpu_setup() to be called whenever a CPU changes state. It 386 * NOTE: Threads are not bound to any CPU and there is absolutely no association 387 * between the bucket and actual thread CPU, so buckets are used only to 389 * to the CPU denoted by a bucket may reduce number of times the job 429 * 2) Each per-CPU bucket has a lock for bucket management. 944 * one processor set, so we only have to update the current CPU. 946 (void) taskq_cpu_setup(CPU_ON, CPU->cpu_id, NULL); 1185 * In a single-CPU case there is only one bucket, so get 1195 uintptr_t h = ((uintptr_t)CPU [all...] |
H A D | priv_defs | 57 Allow a process to access per-CPU hardware performance counters.
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H A D | fm.c | 1185 return (fm_ena_generate_cpu(timestamp, CPU->cpu_id, format));
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H A D | timers.c | 701 if (t->t_state == TS_ONPROC && t->t_cpu != CPU)
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/illumos-gate/usr/src/uts/sun4u/starcat/io/ |
H A D | axq.c | 1283 exp = CPU->cpu_id >> 5; 1284 slot = (CPU->cpu_id >> 3) & 0x1;
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/illumos-gate/usr/src/uts/intel/dtrace/ |
H A D | fasttrap_isa.c | 667 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock; 924 pid_mtx = &cpu_core[CPU->cpu_id].cpuc_pid_lock;
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/illumos-gate/usr/src/uts/i86pc/io/acpi/drmach_acpi/ |
H A D | drmach_acpi.c | 764 (void) strlcpy(stat->type, "CPU Board", sizeof (stat->type)); 906 cmn_err(CE_WARN, "!drmach_init: system has more CPU/memory/IO " 1402 * Disable fast reboot if CPU/MEM/IOH hotplug event happens. 1404 * fast reboot can support CPU/MEM/IOH DR operations in future. 1408 * power-on. When CPU/MEM/IOH hotplug event happens, those 1417 * CPU/MEM/IOH hotplug event happens. This solution should be 1418 * revised when fast reboot is enhanced to support CPU/MEM/IOH 1464 * CPU/memory/IO DR operations will be supported in stages on x86. 1466 * This temporary hook will be removed when all CPU/memory/IO DR 1566 /* allocate cpu id for the CPU devic [all...] |
/illumos-gate/usr/src/uts/sun4u/vm/ |
H A D | mach_kpm.c | 1792 CPUSET_DEL(cpuset, CPU->cpu_id); 2203 CPUSET_DEL(cpuset, CPU->cpu_id);
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/illumos-gate/usr/src/uts/intel/io/acpica/ |
H A D | osl.c | 108 /* CPU mapping data */ 501 if (curthread == CPU->cpu_idle_thread) { 1544 * Return the ACPI device node matching the CPU dev_info node. 1583 uint32_t apicid = cpuid_get_apicid(CPU); 1984 * If we're a uppc system and ACPI device configuration for CPU has 1985 * been disabled, there won't be a CPU map yet because uppc psm doesn't 1987 * as CPU 0 1988 * Assumption: the first CPU returned by
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/illumos-gate/usr/src/uts/common/disp/ |
H A D | cpupart.c | 48 * CPU partitions. cpu_lock protects the CPU partition list, and prevents 83 * Processor sets and CPU partitions are different but related concepts. 85 * sets of CPUs and bind threads exclusively to those sets. A CPU 88 * implemented via a CPU partition, and currently there is a 1-1 91 * numbering for processor sets and CPU partitions is identical. This 94 * CPU partitions. 102 * Find a CPU partition given a processor set ID. 129 * Find a CPU partition given a processor set ID if the processor set 358 * The last CPU i [all...] |
/illumos-gate/usr/src/uts/common/fs/ |
H A D | lookup.c | 233 CPU_STATS_ADDQ(CPU, sys, namei, 1);
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/illumos-gate/usr/src/uts/common/syscall/ |
H A D | sem.c | 880 CPU_STATS_ADDQ(CPU, sys, sema, 1); /* bump semaphore op count */
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/illumos-gate/usr/src/uts/common/vm/ |
H A D | vm_pvn.c | 494 * another CPU could've 554 cpup = CPU; /* get cpup now that CPU cannot change */
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/illumos-gate/usr/src/uts/i86pc/cpu/authenticamd/ |
H A D | authamd_main.c | 201 * - possibly having PCC set (if source CPU) 917 * GART walk errors set UC and possibly PCC (if source CPU) 925 * also set UC and PCC (if src CPU) but the requester gets -1 1005 cpuid_get_procnodes_per_pkg(CPU);
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/illumos-gate/usr/src/uts/i86pc/io/pcplusmp/ |
H A D | apic.c | 203 apic_cpu_ops, /* CPU control interface. */ 293 if (cpuid_have_cr8access(CPU)) 731 /* We know this CPU + BSP started successfully. */ 739 * local APIC mode of the current CPU is MMIO (xAPIC). 748 * CPU has entered x2apic mode. 844 * CPU is busy -- it's the target of 896 * Bind interrupts to the CPU's local APIC. 897 * Interrupts should not be bound to a CPU's local APIC until the CPU 1277 * and it protects apic_get_next_bind_cpu() from a race in which a CPU ca [all...] |
/illumos-gate/usr/src/uts/sun4u/serengeti/os/ |
H A D | serengeti.c | 365 * belongs to this CPU or a different one. 367 if (portid == cpunodes[CPU->cpu_id].portid) 376 * If the memory controller is local to this CPU, we use 401 * here, we know about all the active CPU boards in the system, and we have 452 * Macro for extracting the board number from the CPU id 457 * Return the platform handle for the lgroup containing the given CPU 498 * values equate to one CPU's load and so attempt to spread the 499 * load out across as many lgroups as possible one CPU at a time. 698 * write CPU signatures, so only bother setting it if we 770 return (SG_MAX_CMPS_PER_BD); /* each CPU di [all...] |