03831d35f7499c87d51205817c93e9a8d42c4baestevel * CDDL HEADER START
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The contents of this file are subject to the terms of the
c39996a7c853f35e9cf2fc40b30e0d2eec0e9996stevel * Common Development and Distribution License (the "License").
c39996a7c853f35e9cf2fc40b30e0d2eec0e9996stevel * You may not use this file except in compliance with the License.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
03831d35f7499c87d51205817c93e9a8d42c4baestevel * See the License for the specific language governing permissions
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and limitations under the License.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * When distributing Covered Code, include this CDDL HEADER in each
03831d35f7499c87d51205817c93e9a8d42c4baestevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If applicable, add the following below this CDDL HEADER, with the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * fields enclosed by brackets "[]" replaced with your own identifying
03831d35f7499c87d51205817c93e9a8d42c4baestevel * information: Portions Copyright [yyyy] [name of copyright owner]
03831d35f7499c87d51205817c93e9a8d42c4baestevel * CDDL HEADER END
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Use is subject to license terms.
03831d35f7499c87d51205817c93e9a8d42c4baestevelint (*p2get_mem_unum)(int, uint64_t, char *, int, int *);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* local functions */
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic void cpu_sgn_update(ushort_t sgn, uchar_t state,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Local data.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * iosram_write_ptr is a pointer to iosram_write(). Because of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * kernel dynamic linking, we can't get to the function by name,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * but we can look up its address, and store it in this variable
03831d35f7499c87d51205817c93e9a8d42c4baestevel * We include the extern for iosram_write() here not because we call
03831d35f7499c87d51205817c93e9a8d42c4baestevel * it, but to force compilation errors if its prototype doesn't
03831d35f7499c87d51205817c93e9a8d42c4baestevel * match the prototype of iosram_write_ptr.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The same issues apply to iosram_read() and iosram_read_ptr.
03831d35f7499c87d51205817c93e9a8d42c4baestevelextern int iosram_write (int, uint32_t, caddr_t, uint32_t);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int (*iosram_write_ptr)(int, uint32_t, caddr_t, uint32_t) = NULL;
03831d35f7499c87d51205817c93e9a8d42c4baestevelextern int iosram_read (int, uint32_t, caddr_t, uint32_t);
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int (*iosram_read_ptr)(int, uint32_t, caddr_t, uint32_t) = NULL;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Variable to indicate if the date should be obtained from the SC or not.
03831d35f7499c87d51205817c93e9a8d42c4baestevelint todsg_use_sc = FALSE; /* set the false at the beginning */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Preallocation of spare tsb's for DR
03831d35f7499c87d51205817c93e9a8d42c4baestevel * We don't allocate spares for Wildcat since TSBs should come
03831d35f7499c87d51205817c93e9a8d42c4baestevel * out of memory local to the node.
03831d35f7499c87d51205817c93e9a8d42c4baestevelint serengeti_tsb_spares = (SG_MAX_IO_BDS * SG_SCHIZO_PER_IO_BD *
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuah * sg_max_ncpus is the maximum number of CPUs supported on Serengeti.
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuah * sg_max_ncpus is set to be smaller than NCPU to reduce the amount of
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuah * memory the logs take up until we have a dynamic log memory allocation
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuah * solution.
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuahint sg_max_ncpus = (24 * 2); /* (max # of processors * # of cores/proc) */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * variables to control mailbox message timeouts.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * These can be patched via /etc/system or mdb.
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* cached 'chosen' node_id */
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic void (*sg_ecc_taskq_func)(sbbc_ecc_mbox_t *) = NULL;
03831d35f7499c87d51205817c93e9a8d42c4baestevelstatic int (*sg_ecc_mbox_func)(sbbc_ecc_mbox_t *) = NULL;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Table that maps memory slices to a specific memnode.
03831d35f7499c87d51205817c93e9a8d42c4baestevelplat_dimm_sid_board_t domain_dimm_sids[SG_MAX_CPU_BDS];
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif /* DEBUG */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* tod_module_name should be set to "todsg" from OBP property */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (tod_module_name && (strcmp(tod_module_name, todsg_name) == 0))
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif /* DEBUG */
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* Serengeti does not support forthdebug */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Some DR operations require the system to be sync paused.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Sync pause on Serengeti could potentially take up to 4
03831d35f7499c87d51205817c93e9a8d42c4baestevel * seconds to complete depending on the load on the SC. To
03831d35f7499c87d51205817c93e9a8d42c4baestevel * avoid send_mond panics during such operations, we need to
03831d35f7499c87d51205817c93e9a8d42c4baestevel * increase xc_tick_limit to a larger value on Serengeti by
03831d35f7499c87d51205817c93e9a8d42c4baestevel * setting xc_tick_limit_scale to 5.
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel (int (*)(struct cpu *))modgetsymvalue("sbdp_cpu_poweron", 0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel (int (*)(struct cpu *))modgetsymvalue("sbdp_cpu_poweroff", 0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* Preferred minimum cage size (expressed in pages)... for DR */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Post copies obp into the lowest slice. This requires the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * cage to grow upwards
85f5803819bea86c07827a9544494e4ad327d95ddp kcage_range_init(phys_avail, KCAGE_UP, preferred_cage_size);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* Only note when the cage is off since it should always be on. */
03831d35f7499c87d51205817c93e9a8d42c4baestevel (((uint64_t)(x) + (uint64_t)(a) - 1l) & ~((uint64_t)(a) - 1l)))
03831d35f7499c87d51205817c93e9a8d42c4baestevelupdate_mem_bounds(int brd, uint64_t base, uint64_t sz)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * First see if this board already has a memnode associated
03831d35f7499c87d51205817c93e9a8d42c4baestevel * with it. If not, see if this slice has a memnode. This
03831d35f7499c87d51205817c93e9a8d42c4baestevel * covers the cases where a single slice covers multiple
03831d35f7499c87d51205817c93e9a8d42c4baestevel * boards (cross-board interleaving) and where a single
03831d35f7499c87d51205817c93e9a8d42c4baestevel * board has multiple slices (1+GB DIMMs).
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((mnode = plat_lgrphand_to_mem_node(brd)) == -1) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((mnode = slice_to_memnode[PA_2_SLICE(base)]) == -1)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Align base at 16GB boundary
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Dynamically detect memory slices in the system by decoding
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the cpu memory decoder registers at boot time.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) < 0) ||
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Decode the board number from the MC portid
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The "reg" property returns 4 32-bit values. The first two are
03831d35f7499c87d51205817c93e9a8d42c4baestevel * combined to form a 64-bit address. The second two are for a
03831d35f7499c87d51205817c93e9a8d42c4baestevel * 64-bit size, but we don't actually need to look at that value.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Figure out whether the memory controller we are examining
03831d35f7499c87d51205817c93e9a8d42c4baestevel * belongs to this CPU or a different one.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < SG_MAX_BANKS_PER_MC; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If the memory controller is local to this CPU, we use
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the special ASI to read the decode registers.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Otherwise, we load the values from a magic address in
03831d35f7499c87d51205817c93e9a8d42c4baestevel * I/O space.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The memory decode register is a bitmask field,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * so we can decode that into both a base and
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This routine is run midway through the boot process. By the time we get
03831d35f7499c87d51205817c93e9a8d42c4baestevel * here, we know about all the active CPU boards in the system, and we have
03831d35f7499c87d51205817c93e9a8d42c4baestevel * extracted information about each board's memory from the memory
03831d35f7499c87d51205817c93e9a8d42c4baestevel * controllers. We have also figured out which ranges of memory will be
03831d35f7499c87d51205817c93e9a8d42c4baestevel * assigned to which memnodes, so we walk the slice table to build the table
03831d35f7499c87d51205817c93e9a8d42c4baestevel * of memnodes.
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* ARGSUSED */
986fd29a0dc13f7608ef7f508f6e700bd7bc2720setjeplat_build_mem_nodes(prom_memlist_t *list, size_t nelems)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Serengeti support for lgroups.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * On Serengeti, an lgroup platform handle == board number.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Mappings between lgroup handles and memnodes are managed
03831d35f7499c87d51205817c93e9a8d42c4baestevel * in addition to mappings between memory slices and memnodes
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to support cross-board interleaving as well as multiple
03831d35f7499c87d51205817c93e9a8d42c4baestevel * slices per board (e.g. >1GB DIMMs). The initial mapping
03831d35f7499c87d51205817c93e9a8d42c4baestevel * of memnodes to lgroup handles is determined at boot time.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * A DR addition of memory adds a new mapping. A DR copy-rename
03831d35f7499c87d51205817c93e9a8d42c4baestevel * swaps mappings.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Macro for extracting the board number from the CPU id
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Return the platform handle for the lgroup containing the given CPU
03831d35f7499c87d51205817c93e9a8d42c4baestevel * For Serengeti, lgroup platform handle == board number
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Platform specific lgroup initialization
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Initialize lookup tables to invalid values so we catch
03831d35f7499c87d51205817c93e9a8d42c4baestevel * any illegal use of them.
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < SG_MAX_SLICE; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Set tuneables for Serengeti architecture
03831d35f7499c87d51205817c93e9a8d42c4baestevel * lgrp_expand_proc_thresh is the minimum load on the lgroups
03831d35f7499c87d51205817c93e9a8d42c4baestevel * this process is currently running on before considering
03831d35f7499c87d51205817c93e9a8d42c4baestevel * expanding threads to another lgroup.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * lgrp_expand_proc_diff determines how much less the remote lgroup
03831d35f7499c87d51205817c93e9a8d42c4baestevel * must be loaded before expanding to it.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Bandwidth is maximized on Serengeti by spreading load across
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the machine. The impact to inter-thread communication isn't
03831d35f7499c87d51205817c93e9a8d42c4baestevel * too costly since remote latencies are relatively low. These
03831d35f7499c87d51205817c93e9a8d42c4baestevel * values equate to one CPU's load and so attempt to spread the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * load out across as many lgroups as possible one CPU at a time.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Platform notification of lgroup (re)configuration changes
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevelplat_lgrp_config(lgrp_config_flag_t evt, uintptr_t arg)
03831d35f7499c87d51205817c93e9a8d42c4baestevel update_mem_bounds(umb->u_board, umb->u_base, umb->u_len);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* We don't have to do anything */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * During a DR copy-rename operation, all of the memory
03831d35f7499c87d51205817c93e9a8d42c4baestevel * on one board is moved to another board -- but the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * addresses/pfns and memnodes don't change. This means
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the memory has changed locations without changing identity.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Source is where we are copying from and target is where we
03831d35f7499c87d51205817c93e9a8d42c4baestevel * are copying to. After source memnode is copied to target
03831d35f7499c87d51205817c93e9a8d42c4baestevel * memnode, the physical addresses of the target memnode are
03831d35f7499c87d51205817c93e9a8d42c4baestevel * renamed to match what the source memnode had. Then target
03831d35f7499c87d51205817c93e9a8d42c4baestevel * memnode can be removed and source memnode can take its
03831d35f7499c87d51205817c93e9a8d42c4baestevel * To do this, swap the lgroup handle to memnode mappings for
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the boards, so target lgroup will have source memnode and
03831d35f7499c87d51205817c93e9a8d42c4baestevel * source lgroup will have empty target memnode which is where
03831d35f7499c87d51205817c93e9a8d42c4baestevel * its memory will go (if any is added to it later).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Then source memnode needs to be removed from its lgroup
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and added to the target lgroup where the memory was living
03831d35f7499c87d51205817c93e9a8d42c4baestevel * but under a different name/memnode. The memory was in the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * target memnode and now lives in the source memnode with
03831d35f7499c87d51205817c93e9a8d42c4baestevel * different physical addresses even though it is the same
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Remove source memnode of copy rename from its lgroup
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and add it to its new target lgroup
03831d35f7499c87d51205817c93e9a8d42c4baestevel lgrp_config(LGRP_CONFIG_MEM_RENAME, (uintptr_t)snode,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Return latency between "from" and "to" lgroups
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This latency number can only be used for relative comparison
03831d35f7499c87d51205817c93e9a8d42c4baestevel * between lgroups on the running system, cannot be used across platforms,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * and may not reflect the actual latency. It is platform and implementation
03831d35f7499c87d51205817c93e9a8d42c4baestevel * specific, so platform gets to decide its value. It would be nice if the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * number was at least proportional to make comparisons more meaningful though.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * NOTE: The numbers below are supposed to be load latencies for uncached
03831d35f7499c87d51205817c93e9a8d42c4baestevel * memory divided by 10.
03831d35f7499c87d51205817c93e9a8d42c4baestevelplat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Return min remote latency when there are more than two lgroups
03831d35f7499c87d51205817c93e9a8d42c4baestevel * (root and child) and getting latency between two different lgroups
03831d35f7499c87d51205817c93e9a8d42c4baestevel * or root is involved
03831d35f7499c87d51205817c93e9a8d42c4baestevel from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE))
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (28);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (23);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* ARGSUSED */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Find dip for chosen IOSRAM
03831d35f7499c87d51205817c93e9a8d42c4baestevel * find the /chosen SBBC node, prom interface will handle errors
03831d35f7499c87d51205817c93e9a8d42c4baestevel * get the 'iosram' property from the /chosen node
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (prom_getprop(nodeid, IOSRAM_CHOSEN_PROP, (caddr_t)&tunnel) <= 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (prom_phandle_to_path((phandle_t)tunnel, master_sbbc,
03831d35f7499c87d51205817c93e9a8d42c4baestevel sizeof (master_sbbc)) < 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel SBBC_ERR1(CE_PANIC, "prom_phandle_to_path(%d) failed\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * load and attach the sgsbbc driver.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This will also attach all the sgsbbc driver instances
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (i_ddi_attach_hw_nodes("sgsbbc") != DDI_SUCCESS) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* translate a path name to a dev_info_t */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((dip == NULL) || (ddi_get_nodeid(dip) != tunnel)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_PANIC, "i_ddi_path_to_devi(%x) failed for SBBC\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* make sure devi_ref is ZERO */
03831d35f7499c87d51205817c93e9a8d42c4baestevel DCMNERR(CE_CONT, "Chosen IOSRAM is at %s \n", master_sbbc);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Load and attach the mc-us3 memory driver.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Initialize the chosen IOSRAM before its clients
03831d35f7499c87d51205817c93e9a8d42c4baestevel * are loaded.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Ideally, we'd do this in set_platform_defaults(), but
03831d35f7499c87d51205817c93e9a8d42c4baestevel * at that point it's too early to look up symbols.
03831d35f7499c87d51205817c93e9a8d42c4baestevel iosram_write_ptr = (int (*)(int, uint32_t, caddr_t, uint32_t))
03831d35f7499c87d51205817c93e9a8d42c4baestevel DCMNERR(CE_WARN, "load_platform_defaults: iosram_write()"
03831d35f7499c87d51205817c93e9a8d42c4baestevel " not found; signatures will not be updated\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The iosram read ptr is only needed if we can actually
03831d35f7499c87d51205817c93e9a8d42c4baestevel * write CPU signatures, so only bother setting it if we
03831d35f7499c87d51205817c93e9a8d42c4baestevel * set a valid write pointer, above.
03831d35f7499c87d51205817c93e9a8d42c4baestevel iosram_read_ptr = (int (*)(int, uint32_t, caddr_t, uint32_t))
03831d35f7499c87d51205817c93e9a8d42c4baestevel DCMNERR(CE_WARN, "load_platform_defaults: iosram_read()"
03831d35f7499c87d51205817c93e9a8d42c4baestevel " not found\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Set todsg_use_sc to TRUE so that we will be getting date
03831d35f7499c87d51205817c93e9a8d42c4baestevel * from the SC.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Now is a good time to activate hardware watchdog (if one exists).
03831d35f7499c87d51205817c93e9a8d42c4baestevel ret = tod_ops.tod_set_watchdog_timer(watchdog_timeout_seconds);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Load and attach the schizo pci bus nexus driver.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * No platform drivers on this platform
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (SG_MAX_CMPS_PER_BD); /* each CPU die has a memory controller */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Our nodename has been set, pass it along to the SC.
03831d35f7499c87d51205817c93e9a8d42c4baestevel int (*sg_mbox)(sbbc_msg_t *, sbbc_msg_t *, time_t) = NULL;
03831d35f7499c87d51205817c93e9a8d42c4baestevel * find the symbol for the mailbox routine
03831d35f7499c87d51205817c93e9a8d42c4baestevel sg_mbox = (int (*)(sbbc_msg_t *, sbbc_msg_t *, time_t))
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_NOTE, "!plat_nodename_set: sg_mbox not found\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * construct the message telling the SC our nodename
03831d35f7499c87d51205817c93e9a8d42c4baestevel req.msg_len = (int)(nni.namelen + sizeof (nni.namelen));
03831d35f7499c87d51205817c93e9a8d42c4baestevel * initialize the response back from the SC
03831d35f7499c87d51205817c93e9a8d42c4baestevel * ship it and check for success
03831d35f7499c87d51205817c93e9a8d42c4baestevel rv = (sg_mbox)(&req, &resp, sbbc_mbox_default_timeout);
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (rv != 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_NOTE, "!plat_nodename_set: sg_mbox retval %d\n", rv);
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmn_err(CE_NOTE, "!plat_nodename_set: msg_status %d\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel DCMNERR(CE_NOTE, "!plat_nodename_set was successful\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * It is necessary to exchange the capability bitmap
03831d35f7499c87d51205817c93e9a8d42c4baestevel * with SC before sending any ecc error information and
03831d35f7499c87d51205817c93e9a8d42c4baestevel * indictment. We are calling the plat_ecc_capability_send()
03831d35f7499c87d51205817c93e9a8d42c4baestevel * here just after sending the nodename successfully.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (rv == 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel " successful\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * flag to allow users switch between using OBP's
03831d35f7499c87d51205817c93e9a8d42c4baestevel * prom_get_unum() and mc-us3 driver's p2get_mem_unum()
03831d35f7499c87d51205817c93e9a8d42c4baestevel * (for main memory errors only).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Debugging flag: set to 1 to call into obp for get_unum, or set it to 0
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to call into the unum cache system. This is the E$ equivalent of
03831d35f7499c87d51205817c93e9a8d42c4baestevel * sg_use_prom_get_unum.
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* used for logging ECC errors to the SC */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * plat_get_mem_unum() generates a string identifying either the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * memory or E$ DIMM(s) during error logging. Depending on whether
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the error is E$ or memory related, the appropriate support
03831d35f7499c87d51205817c93e9a8d42c4baestevel * routine is called to assist in the string generation.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * - For main memory errors we can use the mc-us3 drivers p2getunum()
03831d35f7499c87d51205817c93e9a8d42c4baestevel * (or prom_get_unum() for debugging purposes).
03831d35f7499c87d51205817c93e9a8d42c4baestevel * - For E$ errors we call sg_get_ecacheunum() to generate the unum (or
03831d35f7499c87d51205817c93e9a8d42c4baestevel * prom_serengeti_get_ecacheunum() for debugging purposes).
03831d35f7499c87d51205817c93e9a8d42c4baestevelsg_prom_get_unum(int synd_code, uint64_t paddr, char *buf, int buflen,
03831d35f7499c87d51205817c93e9a8d42c4baestevel if ((prom_get_unum(synd_code, (unsigned long long)paddr,
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevelplat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id,
03831d35f7499c87d51205817c93e9a8d42c4baestevel int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * unum_func will either point to the memory drivers p2get_mem_unum()
03831d35f7499c87d51205817c93e9a8d42c4baestevel * or to prom_get_unum() for memory errors.
03831d35f7499c87d51205817c93e9a8d42c4baestevel int (*unum_func)(int synd_code, uint64_t paddr, char *buf,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * check if it's a Memory or an Ecache error.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * It's a main memory error.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * For debugging we allow the user to switch between
03831d35f7499c87d51205817c93e9a8d42c4baestevel * using OBP's get_unum and the memory driver's get_unum
03831d35f7499c87d51205817c93e9a8d42c4baestevel * so we create a pointer to the functions and switch
03831d35f7499c87d51205817c93e9a8d42c4baestevel * depending on the sg_use_prom_get_unum flag.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * It's an E$ error.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * We call to OBP to handle this.
03831d35f7499c87d51205817c93e9a8d42c4baestevel "Using prom_serengeti_get_ecacheunum from OBP");
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This platform hook gets called from mc_add_mem_unum_label() in the mc-us3
03831d35f7499c87d51205817c93e9a8d42c4baestevel * driver giving each platform the opportunity to add platform
03831d35f7499c87d51205817c93e9a8d42c4baestevel * specific label information to the unum for ECC error logging purposes.
03831d35f7499c87d51205817c93e9a8d42c4baestevelplat_add_mem_unum_label(char *unum, int mcid, int bank, int dimm)
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The mc-us3 driver deals with logical banks but for unum
03831d35f7499c87d51205817c93e9a8d42c4baestevel * purposes we need to use physical banks so that the correct
03831d35f7499c87d51205817c93e9a8d42c4baestevel * dimm can be physically located. Logical banks 0 and 2
03831d35f7499c87d51205817c93e9a8d42c4baestevel * make up physical bank 0. Logical banks 1 and 3 make up
03831d35f7499c87d51205817c93e9a8d42c4baestevel * physical bank 1. Here we do the necessary conversion.
03831d35f7499c87d51205817c93e9a8d42c4baestevelplat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp)
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * We log all ECC events to the SC so we send a mailbox
03831d35f7499c87d51205817c93e9a8d42c4baestevel * message to the SC passing it the relevant data.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * ECC mailbox messages are sent via a taskq mechanism to
03831d35f7499c87d51205817c93e9a8d42c4baestevel * prevent impaired system performance during ECC floods.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Indictments have already passed through a taskq, so they
03831d35f7499c87d51205817c93e9a8d42c4baestevel * are not queued here.
03831d35f7499c87d51205817c93e9a8d42c4baestevelplat_send_ecc_mailbox_msg(plat_ecc_message_type_t msg_type, void *datap)
03831d35f7499c87d51205817c93e9a8d42c4baestevel "sbbc_mbox_queue_ecc_event not found");
03831d35f7499c87d51205817c93e9a8d42c4baestevel "sbbc_mbox_ecc_output not found");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Initialize the request and response structures
03831d35f7499c87d51205817c93e9a8d42c4baestevel strlen(utsname.release) + strlen(utsname.version) + 2;
03831d35f7499c87d51205817c93e9a8d42c4baestevel msgp = (sbbc_ecc_mbox_t *)kmem_zalloc(sizeof (sbbc_ecc_mbox_t),
986fd29a0dc13f7608ef7f508f6e700bd7bc2720setje "unable to allocate sbbc_ecc_mbox");
03831d35f7499c87d51205817c93e9a8d42c4baestevel msgp->ecc_req.msg_buf = (caddr_t)kmem_zalloc(msg_size, sleep_flag);
986fd29a0dc13f7608ef7f508f6e700bd7bc2720setje "unable to allocate request msg_buf");
03831d35f7499c87d51205817c93e9a8d42c4baestevel bcopy(datap, (void *)msgp->ecc_req.msg_buf, msg_size);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * initialize the response back from the SC
03831d35f7499c87d51205817c93e9a8d42c4baestevel * For Error Messages, we go through a taskq.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Queue up the message for processing
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * For indictment and capability messages, we've already gone
03831d35f7499c87d51205817c93e9a8d42c4baestevel * through the taskq, so we can call the mailbox routine
03831d35f7499c87d51205817c93e9a8d42c4baestevel * directly. Find the symbol for the routine that sends
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the mailbox msg
03831d35f7499c87d51205817c93e9a8d42c4baestevel msgp->ecc_resp.msg_buf = (caddr_t)kmem_zalloc(msg_size,
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* FALLTHRU */
03831d35f7499c87d51205817c93e9a8d42c4baestevel msgp->ecc_resp.msg_len = sizeof (plat_dimm_sid_board_data_t);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * m is redundant on serengeti as the multiplier is always 4
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel * board number for a given proc
03831d35f7499c87d51205817c93e9a8d42c4baestevelcpu_sgn_update(ushort_t sig, uchar_t state, uchar_t sub_state, int cpuid)
03831d35f7499c87d51205817c93e9a8d42c4baestevel uint32_t signature = CPU_SIG_BLD(sig, state, sub_state);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If the IOSRAM write pointer isn't set, we won't be able
03831d35f7499c87d51205817c93e9a8d42c4baestevel * to write signatures to ANYTHING, so we may as well just
03831d35f7499c87d51205817c93e9a8d42c4baestevel * write out an error message (if desired) and exit this
03831d35f7499c87d51205817c93e9a8d42c4baestevel * routine now...
03831d35f7499c87d51205817c93e9a8d42c4baestevel "cpu_sgn_update: iosram_write() not found;"
03831d35f7499c87d51205817c93e9a8d42c4baestevel " cannot write signature 0x%x for CPU(s) or domain\n",
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Differentiate a panic reboot from a non-panic reboot in the
03831d35f7499c87d51205817c93e9a8d42c4baestevel * setting of the substate of the signature.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * If the new substate is REBOOT and we're rebooting due to a panic,
03831d35f7499c87d51205817c93e9a8d42c4baestevel * then set the new substate to a special value indicating a panic
03831d35f7499c87d51205817c93e9a8d42c4baestevel * reboot, SIGSUBST_PANIC_REBOOT.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * A panic reboot is detected by a current (previous) domain signature
03831d35f7499c87d51205817c93e9a8d42c4baestevel * state of SIGST_EXIT, and a new signature substate of SIGSUBST_REBOOT.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The domain signature state SIGST_EXIT is used as the panic flow
03831d35f7499c87d51205817c93e9a8d42c4baestevel * progresses.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * At the end of the panic flow, the reboot occurs but we should now
03831d35f7499c87d51205817c93e9a8d42c4baestevel * one that was involuntary, something that may be quite useful to know
03831d35f7499c87d51205817c93e9a8d42c4baestevel * at OBP level.
03831d35f7499c87d51205817c93e9a8d42c4baestevel "cpu_sgn_update: iosram_read() not found;"
03831d35f7499c87d51205817c93e9a8d42c4baestevel " could not check current domain signature\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel * cpuid == -1 indicates that the operation applies to all cpus.
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (cpuid >= 0) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel for (i = 0; i < NCPU; i++) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (state == SIGST_OFFLINE || state == SIGST_DETACHED) {
575a742678105d588b7c8e1653b57a7e3d78440bpt /* set per-platform constants for mutex backoff */
03831d35f7499c87d51205817c93e9a8d42c4baestevel * A routine to convert a number (represented as a string) to
03831d35f7499c87d51205817c93e9a8d42c4baestevel * the integer value it represents.
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define isspace(c) ((c) == ' ' || (c) == '\t' || (c) == '\n')
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (!isdigit(c = *p)) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel switch (c) {
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* FALLTHROUGH */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel n *= 10; /* two steps to avoid unnecessary overflow */
03831d35f7499c87d51205817c93e9a8d42c4baestevel n += '0' - c; /* accum neg to avoid surprises at MAX */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (neg ? n : -n);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Get the three parts of the Serengeti PROM version.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Used for feature readiness tests.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Return 0 if version extracted successfully, -1 otherwise.
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel /* Make sure it's an OBP flashprom */
03831d35f7499c87d51205817c93e9a8d42c4baestevel if (vers[0] != 'O' && vers[1] != 'B' && vers[2] != 'P') {
03831d35f7499c87d51205817c93e9a8d42c4baestevel "unknown <version> string in </openprom>\n");
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (-1);
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Return 0 if system board Dynamic Reconfiguration
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is supported by the firmware, -1 otherwise.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Return 0 if cPCI Dynamic Reconfiguration
03831d35f7499c87d51205817c93e9a8d42c4baestevel * is supported by the firmware, -1 otherwise.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The version check is currently the same as for
03831d35f7499c87d51205817c93e9a8d42c4baestevel * system boards. Since the two DR sub-systems are
03831d35f7499c87d51205817c93e9a8d42c4baestevel * independent, this could change.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * KDI functions - used by the in-situ kernel debugger (kmdb) to perform
03831d35f7499c87d51205817c93e9a8d42c4baestevel * platform-specific operations. These functions execute when the world is
03831d35f7499c87d51205817c93e9a8d42c4baestevel * stopped, and as such cannot make any blocking calls, hold locks, etc.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * promif functions are a special case, and may be used.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Our implementation of this KDI op updates the CPU signature in the system
03831d35f7499c87d51205817c93e9a8d42c4baestevel * controller. Note that we set the signature to OBP_SIG, rather than DBG_SIG.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The Forth words we execute will, among other things, transform our OBP_SIG
03831d35f7499c87d51205817c93e9a8d42c4baestevel * into DBG_SIG. They won't function properly if we try to use DBG_SIG.
03831d35f7499c87d51205817c93e9a8d42c4baestevel prom_interpret("sigb-sig! my-sigb-sig!", OBP_SIG, OBP_SIG, 0, 0, 0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel prom_interpret("sigb-sig! my-sigb-sig!", OS_SIG, OS_SIG, 0, 0, 0);
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki (void) prom_serengeti_set_console_input(SGCN_OBP_STR);