Searched defs:pVCpu (Results 1 - 25 of 120) sorted by relevance

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/vbox/src/VBox/VMM/VMMAll/
H A DCPUMStack.cpp33 VMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32) argument
36 pVCpu->cpum.s.Hyper.esp -= sizeof(u32);
37 *(uint32_t *)MMHyperRCToR3(pVCpu->CTXALLSUFF(pVM), (RTRCPTR)pVCpu->cpum.s.Hyper.esp) = u32;
H A DPDMAllCritSectBoth.cpp38 * @param pVCpu Pointer to the VMCPU.
40 VMM_INT_DECL(void) PDMCritSectBothFF(PVMCPU pVCpu) argument
43 Assert( pVCpu->pdm.s.cQueuedCritSectLeaves > 0
44 || pVCpu->pdm.s.cQueuedCritSectRwShrdLeaves > 0
45 || pVCpu->pdm.s.cQueuedCritSectRwExclLeaves > 0);
48 i = pVCpu->pdm.s.cQueuedCritSectRwShrdLeaves;
49 pVCpu->pdm.s.cQueuedCritSectRwShrdLeaves = 0;
53 PPDMCRITSECTRW pCritSectRw = pVCpu->pdm.s.apQueuedCritSectRwShrdLeaves[i];
55 PPDMCRITSECTRW pCritSectRw = (PPDMCRITSECTRW)MMHyperR3ToCC(pVCpu->CTX_SUFF(pVM),
56 pVCpu
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H A DGIMAll.cpp62 * @param pVCpu Pointer to the VMCPU.
64 VMM_INT_DECL(bool) GIMAreHypercallsEnabled(PVMCPU pVCpu) argument
66 PVM pVM = pVCpu->CTX_SUFF(pVM);
73 return gimHvAreHypercallsEnabled(pVCpu);
76 return gimKvmAreHypercallsEnabled(pVCpu);
88 * @param pVCpu Pointer to the VMCPU.
91 VMM_INT_DECL(int) GIMHypercall(PVMCPU pVCpu, PCPUMCTX pCtx) argument
93 PVM pVM = pVCpu->CTX_SUFF(pVM);
94 VMCPU_ASSERT_EMT(pVCpu);
102 return gimHvHypercall(pVCpu, pCt
153 GIMShouldTrapXcptUD(PVMCPU pVCpu) argument
178 GIMXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis) argument
206 GIMReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) argument
241 GIMWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue) argument
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H A DGIMAllHv.cpp41 * @param pVCpu Pointer to the VMCPU.
44 VMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx) argument
46 PVM pVM = pVCpu->CTX_SUFF(pVM);
60 * @param pVCpu Pointer to the VMCPU.
62 VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu) argument
64 return MSR_GIM_HV_HYPERCALL_IS_ENABLED(pVCpu->CTX_SUFF(pVM)->gim.s.u.Hv.u64HypercallMsr);
88 * @param pVCpu Pointer to the VMCPU.
93 VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue) argument
96 PVM pVM = pVCpu->CTX_SUFF(pVM);
104 uint64_t u64Tsc = TMCpuTickGet(pVCpu);
183 gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue) argument
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H A DDBGFAll.cpp172 * @param pVCpu The cross context CPU structure for the calling EMT.
177 VMM_INT_DECL(VBOXSTRICTRC) DBGFBpCheckIo(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTIOPORT uIoPort, uint8_t cbValue) argument
199 pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
200 pVCpu->dbgf.s.fSingleSteppingRaw = false;
261 * @param pVCpu Pointer to the VMCPU.
263 VMM_INT_DECL(bool) DBGFIsStepping(PVMCPU pVCpu) argument
265 return pVCpu->dbgf.s.fSingleSteppingRaw;
H A DREMAll.cpp208 * @param pVCpu Pointer to the VMCPU of the calling EMT.
210 VMMDECL(void) REMNotifyHandlerPhysicalFlushIfAlmostFull(PVM pVM, PVMCPU pVCpu) argument
212 Assert(pVM->cCpus == 1); NOREF(pVCpu);
/vbox/src/VBox/VMM/VMMR0/
H A DTRPMR0.cpp44 PVMCPU pVCpu = VMMGetCpu0(pVM); local
45 RTUINT uActiveVector = pVCpu->trpm.s.uActiveVector;
46 pVCpu->trpm.s.uActiveVector = UINT32_MAX;
H A DHMVMXR0.h31 VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu);
32 VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit);
41 VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu);
42 VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
43 DECLASM(int) VMXR0StartVM32(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
44 DECLASM(int) VMXR0StartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
48 DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
49 VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
55 VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
57 DECLINLINE(int) VMXReadCachedVmcsEx(PVMCPU pVCpu, uint32_ argument
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H A DPGMR0SharedPage.cpp51 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
75 rc = PGMGstGetPage(pVCpu, GCPtrPage, &fFlags, &GCPhys);
110 || ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
111 && (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL)));
/vbox/src/VBox/VMM/VMMR3/
H A DIEMR3.cpp46 PVMCPU pVCpu = &pVM->aCpus[idCpu]; local
47 pVCpu->iem.s.offVM = -RT_OFFSETOF(VM, aCpus[idCpu].iem.s);
48 pVCpu->iem.s.offVMCpu = -RT_OFFSETOF(VMCPU, iem.s);
49 pVCpu->iem.s.pCtxR3 = CPUMQueryGuestCtxPtr(pVCpu);
50 pVCpu->iem.s.pCtxR0 = VM_R0_ADDR(pVM, pVCpu->iem.s.pCtxR3);
51 pVCpu->iem.s.pCtxRC = VM_RC_ADDR(pVM, pVCpu->iem.s.pCtxR3);
53 STAMR3RegisterF(pVM, &pVCpu
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H A DDBGFCpu.cpp45 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu); local
46 *penmMode = CPUMGetGuestMode(pVCpu);
83 PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu); local
84 *pfIn64BitCode = CPUMIsGuestIn64BitCode(pVCpu);
H A DEMHM.cpp63 DECLINLINE(int) emR3HmExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
64 static int emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
65 static int emR3HmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
84 * @param pVCpu Pointer to the cross context CPU structure for
89 VMMR3_INT_DECL(VBOXSTRICTRC) EMR3HmSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags) argument
91 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
104 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
106 VBOXSTRICTRC rcStrict = emR3HmForcedActions(pVM, pVCpu, pCtx);
117 bool fOld = HMSetSingleInstruction(pVCpu, true);
118 VBOXSTRICTRC rcStrict = VMMR3HmRunGC(pVM, pVCpu);
168 emR3HmExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix) argument
244 emR3HmExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC) argument
260 emR3HmExecuteIOInstruction(PVM pVM, PVMCPU pVCpu) argument
390 emR3HmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx) argument
466 emR3HmExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone) argument
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/vbox/src/VBox/VMM/VMMRC/
H A DIOMRC.cpp64 * @param pVCpu Pointer to the virtual CPU structure of the caller.
68 VMMRCDECL(VBOXSTRICTRC) IOMRCIOPortHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu) argument
73 return IOMInterpretIN(pVM, pVCpu, pRegFrame, pCpu);
76 return IOMInterpretOUT(pVM, pVCpu, pRegFrame, pCpu);
80 return IOMInterpretINS(pVM, pVCpu, pRegFrame, pCpu);
84 return IOMInterpretOUTS(pVM, pVCpu, pRegFrame, pCpu);
H A DCPUMRC.cpp92 PVMCPU pVCpu = VMMGetCpu0(pVM); local
93 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
94 uint8_t const uRawCpl = CPUMGetGuestCPL(pVCpu);
95 uint32_t const u32EFlags = CPUMRawGetEFlags(pVCpu);
106 AssertMsg(CPUMIsGuestInRawMode(pVCpu), ("cs:eip=%04x:%08x ss:esp=%04x:%08x cpl=%u raw/efl=%#x/%#x%s\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, uRawCpl, u32EFlags, pCtx->eflags.u, fPatch ? " patch" : ""));
115 * @param pVCpu The current virtual CPU.
121 VMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame) argument
145 if (pVCpu->cpum.s.fRawEntered)
148 && EMIsRawRing1Enabled(pVCpu->CTX_SUFF(pVM)) )
175 * @param pVCpu Pointe
181 CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore) argument
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H A DCSAMRC.cpp69 PVMCPU pVCpu = VMMGetCpu0(pVM); local
93 rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
122 VMCPU_FF_SET(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION);
134 rc = PGMShwMakePageWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
H A DMMRamRC.cpp86 PVMCPU pVCpu = VMMGetCpu0(pVM); local
91 TRPMSaveTrap(pVCpu);
125 TRPMRestoreTrap(pVCpu);
144 PVMCPU pVCpu = VMMGetCpu0(pVM); local
145 TRPMSaveTrap(pVCpu); /* save the current trap info, because it will get trashed if our access failed. */
151 TRPMRestoreTrap(pVCpu);
H A DTRPMRC.cpp83 PVMCPU pVCpu = VMMGetCpu0(pVM); local
86 TRPMResetTrap(pVCpu);
106 PVMCPU pVCpu = VMMGetCpu0(pVM); local
108 RTGCPTR GCPtrIDT = (RTGCPTR)CPUMGetGuestIDTR(pVCpu, &cbIDT);
126 int rc = EMInterpretInstructionEx(pVM, pVCpu, pRegFrame, pvFault, &cb);
148 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
169 PVMCPU pVCpu = VMMGetCpu0(pVM); local
185 int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, NULL);
/vbox/src/VBox/VMM/include/
H A DEMHandleRCTmpl.h36 * @param pVCpu Pointer to the VMCPU.
41 int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc) argument
43 int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
68 rc = emR3RawPrivileged(pVM, pVCpu);
77 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
81 rc = emR3RawGuestTrap(pVM, pVCpu);
89 rc = emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
120 | (CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0));
122 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
127 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMI
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H A DIOMInline.h65 * @param pVCpu Pointer to the virtual CPU structure of the caller.
68 DECLINLINE(PIOMMMIORANGE) iomMmioGetRange(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys) argument
71 PIOMMMIORANGE pRange = pVCpu->iom.s.CTX_SUFF(pMMIORangeLast);
74 pVCpu->iom.s.CTX_SUFF(pMMIORangeLast) = pRange
101 * @param pVCpu Pointer to the virtual CPU structure of the caller.
104 DECLINLINE(PIOMMMIORANGE) iomMmioGetRangeWithRef(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
109 PIOMMMIORANGE pRange = pVCpu->iom.s.CTX_SUFF(pMMIORangeLast);
112 pVCpu->iom.s.CTX_SUFF(pMMIORangeLast) = pRange
144 * @param pVCpu Pointer to the virtual CPU structure of the caller.
147 DECLINLINE(PIOMMMIORANGE) iomMMIOGetRangeUnsafe(PVM pVM, PVMCPU pVCpu, RTGCPHY
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H A DSELMInline.h101 * @param pVCpu The current virtual CPU.
107 DECLINLINE(bool) selmIsGstDescGoodForSReg(PVMCPU pVCpu, PCCPUMSELREG pSReg, PCX86DESC pGstDesc, uint32_t iSReg, uint32_t uCpl) argument
158 || !CPUMIsGuestInRawMode(pVCpu) ) )
164 pGstDesc->Gen.u2Dpl, uCpl, pSReg->Sel & X86_SEL_RPL, CPUMIsGuestInRawMode(pVCpu)));
295 * @param pVCpu The current virtual CPU.
299 DECLINLINE(void) selmLoadHiddenSRegFromGuestDesc(PVMCPU pVCpu, PCPUMSELREG pSReg, PCX86DESC pGstDesc) argument
307 if ((pSReg->ValidSel & 1) && CPUMIsGuestInRawMode(pVCpu))
/vbox/include/VBox/vmm/
H A Diem.h63 VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPU pVCpu); variable
64 VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
65 VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
67 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint32_t *pcbWritten);
68 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, uint64_t OpcodeBytesPC,
70 VMMDECL(VBOXSTRICTRC) IEMExecLots(PVMCPU pVCpu); variable
71 VMMDECL(VBOXSTRICTRC) IEMInjectTrpmEvent(PVMCPU pVCpu); variable
72 VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2,
80 VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPU pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,
82 VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPU pVCpu, uint8_
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H A Dpdmcritsect.h56 VMM_INT_DECL(void) PDMCritSectBothFF(PVMCPU pVCpu); variable
75 VMMDECL(bool) PDMCritSectIsOwnerEx(PCPDMCRITSECT pCritSect, PVMCPU pVCpu);
H A Dtrpm.h71 VMMDECL(int) TRPMQueryTrap(PVMCPU pVCpu, uint8_t *pu8TrapNo, PTRPMEVENT penmType);
72 VMMDECL(uint8_t) TRPMGetTrapNo(PVMCPU pVCpu); variable
73 VMMDECL(RTGCUINT) TRPMGetErrorCode(PVMCPU pVCpu); variable
74 VMMDECL(RTGCUINTPTR) TRPMGetFaultAddress(PVMCPU pVCpu); variable
75 VMMDECL(uint8_t) TRPMGetInstrLength(PVMCPU pVCpu); variable
76 VMMDECL(int) TRPMResetTrap(PVMCPU pVCpu); variable
77 VMMDECL(int) TRPMAssertTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType);
78 VMMDECL(int) TRPMAssertXcptPF(PVMCPU pVCpu, RTGCUINTPTR uCR2, RTGCUINT uErrorCode);
79 VMMDECL(void) TRPMSetErrorCode(PVMCPU pVCpu, RTGCUINT uErrorCode);
80 VMMDECL(void) TRPMSetFaultAddress(PVMCPU pVCpu, RTGCUINTPT
82 VMMDECL(bool) TRPMIsSoftwareInterrupt(PVMCPU pVCpu); variable
83 VMMDECL(bool) TRPMHasTrap(PVMCPU pVCpu); variable
85 VMMDECL(void) TRPMSaveTrap(PVMCPU pVCpu); variable
86 VMMDECL(void) TRPMRestoreTrap(PVMCPU pVCpu); variable
99 VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu); variable
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/vbox/src/VBox/VMM/VMMRZ/
H A DDBGFRZ.cpp41 * @param pVCpu Pointer to the VMCPU.
46 VMMRZ_INT_DECL(int) DBGFRZTrap01Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6, bool fAltStepping) argument
66 pVCpu->dbgf.s.iActiveBp = pVM->dbgf.s.aHwBreakpoints[iBp].iBp;
67 pVCpu->dbgf.s.fSingleSteppingRaw = false;
81 && (fInHyper || pVCpu->dbgf.s.fSingleSteppingRaw || fAltStepping))
83 pVCpu->dbgf.s.fSingleSteppingRaw = false;
111 * @param pVCpu Pointer to the VMCPU.
114 VMMRZ_INT_DECL(int) DBGFRZTrap03Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame) argument
129 int rc = SELMValidateAndConvertCSAddr(pVCpu, pRegFrame->eflags, pRegFrame->ss.Sel, pRegFrame->cs.Sel, &pRegFrame->cs,
144 pVCpu
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H A DVMMRZ.cpp42 * @param pVCpu Pointer to the VMCPU of the calling EMT.
46 VMMRZDECL(int) VMMRZCallRing3(PVM pVM, PVMCPU pVCpu, VMMCALLRING3 enmOperation, uint64_t uArg) argument
48 VMCPU_ASSERT_EMT(pVCpu);
53 if (RT_UNLIKELY( pVCpu->vmm.s.cCallRing3Disabled != 0
72 "VMMRZCallRing3: enmOperation=%d uArg=%#llx idCpu=%#x\n", enmOperation, uArg, pVCpu->idCpu);
75 "VMMRZCallRing3: enmOperation=%d uArg=%#llx idCpu=%#x\n", enmOperation, uArg, pVCpu->idCpu);
83 pVCpu->vmm.s.enmCallRing3Operation = enmOperation;
84 pVCpu->vmm.s.u64CallRing3Arg = uArg;
85 pVCpu->vmm.s.rcCallRing3 = VERR_VMM_RING3_CALL_NO_RC;
90 if (pVCpu
128 VMMRZCallRing3Disable(PVMCPU pVCpu) argument
162 VMMRZCallRing3Enable(PVMCPU pVCpu) argument
194 VMMRZCallRing3IsEnabled(PVMCPU pVCpu) argument
211 VMMRZCallRing3SetNotification(PVMCPU pVCpu, R0PTRTYPE(PFNVMMR0CALLRING3NOTIFICATION) pfnCallback, RTR0PTR pvUser) argument
230 VMMRZCallRing3RemoveNotification(PVMCPU pVCpu) argument
242 VMMRZCallRing3IsNotificationSet(PVMCPU pVCpu) argument
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