/vbox/include/VBox/vmm/ |
H A D | dbgfsel.h | 55 RTSEL Sel; member in struct:DBGFSELINFO
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H A D | cpumctx.h | 50 RTSEL Sel; member in struct:CPUMSELREG 86 && ( (a_pSelReg)->ValidSel == (a_pSelReg)->Sel \ 88 && (a_pSelReg)->ValidSel == ((a_pSelReg)->Sel & X86_SEL_MASK_OFF_RPL) \ 89 && ((a_pSelReg)->Sel & X86_SEL_RPL) == 1 \ 98 && (a_pSelReg)->ValidSel == (a_pSelReg)->Sel )
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H A D | dbgf.h | 68 RTSEL Sel; member in struct:DBGFADDRESS 117 VMMR3DECL(int) DBGFR3AddrFromSelOff(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddress, RTSEL Sel, RTUINTPTR off); 770 * The off member is [e|r]bp and the Sel member is ss. */ 773 * The off member is [e|r]sp and the Sel member is ss. */ 776 * The off member is [e|r]ip and the Sel member is cs. */ 784 * The off member is [e|r]bp and the Sel member is ss. */ 787 * The off member is [e|r]sp and the Sel member is ss. */ 793 * The off member is [e|r]ip and the Sel member is cs. */ 910 VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags, 929 VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPT [all...] |
/vbox/src/VBox/VMM/VMMAll/ |
H A D | SELMAll.cpp | 60 * @param Sel Selector part. 64 VMMDECL(RTGCPTR) SELMToFlatBySel(PVM pVM, RTSEL Sel, RTGCPTR Addr) argument 71 if (!(Sel & X86_SEL_LDT)) 72 Desc = pVM->selm.s.CTX_SUFF(paGdt)[Sel >> X86_SEL_SHIFT]; 77 Desc = paLDT[Sel >> X86_SEL_SHIFT]; 114 uFlat += (uint32_t)pSReg->Sel << 4; 186 *ppvGC = ((uint32_t)pSReg->Sel << 4) + uFlat; 312 * @param Sel Selector part. 321 VMMDECL(int) SELMToFlatBySelEx(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL Sel, RTGCPTR Addr, argument 335 *ppvGC = ((RTGCUINTPTR)Sel << 489 selLoadHiddenSelectorRegFromGuestTable(PVMCPU pVCpu, PCCPUMCTX pCtx, PCPUMSELREG pSReg, RTGCPTR GCPtrDesc, RTSEL const Sel, uint32_t const iSReg) argument 554 RTSEL const Sel = pSReg->Sel; local [all...] |
H A D | IEMAll.cpp | 691 static VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel); 896 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "I32/%u %04x:%08x", pIemCpu->uCpl, pCtx->cs.Sel, pCtx->eip); 899 RTTraceBufAddMsgF(pVCpu->CTX_SUFF(pVM)->CTX_SUFF(hTraceBuf), "I16/%u %04x:%04x", pIemCpu->uCpl, pCtx->cs.Sel, pCtx->eip); 939 AssertMsg(!(GCPtrPC32 & ~(uint32_t)UINT16_MAX) || pIemCpu->enmCpuMode == IEMMODE_32BIT, ("%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip)); 2211 pu16Frame[1] = (uint16_t)pCtx->cs.Sel; 2221 pCtx->cs.Sel = Idte.sel; 2246 pSReg->Sel = 0; 2274 pSReg->Sel = uSel; 2295 pSReg->Sel = uRpl; 2396 pSReg->Sel 4092 iemRaiseGeneralProtectionFaultBySelector(PIEMCPU pIemCpu, RTSEL Sel) argument 4116 iemRaiseSelectorBoundsBySelector(PIEMCPU pIemCpu, RTSEL Sel) argument [all...] |
/vbox/src/VBox/VMM/VMMR3/ |
H A D | DBGFAddr.cpp | 97 * Creates a mixed address from a Sel:off pair. 103 * @param Sel The selector part. 106 VMMR3DECL(int) DBGFR3AddrFromSelOff(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddress, RTSEL Sel, RTUINTPTR off) argument 112 pAddress->Sel = Sel; 114 if (Sel != DBGF_SEL_FLAT) 117 int rc = DBGFR3SelQueryInfo(pUVM, idCpu, Sel, DBGFSELQI_FLAGS_DT_GUEST | DBGFSELQI_FLAGS_DT_ADJ_64BIT_MODE, &SelInfo); 119 rc = DBGFR3SelQueryInfo(pUVM, idCpu, Sel, DBGFSELQI_FLAGS_DT_SHADOW, &SelInfo); 158 pAddress->Sel = pSelInfo->Sel; [all...] |
H A D | DBGFMem.cpp | 385 static DECLCALLBACK(int) dbgfR3SelQueryInfo(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, uint32_t fFlags, PDBGFSELINFO pSelInfo) argument 398 rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, pSelInfo); 418 else if ( Sel == 0 423 pSelInfo->Sel = 0; 438 rc = SELMR3GetShadowSelectorInfo(pVM, Sel, pSelInfo); 462 * @param Sel The selector to get info about. 470 VMMR3DECL(int) DBGFR3SelQueryInfo(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, uint32_t fFlags, PDBGFSELINFO pSelInfo) argument 484 return VMR3ReqPriorityCallWaitU(pUVM, idCpu, (PFNRT)dbgfR3SelQueryInfo, 5, pUVM, idCpu, Sel, fFlags, pSelInfo); 511 unsigned uLevel = RT_MAX(SelCPL & X86_SEL_RPL, pSelInfo->Sel & X86_SEL_RPL);
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H A D | DBGFDisas.cpp | 341 : pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel)) 405 * @param Sel The code selector. This used to determine the 32/16 bit ness and 408 * relative to the base of Sel. 416 dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags, argument 424 * Get the Sel and GCPtr if fFlags requests that. 431 Sel = pCtxCore->cs.Sel; 439 Sel = pCtxCore->cs.Sel; 449 if (pCtxCore->cs.Sel 695 DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags, char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr) argument 790 DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix) argument [all...] |
H A D | SELM.cpp | 1299 RTSEL const Sel = paSReg[iSReg].Sel; local 1300 if (Sel & X86_SEL_MASK_OFF_RPL) 1305 if (!(Sel & X86_SEL_LDT)) 1307 if ((Sel | (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt) 1308 pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT]; 1314 if ((Sel | (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit) 1315 pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT]; 1328 Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel)); 1345 Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel)); 2102 selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo) argument 2263 selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo) argument 2370 SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo) argument 2401 SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo) argument 2458 selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput) argument 2544 SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg) argument [all...] |
/vbox/src/VBox/VMM/testcase/ |
H A D | tstMicro.cpp | 164 RTSEL Sel = (i << 12) + 0x60; local 167 PX86DESC pGDTE = &paGDTEs[Sel >> X86_SEL_SHIFT];
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/vbox/src/VBox/VMM/VMMRC/ |
H A D | SELMRC.cpp | 99 RTSEL Sel = iGDTEntry << X86_SEL_SHIFT; local 105 if ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == Sel 106 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == Sel 107 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == Sel 108 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == Sel 109 || pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == Sel) 113 Log(("selmRCSyncGDTEntry: Sel=%d Desc=%.8Rhxs: detected conflict!!\n", Sel, &Desc)); 118 Log(("selmRCSyncGDTEntry: Sel=%d Desc=%.8Rhxs: potential conflict (still not present)!\n", Sel, [all...] |
/vbox/src/VBox/Debugger/testcase/ |
H A D | tstDBGCStubs.cpp | 30 VMMR3DECL(int) DBGFR3AddrFromSelOff(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddress, RTSEL Sel, RTUINTPTR off) argument 33 if (Sel == 0xbad && off == 0xbad) 37 pAddress->FlatPtr = (uint32_t)(Sel << 4) | off; 39 pAddress->Sel = DBGF_SEL_FLAT; 91 VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags, argument 301 VMMR3DECL(int) DBGFR3SelQueryInfo(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, uint32_t fFlags, PDBGFSELINFO pSelInfo) argument
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/vbox/src/VBox/Debugger/ |
H A D | DBGCEmulateCodeView.cpp | 1649 pFrame->AddrFrame.Sel, 1651 pFrame->AddrReturnFrame.Sel, 1653 (uint32_t)pFrame->AddrReturnPC.Sel, 1667 (uint32_t)pFrame->AddrReturnPC.Sel, 1680 pFrame->AddrReturnFrame.Sel, 1693 , pFrame->AddrPC.Sel, pFrame->AddrPC.off); 1828 rc = DBGCCmdHlpPrintf(pCmdHlp, "%04x %s Sel:Off=%04x:%016RX64 DPL=%d %s %s=%d%s\n", 1843 rc = DBGCCmdHlpPrintf(pCmdHlp, "%04x %s Sel:Off=%04x:%016RX64 DPL=%d %s%s\n", 1983 rc = DBGCCmdHlpPrintf(pCmdHlp, "%04x %s Sel:Off=%04x:%08x DPL=%d %s %s=%d%s\n", 1996 rc = DBGCCmdHlpPrintf(pCmdHlp, "%04x %s Sel 2072 unsigned Sel = (RTSEL)u64; local [all...] |