Searched defs:DPLL (Results 1 - 1 of 1) sorted by relevance

/solaris-x11-s11/open-src/kernel/i915/src/
H A Di915_reg.h1214 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) macro
1263 * Selects the phase for the 10X DPLL clock for the PCIe
1290 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1296 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
2089 * the DPLL semantics change when the LVDS is assigned to that pipe.
2127 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2

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