EMAll.cpp revision 8da94e4d6813b682cdb38eb9b151ada72d91b40e
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * EM - Execution Monitor(/Manager) - All contexts
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * available from http://www.virtualbox.org. This file is free software;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * you can redistribute it and/or modify it under the terms of the GNU
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * General Public License (GPL) as published by the Free Software
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
a16eb14ad7a4b5ef91ddc22d3e8e92d930f736fcvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
1c94c0a63ba68be1a7b2c640e70d7a06464e4fcavboxsync * additional information or have any questions.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync/*******************************************************************************
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync* Header Files *
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync*******************************************************************************/
223cf005b18af2c21352a70693ebaf0582f68ebcvboxsync/*******************************************************************************
223cf005b18af2c21352a70693ebaf0582f68ebcvboxsync* Defined Constants And Macros *
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync*******************************************************************************/
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync/** @def EM_ASSERT_FAULT_RETURN
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Safety check.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Could in theory it misfire on a cross page boundary access...
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Currently disabled because the CSAM (+ PATM) patch monitoring occationally
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * turns up an alias page instead of the original faulting one and annoying the
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * heck out of anyone running a debug build. See @bugref{2609} and @bugref{1931}.
0174432b2b1a760b89840ba696f7ba51def65dddvboxsync# define EM_ASSERT_FAULT_RETURN(expr, rc) AssertReturn(expr, rc)
0174432b2b1a760b89840ba696f7ba51def65dddvboxsync# define EM_ASSERT_FAULT_RETURN(expr, rc) do { } while (0)
7666082b743c5e146a8cee6cc794ff4bc3fd0ffdvboxsync/*******************************************************************************
7666082b743c5e146a8cee6cc794ff4bc3fd0ffdvboxsync* Internal Functions *
7666082b743c5e146a8cee6cc794ff4bc3fd0ffdvboxsync*******************************************************************************/
7666082b743c5e146a8cee6cc794ff4bc3fd0ffdvboxsyncDECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Get the current execution manager status.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns Current status.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Read callback for disassembly function; supports reading bytes that cross a page boundary
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pSrc GC source pointer
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pDest HC destination pointer
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param cb Number of bytes to read
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param dwUserdata Callback specific user data (pCpu)
22e281e75ed636601178296c6daebda8f1d17c59vboxsyncDECLCALLBACK(int) EMReadBytes(RTUINTPTR pSrc, uint8_t *pDest, unsigned cb, void *pvUserdata)
22e281e75ed636601178296c6daebda8f1d17c59vboxsync int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync AssertMsgRC(rc, ("PGMPhysSimpleReadGCPtr failed for pSrc=%VGv cb=%x\n", pSrc, cb));
22e281e75ed636601178296c6daebda8f1d17c59vboxsync# else /* IN_RING3 */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync int rc = PGMPhysSimpleReadGCPtr(pVM, pDest, pSrc, cb);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync if (RT_SUCCESS(PATMR3QueryOpcode(pVM, (RTGCPTR)pSrc + i, &opcode)))
22e281e75ed636601178296c6daebda8f1d17c59vboxsync# endif /* IN_RING3 */
22e281e75ed636601178296c6daebda8f1d17c59vboxsyncDECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE *pCpu, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
22e281e75ed636601178296c6daebda8f1d17c59vboxsync return DISCoreOneEx(InstrGC, pCpu->mode, EMReadBytes, pVM, pCpu, pOpsize);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync#else /* IN_GC */
22e281e75ed636601178296c6daebda8f1d17c59vboxsyncDECLINLINE(int) emDisCoreOne(PVM pVM, DISCPUSTATE *pCpu, RTGCUINTPTR InstrGC, uint32_t *pOpsize)
d1cbbd799d8912978f5146960b6780f387bb414bvboxsync#endif /* IN_GC */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * Disassembles one instruction.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pCtxCore The context core (used for both the mode and instruction).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pCpu Where to return the parsed instruction info.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pcbInstr Where to return the instruction size. (optional)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretDisasOne(PVM pVM, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pCtxCore, pCtxCore->rip, 0, &GCPtrInstr);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("EMInterpretDisasOne: Failed to convert %RTsel:%VGv (cpl=%d) - rc=%Rrc !!\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pCtxCore->cs, pCtxCore->rip, pCtxCore->ss & X86_SEL_RPL, rc));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)GCPtrInstr, pCtxCore, pCpu, pcbInstr);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Disassembles one instruction.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * This is used by internally by the interpreter and by trap/access handlers.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param GCPtrInstr The flat address of the instruction.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pCtxCore The context core (used to determin the cpu mode).
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync * @param pCpu Where to return the parsed instruction info.
a11c569636fa6838bd423f4631a9660a5a84204bvboxsync * @param pcbInstr Where to return the instruction size. (optional)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretDisasOneEx(PVM pVM, RTGCUINTPTR GCPtrInstr, PCCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, unsigned *pcbInstr)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = DISCoreOneEx(GCPtrInstr, SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, (PCPUMSELREGHID)&pCtxCore->csHid),
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("DISCoreOne failed to GCPtrInstr=%VGv rc=%Rrc\n", GCPtrInstr, rc));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interprets the current instruction.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @retval VINF_* Scheduling instructions.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @retval VERR_EM_INTERPRETER Something we can't cope with.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @retval VERR_* Fatal errors.
750d4d0506a38b2e80c997075d40aad474e675fbvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame The register frame.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Updates the EIP if an instruction was executed successfully.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pvFault The fault address (CR2).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pcbSize Size of the write (if applicable).
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * to worry about e.g. invalid modrm combinations (!)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretInstruction(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync LogFlow(("EMInterpretInstruction %VGv fault %VGv\n", pRegFrame->rip, pvFault));
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync int rc = SELMToFlatEx(pVM, DIS_SELREG_CS, pRegFrame, pRegFrame->rip, 0, &pbCode);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Cpu.mode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = emDisCoreOne(pVM, &Cpu, (RTGCUINTPTR)pbCode, &cbOp);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync rc = EMInterpretInstructionCPU(pVM, &Cpu, pRegFrame, pvFault, pcbSize);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync pRegFrame->rip += cbOp; /* Move on to the next instruction. */
42c1972c22e09797b4b24afbd0ec114ed076c37cvboxsync * Interprets the current instruction using the supplied DISCPUSTATE structure.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * EIP is *NOT* updated!
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @retval VINF_* Scheduling instructions. When these are returned, it
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync * starts to get a bit tricky to know whether code was
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * executed or not... We'll address this when it becomes a problem.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @retval VERR_EM_INTERPRETER Something we can't cope with.
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync * @retval VERR_* Fatal errors.
909f4391cc20b4a3a9a2d3f8718084b669663ab2vboxsync * @param pVM The VM handle.
e08de24d4792d31b7f2aac29db5cb8840d940009vboxsync * @param pCpu The disassembler cpu state for the instruction to be interpreted.
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync * @param pRegFrame The register frame. EIP is *NOT* changed!
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * @param pvFault The fault address (CR2).
8a132edc1577cbe2a19cd778c1b2bea6ae5e8515vboxsync * @param pcbSize Size of the write (if applicable).
3ecd8008b81f02a04220705ae0033142af363280vboxsync * @remark Invalid opcode exceptions have a higher priority than GP (see Intel
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Architecture System Developers Manual, Vol 3, 5.5) so we don't need
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * to worry about e.g. invalid modrm combinations (!)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @todo At this time we do NOT check if the instruction overwrites vital information.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Make sure this can't happen!! (will add some assertions/checks later)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_PROFILE_START(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync int rc = emInterpretInstructionCPU(pVM, pCpu, pRegFrame, pvFault, pcbSize);
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync STAM_PROFILE_STOP(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Emulate), a);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretSucceeded));
3ecd8008b81f02a04220705ae0033142af363280vboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InterpretFailed));
b978e5849454446957177fd47ee98609ab0457a6vboxsync * Interpret a port I/O instruction.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code suitable for scheduling.
247b55faa8d054157f2481e68caca36f4dc9542cvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pCtxCore The context core. This will be updated on successful return.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pCpu The instruction to interpret.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param cbOp The size of the instruction.
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync * @remark This may raise exceptions.
22e281e75ed636601178296c6daebda8f1d17c59vboxsyncVMMDECL(int) EMInterpretPortIO(PVM pVM, PCPUMCTXCORE pCtxCore, PDISCPUSTATE pCpu, uint32_t cbOp)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Hand it on to IOM.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncDECLINLINE(int) emRamRead(PVM pVM, void *pDest, RTGCPTR GCSrc, uint32_t cb)
247b55faa8d054157f2481e68caca36f4dc9542cvboxsync int rc = MMGCRamRead(pVM, pDest, (void *)GCSrc, cb);
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync * The page pool cache may end up here in some cases because it
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * flushed one of the shadow mappings used by the trapping
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync * instruction and it either flushed the TLB or the CPU reused it.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsyncDECLINLINE(int) emRamWrite(PVM pVM, RTGCPTR GCDest, void *pSrc, uint32_t cb)
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync int rc = MMGCRamWrite(pVM, (void *)GCDest, pSrc, cb);
533ffcb943c4af2c5fe6385d816d0ba3eda9383bvboxsync * The page pool cache may end up here in some cases because it
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * flushed one of the shadow mappings used by the trapping
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * instruction and it either flushed the TLB or the CPU reused it.
e50404712a2b5234c42bdf9740bddab5729ba188vboxsync * We want to play safe here, verifying that we've got write
b978e5849454446957177fd47ee98609ab0457a6vboxsync * access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
806d0b554daa555364af5f87bc96eccbe760db7avboxsync PGMPhysWrite(pVM, GCPhys + ((RTGCUINTPTR)GCDest & PAGE_OFFSET_MASK), pSrc, cb);
1843553dbdf4e46417158b4c6348c503adf10740vboxsync/* Convert sel:addr to a flat GC address */
1843553dbdf4e46417158b4c6348c503adf10740vboxsyncstatic RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr)
1843553dbdf4e46417158b4c6348c503adf10740vboxsync DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam);
ebbb1f6c7e8bae363a4efda4b35b58c8467d24bcvboxsync return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr);
1843553dbdf4e46417158b4c6348c503adf10740vboxsync * Get the mnemonic for the disassembled instruction.
ebbb1f6c7e8bae363a4efda4b35b58c8467d24bcvboxsync * GC/R0 doesn't include the strings in the DIS tables because
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync * of limited space.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync case OP_CMPXCHG: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg" : "CmpXchg";
6ae4b1c72625a8e5c369effea7f018b578d733c4vboxsync case OP_CMPXCHG8B: return pCpu->prefix & PREFIX_LOCK ? "Lock CmpXchg8b" : "CmpXchg8b";
0e77737b0ba913683e614db11463b31ca67aacbevboxsync Log(("Unknown opcode %d\n", pCpu->pCurInstr->opcode));
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync return "???";
0e77737b0ba913683e614db11463b31ca67aacbevboxsync#endif /* VBOX_STRICT || LOG_ENABLED */
2d53f6e472561965d363674e17f48d3bdffc24d3vboxsync * XCHG instruction emulation.
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsyncstatic int emInterpretXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
b74ca013e5f201a2dd371e6c438433ceac12af30vboxsync /* Source to make DISQueryParamVal read the register value - ugly hack */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
2d53f6e472561965d363674e17f48d3bdffc24d3vboxsync rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, ¶m2, PARAM_SOURCE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
b978e5849454446957177fd47ee98609ab0457a6vboxsync case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
42c1972c22e09797b4b24afbd0ec114ed076c37cvboxsync pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
806d0b554daa555364af5f87bc96eccbe760db7avboxsync rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
d98e61ba075ed7d0b567a5d884bc85d643fe3de7vboxsync pParam2 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pParam2);
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync EM_ASSERT_FAULT_RETURN(pParam2 == pvFault, VERR_EM_INTERPRETER);
806d0b554daa555364af5f87bc96eccbe760db7avboxsync rc = emRamRead(pVM, &valpar2, pParam2, param2.size);
e08de24d4792d31b7f2aac29db5cb8840d940009vboxsync AssertMsgFailed(("MMGCRamRead %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /* Write value of parameter 2 to parameter 1 (reg or memory address) */
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync Assert(param1.type == PARMTYPE_IMMEDIATE); /* register actually */
806d0b554daa555364af5f87bc96eccbe760db7avboxsync rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t )valpar2); break;
22e281e75ed636601178296c6daebda8f1d17c59vboxsync case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)valpar2); break;
806d0b554daa555364af5f87bc96eccbe760db7avboxsync case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)valpar2); break;
806d0b554daa555364af5f87bc96eccbe760db7avboxsync case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, valpar2); break;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = emRamWrite(pVM, pParam1, &valpar2, param1.size);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
6ae4b1c72625a8e5c369effea7f018b578d733c4vboxsync /* Write value of parameter 1 to parameter 2 (reg or memory address) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(param2.type == PARMTYPE_IMMEDIATE); /* register actually */
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync rc = DISWriteReg8(pRegFrame, pCpu->param2.base.reg_gen, (uint8_t )valpar1); break;
22e281e75ed636601178296c6daebda8f1d17c59vboxsync case 2: rc = DISWriteReg16(pRegFrame, pCpu->param2.base.reg_gen, (uint16_t)valpar1); break;
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync case 4: rc = DISWriteReg32(pRegFrame, pCpu->param2.base.reg_gen, (uint32_t)valpar1); break;
b978e5849454446957177fd47ee98609ab0457a6vboxsync case 8: rc = DISWriteReg64(pRegFrame, pCpu->param2.base.reg_gen, valpar1); break;
806d0b554daa555364af5f87bc96eccbe760db7avboxsync rc = emRamWrite(pVM, pParam2, &valpar1, param2.size);
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
6ae4b1c72625a8e5c369effea7f018b578d733c4vboxsync * INC and DEC emulation.
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsyncstatic int emInterpretIncDec(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
79b24ef0ab7cd4a03a3571b3954c52ab8b573137vboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_DEST);
57399ab65e2825c324fb9dcb4642d4ae2c232509vboxsync pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /* Safety check (in theory it could cross a page boundary and fault there though) */
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync AssertReturn(pParam1 == pvFault, VERR_EM_INTERPRETER);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
7bae75e0b207aa4d4cad2a951271ad1a0e8ab9fdvboxsync AssertMsgFailed(("emRamRead %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
7082d29724f6c3788977a51591b0379fd3acbf72vboxsync /* Write result back */
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /* Update guest's eflags and finish. */
f827fea1108b8f8a1a5f63318f6ec3cf4a9e7010vboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync | (eflags & (X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
42c1972c22e09797b4b24afbd0ec114ed076c37cvboxsync /* All done! */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync * POP Emulation.
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsyncstatic int emInterpretPop(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
6ae4b1c72625a8e5c369effea7f018b578d733c4vboxsync Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_DEST);
42c1972c22e09797b4b24afbd0ec114ed076c37cvboxsync /* Read stack value first */
e0b9d3c357adf9b7d05f55540e86f22943fc4b23vboxsync if (SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid) == CPUMODE_16BIT)
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync return VERR_EM_INTERPRETER; /* No legacy 16 bits stuff here, please. */
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync /* Convert address; don't bother checking limits etc, as we only read here */
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp);
6f0193f5a9287559d34a75f438c2682d8fb08038vboxsync rc = emRamRead(pVM, &valpar1, pStackVal, param1.size);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync AssertMsgFailed(("emRamRead %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync /* pop [esp+xx] uses esp after the actual pop! */
f9147fe1eaa4e35287f8f39282c7f92f0d7de0b7vboxsync && (pCpu->param1.flags & (USE_REG_GEN16|USE_REG_GEN32))
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + param1.size);
22e281e75ed636601178296c6daebda8f1d17c59vboxsync pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync EM_ASSERT_FAULT_RETURN(pParam1 == pvFault || (RTGCPTR)pRegFrame->esp == pvFault, VERR_EM_INTERPRETER);
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync AssertMsgFailed(("emRamWrite %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /* Update ESP as the last step */
13ba5527caaa9b8c4fee29f22e374fa67c4c6f72vboxsync /* All done! */
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync * XOR/OR/AND Emulation.
46df4404c8dbbf3672e7aae8cd0b2770356e5b73vboxsyncstatic int emInterpretOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_DEST);
46df4404c8dbbf3672e7aae8cd0b2770356e5b73vboxsync rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, ¶m2, PARAM_SOURCE);
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
3dde2f85d4cf477621a3128887a2c08a8bca7c01vboxsync /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
46df4404c8dbbf3672e7aae8cd0b2770356e5b73vboxsync /* The destination is always a virtual address */
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync AssertMsgFailed(("emRamRead %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync /* Register or immediate data */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync LogFlow(("emInterpretOrXorAnd %s %VGv %RX64 - %RX64 size %d (%d)\n", emGetMnemonic(pCpu), pParam1, valpar1, valpar2, param2.size, param1.size));
585f64d6f624f9e683321dabeb21b0eb2e6aa473vboxsync /* Data read, emulate instruction. */
65b61798a61dd4c32cce448db1dac70bba8d5cf5vboxsync uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("emInterpretOrXorAnd %s result %RX64\n", emGetMnemonic(pCpu), valpar1));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Update guest's eflags and finish. */
22e281e75ed636601178296c6daebda8f1d17c59vboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* And write it back */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* All done! */
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync * LOCK XOR/OR/AND Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_DEST);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, ¶m2, PARAM_SOURCE);
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync AssertMsgReturn(pCpu->param1.size >= pCpu->param2.size, /* should never happen! */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync ("%s at %VGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), pRegFrame->rip, pCpu->param1.size, pCpu->param2.size),
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* The destination is always a virtual address */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertReturn(param1.type == PARMTYPE_ADDRESS, VERR_EM_INTERPRETER);
e9a217d585085a6a6d129d27ca0d96a1b8e6d0eevboxsync GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Safety check (in theory it could cross a page boundary and fault there though) */
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync EM_ASSERT_FAULT_RETURN(GCPtrPar1 == pvFault, VERR_EM_INTERPRETER);
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync /* Register and immediate data == PARMTYPE_IMMEDIATE */
08bc90fc2848c80bf8270bedc883745b8398e186vboxsync AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
e17bd6c32a8dd64f2d42838f9028216465e2caf0vboxsync /* Try emulate it with a one-shot #PF handler in place. */
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync Log2(("%s %VGv imm%d=%RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
5ace91141404400247438502a84a418fba00c8cfvboxsync rc = pfnEmulate(pvParam1, ValPar2, pCpu->param2.size, &eflags);
49748bb305bd71f672cd083af208f4bb08c5d6abvboxsync Log(("%s %VGv imm%d=%RX64-> emulation failed due to page fault!\n", emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Update guest's eflags and finish. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * ADD, ADC & SUB Emulation.
b9ca93dd1ad44cb8b27679dc5624be2f7b7f7af5vboxsyncstatic int emInterpretAddSub(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
b9ca93dd1ad44cb8b27679dc5624be2f7b7f7af5vboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_DEST);
8b984478b755f4d3091b977d9beac9fb7434279fvboxsync rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, ¶m2, PARAM_SOURCE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("%s at %VGv parameter mismatch %d vs %d!!\n", emGetMnemonic(pCpu), pRegFrame->rip, pCpu->param1.size, pCpu->param2.size)); /* should never happen! */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Or %Ev, Ib -> just a hack to save some space; the data width of the 1st parameter determines the real width */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* The destination is always a virtual address */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync EM_ASSERT_FAULT_RETURN(pParam1 == pvFault, VERR_EM_INTERPRETER);
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync rc = emRamRead(pVM, &valpar1, pParam1, param1.size);
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync AssertMsgFailed(("emRamRead %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Register or immediate data */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Data read, emulate instruction. */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync uint32_t eflags = pfnEmulate(&valpar1, valpar2, param2.size);
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Update guest's eflags and finish. */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* And write it back */
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync rc = emRamWrite(pVM, pParam1, &valpar1, param1.size);
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* All done! */
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync * ADC Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretAdc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdcWithCarrySet);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return emInterpretAddSub(pVM, pCpu, pRegFrame, pvFault, pcbSize, EMEmulateAdd);
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync * BTR/C/S Emulation.
5ace91141404400247438502a84a418fba00c8cfvboxsyncstatic int emInterpretBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize,
5ace91141404400247438502a84a418fba00c8cfvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_DEST);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, ¶m2, PARAM_SOURCE);
78a205e3fc6719d59e8c561b3d287d3a4f879852vboxsync /* The destination is always a virtual address */
42c1972c22e09797b4b24afbd0ec114ed076c37cvboxsync pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pParam1);
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync /* Register or immediate data */
7e960d3a0a8a3a84d7aba2cca45d72b1c31cc97bvboxsync case PARMTYPE_IMMEDIATE: /* both immediate data and register (ugly) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("emInterpret%s: pvFault=%VGv pParam1=%VGv val2=%x\n", emGetMnemonic(pCpu), pvFault, pParam1, valpar2));
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync pParam1 = (RTGCPTR)((RTGCUINTPTR)pParam1 + valpar2/8);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)pParam1 & ~3) == pvFault, VERR_EM_INTERPRETER);
5cf54b3ffeb7ee90685dcaec329ef71a729f5947vboxsync AssertMsgFailed(("emRamRead %VGv size=%d failed with %Rrc\n", pParam1, param1.size, rc));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Data read, emulate bit test instruction. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("emInterpretBtx: val=%x CF=%d\n", valpar1, !!(eflags & X86_EFL_CF)));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Update guest's eflags and finish. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
42c1972c22e09797b4b24afbd0ec114ed076c37cvboxsync | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* And write it back */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* All done! */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * LOCK BTR/C/S Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
0975ae0a0fb615c945150c48e4a73187c1f4f84dvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_DEST);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, ¶m2, PARAM_SOURCE);
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync /* The destination is always a virtual address */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Register and immediate data == PARMTYPE_IMMEDIATE */
3e6d3b0af632bdcd931b5149915c7b8be1a732cdvboxsync AssertReturn(param2.type == PARMTYPE_IMMEDIATE, VERR_EM_INTERPRETER);
5b6e2c9a765c3c72295acc15791af8a700746956vboxsync /* Adjust the parameters so what we're dealing with is a bit within the byte pointed to. */
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync Log2(("emInterpretLockBitTest %s: pvFault=%VGv GCPtrPar1=%VGv imm=%RX64\n", emGetMnemonic(pCpu), pvFault, GCPtrPar1, ValPar2));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync EM_ASSERT_FAULT_RETURN((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, VERR_EM_INTERPRETER);
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync /* Try emulate it with a one-shot #PF handler in place. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n",
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log2(("emInterpretLockBitTest %s: GCPtrPar1=%VGv imm=%VX64 CF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, ValPar2, !!(eflags & X86_EFL_CF)));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Update guest's eflags and finish. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * MOV emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretMov(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_DEST);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, ¶m2, PARAM_SOURCE);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /** @todo Make this the default and don't rely on TRPM information. */
6778b34cb96bef0fef23ebc461eb6a429d2907c5vboxsync /* fallthru */
614cbe11a7e5588dc8d369e223174b1441a09359vboxsync pDest = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, pDest);
614cbe11a7e5588dc8d369e223174b1441a09359vboxsync case PARMTYPE_IMMEDIATE: /* register type is translated to this one too */
d4b98dbce4cf7b3694b62d62a47553d399718dccvboxsync Log(("emInterpretMov: unexpected type=%d eip=%VGv\n", param2.type, pRegFrame->rip));
b6d0062d24490dd07b4a424e5809b3b2bc910c5avboxsync LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %RX64 (%d) &val64=%RHv\n", pRegFrame->rip, pDest, val64, param2.size, &val64));
b6d0062d24490dd07b4a424e5809b3b2bc910c5avboxsync LogFlow(("EMInterpretInstruction at %VGv: OP_MOV %VGv <- %08X (%d) &val64=%RHv\n", pRegFrame->rip, pDest, (uint32_t)val64, param2.size, &val64));
d4b98dbce4cf7b3694b62d62a47553d399718dccvboxsync EM_ASSERT_FAULT_RETURN(pDest == pvFault, VERR_EM_INTERPRETER);
fd69ca9bd8b533bfa9ade45c1c2ff3116854e84avboxsync { /* read fault */
b978e5849454446957177fd47ee98609ab0457a6vboxsync /* Source */
5ace91141404400247438502a84a418fba00c8cfvboxsync /* fallthru */
5ace91141404400247438502a84a418fba00c8cfvboxsync pSrc = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param2, pSrc);
5a12b9772d9cf396a0ba7f54db399817ba7a65bavboxsync EM_ASSERT_FAULT_RETURN(pSrc == pvFault, VERR_EM_INTERPRETER);
5ace91141404400247438502a84a418fba00c8cfvboxsync /* Destination */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case 1: rc = DISWriteReg8(pRegFrame, pCpu->param1.base.reg_gen, (uint8_t) val64); break;
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync case 2: rc = DISWriteReg16(pRegFrame, pCpu->param1.base.reg_gen, (uint16_t)val64); break;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync case 4: rc = DISWriteReg32(pRegFrame, pCpu->param1.base.reg_gen, (uint32_t)val64); break;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync case 8: rc = DISWriteReg64(pRegFrame, pCpu->param1.base.reg_gen, val64); break;
3cbb4f9a6a320e58ed398ef7aaa004cc8727abc5vboxsync LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %RX64 (%d)\n", pSrc, val64, param1.size));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync LogFlow(("EMInterpretInstruction: OP_MOV %VGv -> %08X (%d)\n", pSrc, (uint32_t)val64, param1.size));
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync * [REP] STOSWD emulation
1fb9c510656583ba12872e082125263a58d9bc6bvboxsyncstatic int emInterpretStosWD(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync /* Don't support any but these three prefix bytes. */
1fb9c510656583ba12872e082125263a58d9bc6bvboxsync if ((pCpu->prefix & ~(PREFIX_ADDRSIZE|PREFIX_OPSIZE|PREFIX_REP|PREFIX_REX)))
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync GCDest = SELMToFlat(pVM, DIS_SELREG_ES, pRegFrame, GCOffset);
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync offIncrement = pRegFrame->eflags.Bits.u1DF ? -(signed)cbSize : (signed)cbSize;
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync LogFlow(("emInterpretStosWD dest=%04X:%VGv (%VGv) cbSize=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize));
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
09e2f92b8f54aa362088e216007b53ecdb42e283vboxsync /* Update (e/r)di. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync LogFlow(("emInterpretStosWD dest=%04X:%VGv (%VGv) cbSize=%d cTransfers=%x DF=%d\n", pRegFrame->es, GCOffset, GCDest, cbSize, cTransfers, pRegFrame->eflags.Bits.u1DF));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Access verification first; we currently can't recover properly from traps inside this instruction */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = PGMVerifyAccess(pVM, GCDest - (offIncrement > 0) ? 0 : ((cTransfers-1) * cbSize), cTransfers * cbSize, X86_PTE_RW | X86_PTE_US);
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync Log(("STOSWD will generate a trap -> recompiler, rc=%d\n", rc));
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync /* REP case */
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync rc = PGMPhysWriteGCPtr(pVM, GCDest, &pRegFrame->rax, cbSize);
74735ec6edd6640eebac8885fbb2dadc86b89cf5vboxsync /* Update the registers. */
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync#endif /* !IN_GC */
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync * [LOCK] CMPXCHG emulation.
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsyncstatic int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync /* Source to make DISQueryParamVal read the register value - ugly hack */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
ac6ddb9d00c1da301dfa25b0961dbd58b5f2f6e8vboxsync rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, ¶m2, PARAM_SOURCE);
4b808cd07fd33b8a3edd0588dc43615686deb0e3vboxsync AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
b5b12033c1f7eaf82b038f06e2b9e464b9ddd8d2vboxsync GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
4584ef6026a823006bea5acbeb13dc4efe50da69vboxsync LogFlow(("%s %VGv rax=%RX64 %RX64\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar));
4584ef6026a823006bea5acbeb13dc4efe50da69vboxsync eflags = EMEmulateLockCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync LogFlow(("%s %VGv rax=%RX64 %RX64 ZF=%d\n", emGetMnemonic(pCpu), GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync /* Update guest's eflags and finish. */
e17f587595bd5d3a7be56a892e3fd3a0ef83d268vboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync * [LOCK] CMPXCHG8B emulation.
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsyncstatic int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync /* Source to make DISQueryParamVal read the register value - ugly hack */
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync GCPtrPar1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, GCPtrPar1);
13b9db9ae2c12b6c4e00eda5c79772d57a0d29e1vboxsync rc = PGMPhysGCPtr2HCPtr(pVM, GCPtrPar1, &pvParam1);
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync LogFlow(("%s %VGv=%08x eax=%08x\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax));
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync eflags = EMEmulateLockCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync eflags = EMEmulateCmpXchg8b(pvParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx);
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync LogFlow(("%s %VGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pvParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Update guest's eflags and finish; note that *only* ZF is affected. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
4584ef6026a823006bea5acbeb13dc4efe50da69vboxsync#else /* IN_GC */
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync * [LOCK] CMPXCHG emulation.
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsyncstatic int emInterpretCmpXchg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync /* Source to make DISQueryParamVal read the register value - ugly hack */
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param2, ¶m2, PARAM_SOURCE);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync LogFlow(("%s %VRv eax=%08x %08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync rc = EMGCEmulateLockCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = EMGCEmulateCmpXchg(pParam1, &pRegFrame->eax, valpar, pCpu->param2.size, &eflags);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Log(("%s %VGv eax=%08x %08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync LogFlow(("%s %VRv eax=%08x %08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, valpar, !!(eflags & X86_EFL_ZF)));
3ecd8008b81f02a04220705ae0033142af363280vboxsync /* Update guest's eflags and finish. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync * [LOCK] CMPXCHG8B emulation.
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsyncstatic int emInterpretCmpXchg8b(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync /* Source to make DISQueryParamVal read the register value - ugly hack */
1171e4fb031146163c9a5a66bd9cbf3f2a5acdb6vboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync AssertReturn(pCpu->param1.size == 8, VERR_EM_INTERPRETER);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync LogFlow(("%s %VRv=%08x eax=%08x\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
9b726ba798aabd1a27863e6f5cfeef1393bd198dvboxsync rc = EMGCEmulateLockCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
9b726ba798aabd1a27863e6f5cfeef1393bd198dvboxsync rc = EMGCEmulateCmpXchg8b(pParam1, &pRegFrame->eax, &pRegFrame->edx, pRegFrame->ebx, pRegFrame->ecx, &eflags);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Log(("%s %VGv=%08x eax=%08x -> emulation failed due to page fault!\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync LogFlow(("%s %VGv=%08x eax=%08x ZF=%d\n", emGetMnemonic(pCpu), pParam1, pRegFrame->eax, !!(eflags & X86_EFL_ZF)));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Update guest's eflags and finish; note that *only* ZF is affected. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_ZF))
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync#endif /* IN_GC */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync * [LOCK] XADD emulation.
e8f172f2032e21b4be9a8f3df20e8ef689c6a6favboxsyncstatic int emInterpretXAdd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
e8f172f2032e21b4be9a8f3df20e8ef689c6a6favboxsync Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
2b5a4cf3d77ab62dcbd882115b6d497547b20d29vboxsync /* Source to make DISQueryParamVal read the register value - ugly hack */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = DISQueryParamRegPtr(pRegFrame, pCpu, &pCpu->param2, (void **)&pParamReg2, &cbSizeParamReg2);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync AssertReturn(pCpu->param1.size == pCpu->param2.size, VERR_EM_INTERPRETER);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync pParam1 = (RTRCPTR)emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, (RTGCPTR)(RTRCUINTPTR)pParam1);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync EM_ASSERT_FAULT_RETURN(pParam1 == (RTRCPTR)pvFault, VERR_EM_INTERPRETER);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync LogFlow(("XAdd %VRv=%08x reg=%08x\n", pParam1, *pParamReg2));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = EMGCEmulateLockXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = EMGCEmulateXAdd(pParam1, pParamReg2, cbSizeParamReg2, &eflags);
d41220dff1068effe66bb6a11f444811ba58de40vboxsync Log(("XAdd %VGv reg=%08x -> emulation failed due to page fault!\n", pParam1, *pParamReg2));
d41220dff1068effe66bb6a11f444811ba58de40vboxsync LogFlow(("XAdd %VGv reg=%08x ZF=%d\n", pParam1, *pParamReg2, !!(eflags & X86_EFL_ZF)));
d41220dff1068effe66bb6a11f444811ba58de40vboxsync /* Update guest's eflags and finish. */
d41220dff1068effe66bb6a11f444811ba58de40vboxsync pRegFrame->eflags.u32 = (pRegFrame->eflags.u32 & ~(X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF))
90466ec66c4fa6a8cd62f01fbf141b51189d33cbvboxsync | (eflags & (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF));
d41220dff1068effe66bb6a11f444811ba58de40vboxsync#endif /* IN_GC */
d41220dff1068effe66bb6a11f444811ba58de40vboxsync * Interpret IRET (currently only to V86 code)
d41220dff1068effe66bb6a11f444811ba58de40vboxsync * @returns VBox status code.
d41220dff1068effe66bb6a11f444811ba58de40vboxsync * @param pVM The VM handle.
d41220dff1068effe66bb6a11f444811ba58de40vboxsync * @param pRegFrame The register frame.
d41220dff1068effe66bb6a11f444811ba58de40vboxsyncVMMDECL(int) EMInterpretIret(PVM pVM, PCPUMCTXCORE pRegFrame)
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync RTGCUINTPTR pIretStack = (RTGCUINTPTR)pRegFrame->esp;
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync RTGCUINTPTR eip, cs, esp, ss, eflags, ds, es, fs, gs, uMask;
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc = emRamRead(pVM, &eip, (RTGCPTR)pIretStack , 4);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc |= emRamRead(pVM, &cs, (RTGCPTR)(pIretStack + 4), 4);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc |= emRamRead(pVM, &eflags, (RTGCPTR)(pIretStack + 8), 4);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync AssertReturn(eflags & X86_EFL_VM, VERR_EM_INTERPRETER);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc |= emRamRead(pVM, &esp, (RTGCPTR)(pIretStack + 12), 4);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc |= emRamRead(pVM, &ss, (RTGCPTR)(pIretStack + 16), 4);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc |= emRamRead(pVM, &es, (RTGCPTR)(pIretStack + 20), 4);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc |= emRamRead(pVM, &ds, (RTGCPTR)(pIretStack + 24), 4);
01cc79d6798a7ad8b8041ddb2b67fc8b37bf0b37vboxsync rc |= emRamRead(pVM, &fs, (RTGCPTR)(pIretStack + 28), 4);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync rc |= emRamRead(pVM, &gs, (RTGCPTR)(pIretStack + 32), 4);
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync /* Mask away all reserved bits */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync uMask = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_RF | X86_EFL_VM | X86_EFL_AC | X86_EFL_VIF | X86_EFL_VIP | X86_EFL_ID;
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync Assert((pRegFrame->eflags.u32 & (X86_EFL_IF|X86_EFL_IOPL)) == X86_EFL_IF);
dea1368099e5337861dd52906d4c683c447a33c4vboxsync#endif /* IN_GC */
dea1368099e5337861dd52906d4c683c447a33c4vboxsync * IRET Emulation.
dea1368099e5337861dd52906d4c683c447a33c4vboxsyncstatic int emInterpretIret(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
dea1368099e5337861dd52906d4c683c447a33c4vboxsync /* only allow direct calls to EMInterpretIret for now */
dea1368099e5337861dd52906d4c683c447a33c4vboxsync * WBINVD Emulation.
dea1368099e5337861dd52906d4c683c447a33c4vboxsyncstatic int emInterpretWbInvd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
dea1368099e5337861dd52906d4c683c447a33c4vboxsync /* Nothing to do. */
dea1368099e5337861dd52906d4c683c447a33c4vboxsync * Interpret INVLPG
dea1368099e5337861dd52906d4c683c447a33c4vboxsync * @returns VBox status code.
dea1368099e5337861dd52906d4c683c447a33c4vboxsync * @param pVM The VM handle.
dea1368099e5337861dd52906d4c683c447a33c4vboxsync * @param pRegFrame The register frame.
dea1368099e5337861dd52906d4c683c447a33c4vboxsync * @param pAddrGC Operand address
dea1368099e5337861dd52906d4c683c447a33c4vboxsyncVMMDECL(int) EMInterpretInvlpg(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pAddrGC)
dea1368099e5337861dd52906d4c683c447a33c4vboxsync /** @todo is addr always a flat linear address or ds based
dea1368099e5337861dd52906d4c683c447a33c4vboxsync * (in absence of segment override prefixes)????
dea1368099e5337861dd52906d4c683c447a33c4vboxsync || rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
dea1368099e5337861dd52906d4c683c447a33c4vboxsync AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
3cac8f8c6923a3a89ecfccda5e89ad75f48658e0vboxsync * INVLPG Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo is addr always a flat linear address or ds based
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync * (in absence of segment override prefixes)????
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync || rc == VINF_PGM_SYNC_CR3 /* we can rely on the FF */)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgReturn( rc == VERR_REM_FLUSHED_PAGES_OVERFLOW
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interpret CPUID given the parameters in the CPU context
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame The register frame.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretCpuId(PVM pVM, PCPUMCTXCORE pRegFrame)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Note: operates the same in 64 and non-64 bits mode. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync CPUMGetGuestCpuId(pVM, pRegFrame->eax, &pRegFrame->eax, &pRegFrame->ebx, &pRegFrame->ecx, &pRegFrame->edx);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("Emulate: CPUID %x -> %08x %08x %08x %08x\n", iLeaf, pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx));
7e960d3a0a8a3a84d7aba2cca45d72b1c31cc97bvboxsync * CPUID Emulation.
b45d66c0e496e2fd861479202f3d43aad592bd14vboxsyncstatic int emInterpretCpuId(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync * Interpret CRx read
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync * @returns VBox status code.
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync * @param pVM The VM handle.
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync * @param pRegFrame The register frame.
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync * @param DestRegGen General purpose register index (USE_REG_E**))
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync * @param SrcRegCRx CRx register index (USE_REG_CR*)
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsyncVMMDECL(int) EMInterpretCRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegCrx)
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync AssertMsgRCReturn(rc, ("PDMApicGetTPR failed\n"), VERR_EM_INTERPRETER);
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync AssertMsgRCReturn(rc, ("CPUMGetGuestCRx %d failed\n", SrcRegCrx), VERR_EM_INTERPRETER);
1ce20e84ae29a712029d1e213740388d7e158d5cvboxsync LogFlow(("MOV_CR: gen32=%d CR=%d val=%VX64\n", DestRegGen, SrcRegCrx, val64));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interpret CLTS
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsync * CLTS Emulation.
e85d76a7e5a047db3cdc8576ff5f412c7b73bbabvboxsyncstatic int emInterpretClts(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
b55721e255f55546462b62c2d09259bb7bf8ef90vboxsync * Update CRx
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame The register frame.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param DestRegCRx CRx register index (USE_REG_CR*)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param val New CRx value
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int EMUpdateCRx(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint64_t val)
0f59af434918ae6ade24245a5f963e4f2618b89evboxsync /** @todo Clean up this mess. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("EMInterpretCRxWrite at %VGv CR%d <- %VX64\n", pRegFrame->rip, DestRegCrx, val));
5db1d52ffbcaa46c3d944c6c2d9c552306817d9avboxsync /* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsync if ( (oldval & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* global flush */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Deal with long mode enabling/disabling. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Illegal to have an active 64 bits CS selector (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Illegal enabling of paging with CS.u1Long = 1!!\n"));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync /* Illegal to switch to long mode before activating PAE first (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync AssertMsgFailed(("Illegal enabling of paging with PAE disabled!!\n"));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* @todo Do we need to cut off rip here? High dword of rip is undefined, so it shouldn't really matter. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Reloading the current CR3 means the guest just wants to flush the TLBs */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* flush */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMFlushTLB(pVM, val, !(CPUMGetGuestCR4(pVM) & X86_CR4_PGE));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Illegal to disable PAE when long mode is active. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6b022885f2cb6a55167609edecd89570cd80001dvboxsync return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ( (oldval & (X86_CR4_PGE|X86_CR4_PAE|X86_CR4_PSE))
e50404712a2b5234c42bdf9740bddab5729ba188vboxsync /* global flush */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PGMFlushTLB(pVM, CPUMGetGuestCR3(pVM), true /* global */);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Feeling extremely lazy. */
fa7355597d7eba5b4ca8a23056ebe1b8fb306fdbvboxsync if ( (oldval & (X86_CR4_OSFSXR|X86_CR4_OSXMMEEXCPT|X86_CR4_PCE|X86_CR4_MCE|X86_CR4_PAE|X86_CR4_DE|X86_CR4_TSD|X86_CR4_PVI|X86_CR4_VME))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync != (val & (X86_CR4_OSFSXR|X86_CR4_OSXMMEEXCPT|X86_CR4_PCE|X86_CR4_MCE|X86_CR4_PAE|X86_CR4_DE|X86_CR4_TSD|X86_CR4_PVI|X86_CR4_VME)))
74991d7531692858fd22acf371a7ee941567977cvboxsync Log(("emInterpretMovCRx: CR4: %#RX64->%#RX64 => R3\n", oldval, val));
3a21cbe769e7500039a2d17c794a911f7acb2dadvboxsync return PGMChangeMode(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR4(pVM), CPUMGetGuestEFER(pVM));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interpret CRx write
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
74991d7531692858fd22acf371a7ee941567977cvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame The register frame.
74991d7531692858fd22acf371a7ee941567977cvboxsync * @param DestRegCRx CRx register index (USE_REG_CR*)
74991d7531692858fd22acf371a7ee941567977cvboxsync * @param SrcRegGen General purpose register index (USE_REG_E**))
74991d7531692858fd22acf371a7ee941567977cvboxsyncVMMDECL(int) EMInterpretCRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegCrx, uint32_t SrcRegGen)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return EMUpdateCRx(pVM, pRegFrame, DestRegCrx, val);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interpret LMSW
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame The register frame.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param u16Data LMSW source data.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretLMSW(PVM pVM, PCPUMCTXCORE pRegFrame, uint16_t u16Data)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Only PE, MP, EM and TS can be changed; note that PE can't be cleared by this instruction. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync uint64_t NewCr0 = ( OldCr0 & ~( X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync | (u16Data & (X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS));
0174432b2b1a760b89840ba696f7ba51def65dddvboxsync return EMUpdateCRx(pVM, pRegFrame, USE_REG_CR0, NewCr0);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * LMSW Emulation.
0174432b2b1a760b89840ba696f7ba51def65dddvboxsyncstatic int emInterpretLmsw(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretMovCRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ((pCpu->param1.flags == USE_REG_GEN32 || pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_CR)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return EMInterpretCRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_ctrl);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (pCpu->param1.flags == USE_REG_CR && (pCpu->param2.flags == USE_REG_GEN32 || pCpu->param2.flags == USE_REG_GEN64))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return EMInterpretCRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_ctrl, pCpu->param2.base.reg_gen);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailedReturn(("Unexpected control register move\n"), VERR_EM_INTERPRETER);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interpret DRx write
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame The register frame.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param DestRegDRx DRx register index (USE_REG_DR*)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param SrcRegGen General purpose register index (USE_REG_E**))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretDRxWrite(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interpret DRx read
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame The register frame.
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * @param DestRegGen General purpose register index (USE_REG_E**))
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync * @param SrcRegDRx DRx register index (USE_REG_DR*)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretDRxRead(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsyncstatic int emInterpretMovDRx(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
ec588a4ac8429a8b6c744544818b3ce3b2c75690vboxsync if((pCpu->param1.flags == USE_REG_GEN32 || pCpu->param1.flags == USE_REG_GEN64) && pCpu->param2.flags == USE_REG_DBG)
75fca099c974cbbd48f132af1378c60232614760vboxsync rc = EMInterpretDRxRead(pVM, pRegFrame, pCpu->param1.base.reg_gen, pCpu->param2.base.reg_dbg);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if(pCpu->param1.flags == USE_REG_DBG && (pCpu->param2.flags == USE_REG_GEN32 || pCpu->param2.flags == USE_REG_GEN64))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = EMInterpretDRxWrite(pVM, pRegFrame, pCpu->param1.base.reg_dbg, pCpu->param2.base.reg_gen);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Unexpected debug register move\n"));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * LLDT Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretLLdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return VERR_EM_INTERPRETER; //feeling lazy right now
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync // this simple case is most frequent in Windows 2000 (31k - boot & shutdown)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync //still feeling lazy
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync * LIDT/LGDT Emulation.
61fa69e2bc9fc9e7490feed1c020273f3ddb238dvboxsyncstatic int emInterpretLIGdt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
75fca099c974cbbd48f132af1378c60232614760vboxsync Log(("Emulate %s at %VGv\n", emGetMnemonic(pCpu), pRegFrame->rip));
75fca099c974cbbd48f132af1378c60232614760vboxsync /* Only for the VT-x real-mode emulation case. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, ¶m1, PARAM_SOURCE);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pParam1 = emConvertToFlatAddr(pVM, pRegFrame, pCpu, &pCpu->param1, param1.val.val16);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = emRamRead(pVM, &dtr32, pParam1, sizeof(dtr32));
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync dtr32.uAddr &= 0xffffff; /* 16 bits operand size */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * STI Emulation.
6b022885f2cb6a55167609edecd89570cd80001dvboxsync * @remark the instruction following sti is guaranteed to be executed before any interrupts are dispatched
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretSti(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->rip));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* IN_GC */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * HLT Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretHlt(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interpret RDTSC
a27fbcbb29ffc2196c2ebd0f2dad92f40c7ec65dvboxsync * @returns VBox status code.
10e1bc06b2908a0af56d92ffdbadd25b36a5ef61vboxsync * @param pVM The VM handle.
315f443a509c31db47b8f5cb94d26e54c3d5c497vboxsync * @param pRegFrame The register frame.
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsyncVMMDECL(int) EMInterpretRdtsc(PVM pVM, PCPUMCTXCORE pRegFrame)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Same behaviour in 32 & 64 bits mode */
75fca099c974cbbd48f132af1378c60232614760vboxsync * RDTSC Emulation.
75fca099c974cbbd48f132af1378c60232614760vboxsyncstatic int emInterpretRdtsc(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * MONITOR Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretMonitor(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Get the current privilege level. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * MWAIT Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretMWait(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Assert(pCpu->mode != CPUMODE_64BIT); /** @todo check */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Get the current privilege level. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Dummy);
d6b5539478863f176bfffefc1ada2b9489cfa092vboxsync if (!(u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR))
d6b5539478863f176bfffefc1ada2b9489cfa092vboxsync /** @todo not completely correct */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_IA32_APICBASE";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_IA32_CR_PAT";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_IA32_SYSENTER_CS";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_IA32_SYSENTER_EIP";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_IA32_SYSENTER_ESP";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_K6_EFER";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_K8_SF_MASK";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_K6_STAR";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_K8_LSTAR";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_K8_CSTAR";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_K8_FS_BASE";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_K8_GS_BASE";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "MSR_K8_KERNEL_GS_BASE";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_BIOS_SIGN_ID";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_PLATFORM_ID";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_BIOS_UPDT_TRIG";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_TSC";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_MTRR_CAP";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_MCP_CAP";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_MCP_STATUS";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_MCP_CTRL";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_MTRR_DEF_TYPE";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_K7_EVNTSEL0";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_K7_EVNTSEL1";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_K7_EVNTSEL2";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_K7_EVNTSEL3";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_MC0_CTL";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unsupported MSR_IA32_MC0_STATUS";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return "Unknown MSR";
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#endif /* LOG_ENABLED */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interpret RDMSR
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame The register frame.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretRdmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
9a99bb9ca6c5bc8ef1977e01e13b05e5cc58319bvboxsync /** @todo According to the Intel manuals, there's a REX version of RDMSR that is slightly different.
50df3da42ff6589b0ecc4f50f2288811bc370186vboxsync * That version clears the high dwords of both RDX & RAX */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Get the current privilege level. */
fdc5224bd8d9a60af82da5809e3d6729c9bc69cbvboxsync CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#if 0 /*def IN_RING0 */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Available since the P6 family. VT-x implies that this feature is present. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* no break */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* In X2APIC specification this range is reserved for APIC control. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = PDMApicReadMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("EMInterpretRdmsr %s (%x) -> val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * RDMSR Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretRdmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Interpret WRMSR
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns VBox status code.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pRegFrame The register frame.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncVMMDECL(int) EMInterpretWrmsr(PVM pVM, PCPUMCTXCORE pRegFrame)
2c080f6fc6ab70995d6390eeaa199d590c1a34d5vboxsync /* Note: works the same in 32 and 64 bits modes. */
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync /* Get the current privilege level. */
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
32f98f3d0fb00168315b4ece1f0808df4cd88248vboxsync Log(("EMInterpretWrmsr %s (%x) val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pCtx->SysEnter.cs = val & 0xffff; /* 16 bits selector */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync CPUMGetGuestCpuId(pVM, 0x80000001, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if (u32Features & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
6b022885f2cb6a55167609edecd89570cd80001dvboxsync if ( ((pCtx->msrEFER & MSR_K6_EFER_LME) != (val & uMask & MSR_K6_EFER_LME))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsgFailed(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync return VERR_EM_INTERPRETER; /* @todo generate #GP(0) */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync AssertMsg(!(val & ~(MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA /* ignored anyway */ |MSR_K6_EFER_SCE|MSR_K6_EFER_FFXSR)), ("Unexpected value %RX64\n", val));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync pCtx->msrEFER = (pCtx->msrEFER & ~uMask) | (val & uMask);
750d4d0506a38b2e80c997075d40aad474e675fbvboxsync /* AMD64 Achitecture Programmer's Manual: 15.15 TLB Control; flush the TLB if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ((oldval & (MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA)) != (pCtx->msrEFER & (MSR_K6_EFER_NXE|MSR_K6_EFER_LME|MSR_K6_EFER_LMA)))
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* In X2APIC specification this range is reserved for APIC control. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END))
689e03ca2c98ca6feaab8d9de6e4687a98f14ccbvboxsync return PDMApicWriteMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * WRMSR Emulation.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncstatic int emInterpretWrmsr(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Internal worker.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @copydoc EMInterpretInstructionCPU
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsyncDECLINLINE(int) emInterpretInstructionCPU(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize)
491e761460097c61edb725a77477cecb2774da45vboxsync * Only supervisor guest code!!
491e761460097c61edb725a77477cecb2774da45vboxsync * And no complicated prefixes.
491e761460097c61edb725a77477cecb2774da45vboxsync /* Get the current privilege level. */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync && pCpu->pCurInstr->opcode != OP_RDTSC) /* rdtsc requires emulation in ring 3 as well */
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log(("WARNING: refusing instruction emulation for user-mode code!!\n"));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedUserMode));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync //Log(("EMInterpretInstruction: wrong prefix!!\n"));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedPrefix));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync LogFlow(("emInterpretInstructionCPU %s\n", emGetMnemonic(pCpu)));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync# define INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = emInterpretLock##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulateLock); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#define INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize, pfnEmulate); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#define INTERPRET_CASE_EX_PARAM2(opcode, Instr, InstrFn, pfnEmulate) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_PARAM3(opcode, Instr, InstrFn, pfnEmulate)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#define INTERPRET_CASE_EX_LOCK_PARAM2(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock) \
b1c3cdef473df2fbc621d5da81acc82dbfb8a11avboxsync INTERPRET_CASE_EX_LOCK_PARAM3(opcode, Instr, InstrFn, pfnEmulate, pfnEmulateLock)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = emInterpret##Instr(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
19b725c530eb49600728765de7ed451cbe290740vboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync#define INTERPRET_CASE_EX_DUAL_PARAM2(opcode, Instr, InstrFn) \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync rc = emInterpret##InstrFn(pVM, pCpu, pRegFrame, pvFault, pcbSize); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Instr)); \
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); \
3080f6c0871099df43a4e91b31894d9c2b1369a8vboxsync case opcode: STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,Failed##Instr)); return VERR_EM_INTERPRETER;
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_PARAM2(OP_DEC,Dec, IncDec, EMEmulateDec);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_PARAM2(OP_INC,Inc, IncDec, EMEmulateInc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_LOCK_PARAM3(OP_OR, Or, OrXorAnd, EMEmulateOr, EMEmulateLockOr);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_PARAM3(OP_XOR,Xor, OrXorAnd, EMEmulateXor);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_PARAM3(OP_AND,And, OrXorAnd, EMEmulateAnd);
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync INTERPRET_CASE_EX_DUAL_PARAM2(OP_LIDT, LIdt, LIGdt);
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsync INTERPRET_CASE_EX_DUAL_PARAM2(OP_LGDT, LGdt, LIGdt);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_PARAM3(OP_ADD,Add, AddSub, EMEmulateAdd);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_PARAM3(OP_SUB,Sub, AddSub, EMEmulateSub);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_LOCK_PARAM2(OP_BTR,Btr, BitTest, EMEmulateBtr, EMEmulateLockBtr);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_PARAM2(OP_BTS,Bts, BitTest, EMEmulateBts);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync INTERPRET_CASE_EX_PARAM2(OP_BTC,Btc, BitTest, EMEmulateBtc);
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync Log3(("emInterpretInstructionCPU: opcode=%d\n", pCpu->pCurInstr->opcode));
00599f6d39cc25ca39845c2433cd75de7b9f6971vboxsync STAM_COUNTER_INC(&pVM->em.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,FailedMisc));
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Sets the PC for which interrupts should be inhibited.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM The VM handle.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param PC The PC.
9b45880674da6f82ca27cc28b0272de3dd3cc7dfvboxsyncVMMDECL(void) EMSetInhibitInterruptsPC(PVM pVM, RTGCUINTPTR PC)
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * Gets the PC for which interrupts should be inhibited.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * There are a few instructions which inhibits or delays interrupts
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * for the instruction following them. These instructions are:
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * - MOV SS, r/m16
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @returns The PC for which interrupts should be inhibited.
d408b82da0773c7e8cd4b3a01cb8a065a2c73a2dvboxsync * @param pVM VM handle.