#include <mii.h>
#include <stdio.h>
#include <errno.h>
#include <unistd.h>
#include <byteswap.h>
#include <ipxe/if_ether.h>
#include <ipxe/ethernet.h>
#include <ipxe/netdevice.h>
#include "tg3.h"
#define TG3_DEF_RX_MODE 0
#define TG3_DEF_TX_MODE 0
/* Do not place this n-ring entries value into the tp struct itself,
* we really want to expose these constants to GCC so that modulo et
* al. operations are done with shifts and masks instead of with
* replace things like '% foo' with '& (foo - 1)'.
*/
/* FIXME: does TG3_RX_RET_MAX_SIZE_5705 work for all cards? */
(sizeof(struct tg3_rx_buffer_desc) * (TG3_RX_RET_MAX_SIZE_5705))
(sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)
}
}
/*
* Must not be invoked with interrupt sources disabled and
* the hardware shutdown down.
*/
}
tp->rx_rcb_mapping = 0;
}
tp->status_mapping = 0;
}
}
/*
* Must not be invoked with interrupt sources disabled and
* the hardware shutdown down. Can sleep.
*/
goto err_out;
}
goto err_out;
}
if (!tp->tx_buffers)
goto err_out;
goto err_out;
/*
* When RSS is enabled, the status block format changes
* slightly. The "rx_jumbo_consumer", "reserved",
* and "rx_mini_consumer" members get mapped to the
* other three rx return ring producer indexes.
*/
goto err_out;
return 0;
return -ENOMEM;
}
(sizeof(struct ring_info) * TG3_RX_STD_MAX_SIZE_5700)
(sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)
/* Initialize rx rings for packet processing.
*
* The chip has been shut down and the driver detached from
* the networking, so no interrupts or new tx packets will
* end up in the driver.
*/
struct tg3_rx_prodring_set *tpr)
u32 i;
tpr->rx_std_cons_idx = 0;
tpr->rx_std_prod_idx = 0;
/* Initialize invariants of the rings, we only set this
* stuff once. This works because the card does not
* write into the rx buffer posting rings.
*/
/* FIXME: does TG3_RX_STD_MAX_SIZE_5700 work on all cards? */
for (i = 0; i < TG3_RX_STD_MAX_SIZE_5700; i++) {
(i << RXD_OPAQUE_INDEX_SHIFT));
}
return 0;
}
return;
}
unsigned int i;
for (i = 0; i < TG3_DEF_RX_RING_PENDING; i++)
}
*
* The chip has been shut down and the driver detached from
* the networking, so no interrupts or new tx packets will
* end up in the driver.
*/
/* Free up all the SKBs. */
/// tg3_free_rings(tp);
tp->last_irq_tag = 0;
tp->rx_rcb_ptr = 0;
return -ENOMEM;
}
return 0;
}
int err = 0;
/* Initialize MAC address and backoff seed. */
__tg3_set_mac_addr(tp, 0);
if (err)
return err;
tpr->rx_std_iob_cnt = 0;
if (err != 0)
return err;
}
/* Tell compiler to fetch tx indices from memory. */
barrier();
return TG3_DEF_TX_RING_PENDING -
}
#if 0
/**
*
* Prints all registers that could cause a set ERR bit in hw_status->status
*/
}
}
#endif
* support TG3_FLAG_HW_TSO_1 or firmware TSO only.
*/
return -ENOBUFS;
}
/* Packets are ready, update Tx producer idx local and on card. */
mb();
return 0;
}
}
}
(sizeof(struct ring_info) * TG3_RX_STD_MAX_SIZE_5700)
(sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_MAX_SIZE_5700)
/* Returns 0 or < 0 on error.
*
* We only need to fill in the address because the other members
* of the RX descriptor are invariant, see tg3_init_rings.
*
* Note the purposeful assymetry of cpu vs. chip accesses. For
* posting buffers we only dirty the first cache line of the RX
* descriptor (containing the address). Whereas for the RX status
* buffers the cpu only reads the last cacheline of the RX descriptor
* (to fetch the error flags, vlan tag, checksum, and opaque cookie).
*/
/* Do not overwrite any of the map or rp information
* until we are sure we can commit to a new buffer.
*
* Callers depend upon this behavior and assume that
* we leave everything unchanged if we fail.
*/
return -ENOMEM;
return 0;
}
break;
}
}
tpr->rx_std_iob_cnt++;
}
}
unsigned int len;
/* drop packet */
} else {
}
sw_idx++;
tpr->rx_std_iob_cnt--;
}
}
/* ACK interrupts */
}
}
if (enable)
else
}
.transmit = tg3_transmit,
};
int tg3_do_test_dma(struct tg3 *tp, u32 __unused *buf, dma_addr_t buf_dma, int size, int to_device);
int ret = 0;
if (!buf) {
goto out_nofree;
}
goto out;
}
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
/* DMA read watermark not used on PCIE */
else
} else {
read_water = 4;
/* Set bit 23 to enable PCIX hw bug fix */
tp->dma_rwctrl |=
(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
(1 << 23);
/* 5780 always in PCIX mode */
/* 5714 always in PCIX mode */
} else {
}
}
/* Remove this if it causes problems for some boards. */
/* On 5700/5701 chips, we need to set this bit.
* Otherwise the chip will issue cacheline transactions
* to streamable DMA memory with not all the byte
* enables turned on. This is an error on several
* RISC PCI controllers, in particular sparc64.
*
* On 5703/5704 chips, this bit has been reassigned
* a different meaning. In particular, it is used
* on those chips to enable a PCI-X workaround.
*/
}
#if 0
/* Unneeded, already done by tg3_get_invariants. */
#endif
goto out;
/* It is best to perform DMA test with maximum write burst size
* to expose the 5700/5701 write DMA bug.
*/
while (1) {
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
p[i] = i;
/* Send the buffer to the chip. */
if (ret) {
"%s: Buffer write failed. err = %d\n",
break;
}
/* validate data reached card RAM correctly. */
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
if (le32_to_cpu(val) != p[i]) {
"%s: Buffer corrupted on device! "
/* ret = -ENODEV here? */
}
p[i] = 0;
}
/* Now read it back. */
if (ret) {
break;
}
/* Verify it. */
for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
if (p[i] == i)
continue;
break;
} else {
"%s: Buffer corrupted on read back! "
"(%d != %d)\n", __func__, p[i], i);
goto out;
}
}
if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
/* Success. */
ret = 0;
break;
}
}
/* DMA test passed without adjusting DMA boundary,
* now look for chipsets that are known to expose the
* DMA bug without failing the test.
*/
}
out:
return ret;
}
int err = 0;
if (!dev) {
goto err_out_disable_pdev;
}
/* Subsystem IDs are required later */
* swapping. DMA data byte swapping is controlled in the GRC_MODE
* setting below.
*/
tp->misc_host_ctrl =
* on descriptor entries, anything which isn't packet data.
*
* The StrongARM chips on the board (one for tx, one for rx)
* are running in big-endian mode.
*/
#if __BYTE_ORDER == __BIG_ENDIAN
#endif
/* FIXME: how can we detect errors here? */
goto err_out_disable_pdev;
}
if (err) {
goto err_out_iounmap;
}
if (err) {
goto err_out_iounmap;
}
/*
* Reset chip in case UNDI or EFI driver did not shutdown
* DMA self test will enable WDMAC and we'll see (spurious)
* pending DMA on the PCI bus at that point.
*/
}
if (err) {
goto err_out_iounmap;
}
if (err) {
goto err_out_iounmap;
}
/* Call tg3_setup_phy() to start autoneg process, which saves time
* over starting autoneg in tg3_open();
*/
if (err) {
goto err_out_iounmap;
}
return 0;
}
return err;
}
}
};
.probe = tg3_init_one,
.remove = tg3_remove_one,
};