/*******************************************************************************
Intel(R) 82576 Virtual Function Linux driver
Copyright(c) 1999 - 2008 Intel Corporation.
under the terms and conditions of the GNU General Public License,
version 2, as published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
The full GNU General Public License is included in this distribution in
the file called "COPYING".
Contact Information:
Linux NICS <linux.nics@intel.com>
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#ifndef _IGBVF_DEFINES_H_
#define _IGBVF_DEFINES_H_
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
/* Definitions for power management and wakeup registers */
/* Wake Up Control */
/* Wake Up Filter Control */
/* Wake Up Status */
/* Wake Up Packet Length */
/* Four Flexible Filters are supported */
/* Each Flexible Filter is at most 128 (0x80) bytes in length */
/* Extended Device Control */
/* Reserved (bits 4,5) in >= 82575 */
/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
/* IAME enable bit (27) was removed in >= 82575 */
* detection enabled */
* error detection enable */
/* Receive Descriptor bit definitions */
/* mask to determine if packets should be dropped due to frame errors */
#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
E1000_RXD_ERR_CE | \
E1000_RXD_ERR_SE | \
/* Same mask, but for extended and packet split descriptors */
#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
/* Management Control */
/* Enable Neighbor Discovery Filtering */
/* Enable MAC address filtering */
/* Enable MNG packets to host memory */
/* Enable IP address filtering */
/* Receive Control */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
/*
* Use byte values for the following shift parameters
* Usage:
* psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
* E1000_PSRCTL_BSIZE0_MASK) |
* ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
* E1000_PSRCTL_BSIZE1_MASK) |
* ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
* E1000_PSRCTL_BSIZE2_MASK) |
* ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
* E1000_PSRCTL_BSIZE3_MASK))
* where value0 = [128..16256], default=256
* value1 = [1024..64512], default=4096
* value2 = [0..64512], default=4096
* value3 = [0..64512], default=0
*/
/* SWFW_SYNC Definitions */
/* FACTPS Definitions */
/* Device Control */
* indication in SDP[0] */
* PHYRST_N pin */
* LINK_0 and LINK_1 pins */
/*
* Bit definitions for the Management Data IO (MDIO) and Management Data
* Clock (MDC) pins in the Device Control Register.
*/
#define E1000_PCS_LCTL_FSV_10 0
#define E1000_PCS_LSTS_SPEED_10 0
/* Device Status */
* Clear on write '0'. */
* disabled */
/* Constants used to interpret the masked PCI-X bus speed. */
/* 1000/H is not supported, nor spec-compliant. */
/* LED Control */
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
/* Transmit Descriptor bit definitions */
/* Extended desc bits for Linksec and timesync */
/* Transmit Control */
/* Transmit Arbitration Count */
/* SerDes Control */
/* Receive Checksum Control */
/* Header split receive */
/* Collision related configuration parameters */
/* Default values for the transmit IPG register */
/* Ethertype field values */
/* Extended Configuration Control and Size */
/* PBA constants */
/* SW Semaphore Register */
/* Interrupt Cause Read */
* should claim the interrupt */
* bit in the FWSM */
* an interrupt */
/*
* This defines the bits that are set in the Interrupt Mask
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
* o RXSEQ = Receive Sequence Error
*/
#define POLL_IMS_ENABLE_MASK ( \
E1000_IMS_RXDMT0 | \
/*
* This defines the bits that are set in the Interrupt Mask
* o RXT0 = Receiver Timer Interrupt (ring 0)
* o TXDW = Transmit Descriptor Written Back
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
* o RXSEQ = Receive Sequence Error
* o LSC = Link Status Change
*/
#define IMS_ENABLE_MASK ( \
E1000_IMS_RXT0 | \
E1000_IMS_TXDW | \
E1000_IMS_RXDMT0 | \
E1000_IMS_RXSEQ | \
/* Interrupt Mask Set */
* parity error */
* parity error */
* parity error */
* error */
* parity error */
* parity error */
/* Interrupt Cause Set */
* parity error */
* parity error */
* parity error */
* error */
* parity error */
* parity error */
/* Transmit Descriptor Control */
/* Enable the counting of descriptors still to be processed. */
/* Flow Control Constants */
/* 802.1q VLAN Packet Size */
/* Receive Address */
/*
* Registers) holds the directed and multicast addresses that we monitor.
* Technically, we have 16 spots. However, we reserve one of these spots
* (RAR[15]) for our directed address used by controllers with
* manageability enabled, allowing us room for 15 multicast addresses.
*/
/* Error Codes */
#define E1000_SUCCESS 0
/* Loop limit on how long we wait for auto-negotiation to complete */
/* Number of 100 microseconds we wait for PCI Express master disable */
/* Number of milliseconds we wait for PHY configuration done after MAC reset */
/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
/* Number of milliseconds for NVM auto read done after MAC reset. */
/* Flow Control */
/* Transmit Configuration Word */
/* Receive Configuration Word */
/* PCI Express Control */
/* PHY Control Register */
/* PHY Status Register */
/* Autoneg Advertisement Register */
/* Link Partner Ability Register (Base Page) */
/* Autoneg Expansion Register */
/* 1000BASE-T Control Register */
/* 0=DTE device */
/* 0=Configure PHY as Slave */
/* 1000BASE-T Status Register */
/* PHY Registers defined by IEEE */
/* NVM Control */
/* NVM Addressing bits based on type 0=small, 1=large */
/* NVM Word Offsets */
/* Mask bits for fields in Word 0x0f of the NVM */
/* Mask bits for fields in Word 0x1a of the NVM */
/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
#define NVM_MAC_ADDR_OFFSET 0
/* NVM Commands - SPI */
/* SPI NVM Status Register */
/* Word definitions for ID LED Settings */
(ID_LED_OFF1_OFF2 << 8) | \
(ID_LED_DEF1_DEF2 << 4) | \
#ifndef ETH_ADDR_LEN
#endif
/* Bit definitions for valid PHY IDs. */
/*
* I = Integrated
* E = External
*/
/* M88E1000 Specific Registers */
/* M88E1000 PHY Specific Control Register */
/* 1=CLK125 low, 0=CLK125 toggling */
/* Manual MDI configuration */
/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
/* Auto crossover enabled all speeds */
/*
* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
* 0=Normal 10BASE-T Rx Threshold
*/
/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
/* M88E1000 PHY Specific Status Register */
/*
* 0 = <50M
* 1 = 50-80M
* 2 = 80-110M
* 3 = 110-140M
* 4 = >140M
*/
/* M88E1000 Extended PHY Specific Control Register */
/*
* 1 = Lost lock detect enabled.
* Will assert lost lock and bring
* link down if idle not seen
* within 1ms in 1000BASE-T
*/
/*
* Number of times we will attempt to autonegotiate before downshifting if we
* are the master
*/
/*
* Number of times we will attempt to autonegotiate before downshifting if we
* are the slave
*/
/* M88EC018 Rev 2 specific DownShift settings */
/*
* Bits...
* 15-5: page
* 4-0: register offset
*/
/* GG82563 Specific Registers */
#define GG82563_PHY_SPEC_CTRL \
#define GG82563_PHY_SPEC_STATUS \
#define GG82563_PHY_INT_ENABLE \
#define GG82563_PHY_SPEC_STATUS_2 \
#define GG82563_PHY_RX_ERR_CNTR \
#define GG82563_PHY_PAGE_SELECT \
#define GG82563_PHY_SPEC_CTRL_2 \
#define GG82563_PHY_PAGE_SELECT_ALT \
#define GG82563_PHY_TEST_CLK_CTRL \
#define GG82563_PHY_MAC_SPEC_CTRL \
#define GG82563_PHY_MAC_SPEC_CTRL_2 \
#define GG82563_PHY_DSP_DISTANCE \
/* Page 193 - Port Control Registers */
#define GG82563_PHY_KMRN_MODE_CTRL \
#define GG82563_PHY_PORT_RESET \
#define GG82563_PHY_REVISION_ID \
#define GG82563_PHY_DEVICE_ID \
#define GG82563_PHY_PWR_MGMT_CTRL \
#define GG82563_PHY_RATE_ADAPT_CTRL \
/* Page 194 - KMRN Registers */
#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
#define GG82563_PHY_KMRN_CTRL \
#define GG82563_PHY_INBAND_CTRL \
#define GG82563_PHY_KMRN_DIAGNOSTIC \
#define GG82563_PHY_ACK_TIMEOUTS \
#define GG82563_PHY_ADV_ABILITY \
#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
#define GG82563_PHY_ADV_NEXT_PAGE \
#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
#define GG82563_PHY_KMRN_MISC \
/* MDI Control */
/* SerDes Control */
#endif /* _IGBVF_DEFINES_H_ */