/** @file
Local APIC Library.
This local APIC library instance supports x2APIC capable processors
which have xAPIC and x2APIC modes.
Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Register/LocalApic.h>
#include <Library/DebugLib.h>
#include <Library/LocalApicLib.h>
#include <Library/TimerLib.h>
//
// Library internal functions
//
/**
Read from a local APIC register.
This function reads from a local APIC register either in xAPIC or x2APIC mode.
It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
accessed using multiple 32-bit loads or stores, so this function only performs
32-bit read.
@param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
It must be 16-byte aligned.
@return 32-bit Value read from the register.
**/
)
{
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
} else {
//
// DFR is not supported in x2APIC mode.
//
//
// Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
// is not supported in this function for simplicity.
//
return AsmReadMsr32 (MsrIndex);
}
}
/**
Write to a local APIC register.
This function writes to a local APIC register either in xAPIC or x2APIC mode.
It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
accessed using multiple 32-bit loads or stores, so this function only performs
32-bit write.
if the register index is invalid or unsupported in current APIC mode, then ASSERT.
@param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
It must be 16-byte aligned.
@param Value Value to be written to the register.
**/
)
{
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
} else {
//
// DFR is not supported in x2APIC mode.
//
//
// Note that in x2APIC mode, ICR is a 64-bit MSR that needs special treatment. It
// is not supported in this function for simplicity.
//
//
// The serializing semantics of WRMSR are relaxed when writing to the APIC registers.
// Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.
//
MemoryFence ();
}
}
/**
Send an IPI by writing to ICR.
This function returns after the IPI has been accepted by the target processor.
@param IcrLow 32-bit value to be written to the low half of ICR.
@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
**/
SendIpi (
)
{
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
//
// For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
//
do {
} else {
//
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
// interrupt in x2APIC mode.
//
}
}
//
// Library API implementation functions
//
/**
Get the current local APIC mode.
If local APIC is disabled, then ASSERT.
@retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
@retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
**/
)
{
//
// Local APIC should have been enabled
//
return LOCAL_APIC_MODE_X2APIC;
} else {
return LOCAL_APIC_MODE_XAPIC;
}
}
/**
Set the current local APIC mode.
If the specified local APIC mode is not valid, then ASSERT.
If the specified local APIC mode can't be set as current, then ASSERT.
@param ApicMode APIC mode to be set.
**/
)
{
CurrentMode = GetApicMode ();
if (CurrentMode == LOCAL_APIC_MODE_XAPIC) {
switch (ApicMode) {
case LOCAL_APIC_MODE_XAPIC:
break;
case LOCAL_APIC_MODE_X2APIC:
break;
default:
}
} else {
switch (ApicMode) {
case LOCAL_APIC_MODE_XAPIC:
//
// Transition from x2APIC mode to xAPIC mode is a two-step process:
// x2APIC -> Local APIC disabled -> xAPIC
//
break;
case LOCAL_APIC_MODE_X2APIC:
break;
default:
}
}
}
/**
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.
In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
the 32-bit local APIC ID is returned as initial APIC ID.
@return 32-bit initial local APIC ID of the executing processor.
**/
)
{
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
return RegEbx >> 24;
} else {
return GetApicId ();
}
}
/**
Get the local APIC ID of the executing processor.
@return 32-bit local APIC ID of the executing processor.
**/
)
{
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
ApicId >>= 24;
}
return ApicId;
}
/**
Get the value of the local APIC version register.
@return the value of the local APIC version register.
**/
)
{
return ReadLocalApicReg (XAPIC_VERSION_OFFSET);
}
/**
Send a Fixed IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId The local APIC ID of the target processor.
@param Vector The vector number of the interrupt being sent.
**/
)
{
}
/**
Send a Fixed IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
@param Vector The vector number of the interrupt being sent.
**/
)
{
}
/**
Send a SMI IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId Specify the local APIC ID of the target processor.
**/
)
{
}
/**
Send a SMI IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
**/
)
{
}
/**
Send an INIT IPI to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
@param ApicId Specify the local APIC ID of the target processor.
**/
)
{
}
/**
Send an INIT IPI to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
**/
)
{
}
/**
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
This function returns after the IPI has been accepted by the target processor.
if StartupRoutine >= 1M, then ASSERT.
if StartupRoutine is not multiple of 4K, then ASSERT.
@param ApicId Specify the local APIC ID of the target processor.
@param StartupRoutine Points to a start-up routine which is below 1M physical
address and 4K aligned.
**/
)
{
MicroSecondDelay (10);
MicroSecondDelay (200);
}
/**
Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
This function returns after the IPI has been accepted by the target processors.
if StartupRoutine >= 1M, then ASSERT.
if StartupRoutine is not multiple of 4K, then ASSERT.
@param StartupRoutine Points to a start-up routine which is below 1M physical
address and 4K aligned.
**/
)
{
MicroSecondDelay (10);
MicroSecondDelay (200);
}
/**
Programming Virtual Wire Mode.
This function programs the local APIC for virtual wire mode following
the example described in chapter A.3 of the MP 1.4 spec.
IOxAPIC is not involved in this type of virtual wire mode.
**/
)
{
//
// Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
//
//
// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
//
//
// Program the LINT0 vector entry as NMI. Not masked, edge, active high.
//
}
/**
Disable LINT0 & LINT1 interrupts.
This function sets the mask flag in the LVT LINT0 & LINT1 registers.
**/
)
{
}
/**
Read the initial count value from the init-count register.
@return The initial count value read from the init-count register.
**/
)
{
}
/**
Read the current count value from the current-count register.
@return The current count value read from the current-count register.
**/
)
{
}
/**
Initialize the local APIC timer.
The local APIC timer is initialized and enabled.
@param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
If it is 0, then use the current divide value in the DCR.
@param InitCount The initial count value.
@param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
@param Vector The timer interrupt vector number.
**/
)
{
//
// Ensure local APIC is in software-enabled state.
//
//
// Program init-count register.
//
if (DivideValue != 0) {
}
//
// Enable APIC timer interrupt with specified timer mode.
//
if (PeriodicMode) {
} else {
}
}
/**
Get the state of the local APIC timer.
@param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
@param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
@param Vector Return the timer interrupt vector number.
**/
)
{
if (DivideValue != NULL) {
}
if (PeriodicMode != NULL) {
*PeriodicMode = TRUE;
} else {
*PeriodicMode = FALSE;
}
}
}
}
}
/**
Enable the local APIC timer interrupt.
**/
)
{
}
/**
Disable the local APIC timer interrupt.
**/
)
{
}
/**
Get the local APIC timer interrupt state.
@retval TRUE The local APIC timer interrupt is enabled.
@retval FALSE The local APIC timer interrupt is disabled.
**/
)
{
}
/**
Send EOI to the local APIC.
**/
)
{
}
/**
Get the 32-bit address that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
@return 32-bit address used to send an MSI to the Local APIC.
**/
)
{
//
// Return address for an MSI interrupt to be delivered only to the APIC ID
// of the currently executing processor.
//
MsiAddress.Uint32 = 0;
return MsiAddress.Uint32;
}
/**
Get the 64-bit data value that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
If Vector is not in range 0x10..0xFE, then ASSERT().
If DeliveryMode is not supported, then ASSERT().
@param Vector The 8-bit interrupt vector associated with the MSI.
Must be in the range 0x10..0xFE
@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
is handled. The only supported values are:
0: LOCAL_APIC_DELIVERY_MODE_FIXED
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
2: LOCAL_APIC_DELIVERY_MODE_SMI
4: LOCAL_APIC_DELIVERY_MODE_NMI
5: LOCAL_APIC_DELIVERY_MODE_INIT
7: LOCAL_APIC_DELIVERY_MODE_EXTINT
@param LevelTriggered TRUE specifies a level triggered interrupt.
FALSE specifies an edge triggered interrupt.
@param AssertionLevel Ignored if LevelTriggered is FALSE.
TRUE specifies a level triggered interrupt that active
when the interrupt line is asserted.
FALSE specifies a level triggered interrupt that active
when the interrupt line is deasserted.
@return 64-bit data value used to send an MSI to the Local APIC.
**/
)
{
if (LevelTriggered) {
if (AssertionLevel) {
}
}
}