4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/* $NetBSD: ia64_cpu.h,v 1.1 2006/04/07 14:21:18 cherry Exp $ */
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Copyright (c) 2000 Doug Rabson
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * All rights reserved.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Redistribution and use in source and binary forms, with or without
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * modification, are permitted provided that the following conditions
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * 1. Redistributions of source code must retain the above copyright
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * notice, this list of conditions and the following disclaimer.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * 2. Redistributions in binary form must reproduce the above copyright
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * notice, this list of conditions and the following disclaimer in the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * documentation and/or other materials provided with the distribution.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * SUCH DAMAGE.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * $FreeBSD$
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Definition of PSR and IPSR bits.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Definition of ISR bits.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Vector numbers for various ia64 interrupts.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * IA-32 exceptions.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Various special ia64 instructions.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Memory Fence.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Flush Cache.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Flush Instruction Cache
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Sync instruction stream.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Calculate address in VHPT for va.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Calculate VHPT tag for va.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Convert virtual address to physical.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Generate a ptc.e instruction.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Generate a ptc.g instruction.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("ptc.g %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Generate a ptc.ga instruction.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("ptc.ga %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Generate a ptc.l instruction.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("ptc.l %0,%1;; srlz.d;;" :: "r"(va), "r"(log2size));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Read the value of psr.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Define accessors for application registers.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("mov %0=ar." #name : "=r" (result)); \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncstatic __inline void \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("mov ar." #name "=%0;;" :: "r" (v)); \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Define accessors for control registers.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("mov %0=cr." #name : "=r" (result)); \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncstatic __inline void \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync __asm __volatile("mov cr." #name "=%0;;" :: "r" (v)); \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Write a region register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync * Read a CPUID register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#endif /* !_LOCORE */
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#endif /* _MACHINE_IA64_CPU_H_ */