/* $NetBSD: ia64_cpu.h,v 1.1 2006/04/07 14:21:18 cherry Exp $ */
/*-
* Copyright (c) 2000 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_IA64_CPU_H_
#define _MACHINE_IA64_CPU_H_
/*
* Definition of PSR and IPSR bits.
*/
/*
* Definition of ISR bits.
*/
/*
* Vector numbers for various ia64 interrupts.
*/
#define IA64_VEC_VHPT 0
/*
* IA-32 exceptions.
*/
#define IA32_EXCEPTION_DIVIDE 0
#define IA32_INTERCEPT_INSTRUCTION 0
#ifndef _LOCORE
/*
* Various special ia64 instructions.
*/
/*
* Memory Fence.
*/
static __inline void
ia64_mf(void)
{
}
static __inline void
ia64_mf_a(void)
{
}
/*
* Flush Cache.
*/
static __inline void
{
}
/*
* Flush Instruction Cache
*/
static __inline void
{
}
/*
* Sync instruction stream.
*/
static __inline void
ia64_sync_i(void)
{
}
/*
* Calculate address in VHPT for va.
*/
{
return result;
}
/*
* Calculate VHPT tag for va.
*/
{
return result;
}
/*
* Convert virtual address to physical.
*/
{
return result;
}
/*
* Generate a ptc.e instruction.
*/
static __inline void
{
}
/*
* Generate a ptc.g instruction.
*/
static __inline void
{
}
/*
* Generate a ptc.ga instruction.
*/
static __inline void
{
}
/*
* Generate a ptc.l instruction.
*/
static __inline void
{
}
/*
* Read the value of psr.
*/
ia64_get_psr(void)
{
return result;
}
/*
* Define accessors for application registers.
*/
\
{ \
return result; \
} \
\
static __inline void \
{ \
}
/*
* Define accessors for control registers.
*/
\
{ \
return result; \
} \
\
static __inline void \
{ \
}
/*
* Write a region register.
*/
static __inline void
{
}
/*
* Read a CPUID register.
*/
ia64_get_cpuid(int i)
{
return result;
}
static __inline void
ia64_disable_highfp(void)
{
}
static __inline void
ia64_enable_highfp(void)
{
}
#endif /* !_LOCORE */
#endif /* _MACHINE_IA64_CPU_H_ */