/* $NetBSD: cpufunc.h,v 1.37.24.1 2007/02/21 18:36:02 snj Exp $ */
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Causality Limited.
* 4. The name of Causality Limited may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
*
* Prototypes for cpu, mmu and tlb related functions.
*/
#ifndef _ARM32_CPUFUNC_H_
#define _ARM32_CPUFUNC_H_
#ifdef _KERNEL
struct cpu_functions {
/* CPU functions */
/* MMU functions */
/* TLB functions */
/*
* Cache operations:
*
* We define the following primitives:
*
* icache_sync_all Synchronize I-cache
* icache_sync_range Synchronize I-cache range
*
* dcache_wbinv_all Write-back and Invalidate D-cache
* dcache_wbinv_range Write-back and Invalidate D-cache range
* dcache_inv_range Invalidate D-cache range
* dcache_wb_range Write-back D-cache range
*
* idcache_wbinv_all Write-back and Invalidate D-cache,
* Invalidate I-cache
* idcache_wbinv_range Write-back and Invalidate D-cache,
* Invalidate I-cache range
*
* Note that the ARM term for "write-back" is "clean". We use
* the term "write-back" since it's a more common way to describe
* the operation.
*
* There are some rules that must be followed:
*
* I-cache Synch (all or range):
* The goal is to synchronize the instruction stream,
* so you may beed to write-back dirty D-cache blocks
* first. If a range is requested, and you can't
* synchronize just a range, you have to hit the whole
* thing.
*
* D-cache Write-Back and Invalidate range:
* If you can't WB-Inv a range, you must WB-Inv the
* entire D-cache.
*
* D-cache Invalidate:
* If you can't Inv the D-cache, you must Write-Back
* and Invalidate. Code that uses this operation
* MUST NOT assume that the D-cache will not be written
* back to memory.
*
* D-cache Write-Back:
* If you can't Write-back without doing an Inv,
* that's fine. Then treat this as a WB-Inv.
* Skipping the invalidate is merely an optimization.
*
* All operations:
* Valid virtual addresses must be passed to each
* cache operation.
*/
/* Other functions */
/* Soft functions */
};
extern struct cpu_functions cpufuncs;
int set_cpufuncs __P((void));
void cpufunc_nullop __P((void));
int cpufunc_null_fixup __P((void *));
int early_abort_fixup __P((void *));
int late_abort_fixup __P((void *));
#ifdef CPU_ARM3
void arm3_cache_flush __P((void));
#endif /* CPU_ARM3 */
void arm67_tlb_flush __P((void));
void arm67_cache_flush __P((void));
void arm67_context_switch __P((void));
#endif /* CPU_ARM6 || CPU_ARM7 */
#ifdef CPU_ARM6
void arm6_setup __P((char *));
#endif /* CPU_ARM6 */
#ifdef CPU_ARM7
void arm7_setup __P((char *));
#endif /* CPU_ARM7 */
#ifdef CPU_ARM7TDMI
int arm7_dataabt_fixup __P((void *));
void arm7tdmi_setup __P((char *));
void arm7tdmi_tlb_flushID __P((void));
void arm7tdmi_cache_flushID __P((void));
void arm7tdmi_context_switch __P((void));
#endif /* CPU_ARM7TDMI */
#ifdef CPU_ARM8
void arm8_tlb_flushID __P((void));
void arm8_cache_flushID __P((void));
void arm8_cache_cleanID __P((void));
void arm8_cache_purgeID __P((void));
void arm8_cache_syncI __P((void));
void arm8_context_switch __P((void));
void arm8_setup __P((char *));
#endif
#ifdef CPU_SA110
void sa110_setup __P((char *));
void sa110_context_switch __P((void));
#endif /* CPU_SA110 */
#if defined(CPU_SA1100) || defined(CPU_SA1110)
void sa11x0_drain_readbuf __P((void));
void sa11x0_context_switch __P((void));
void sa11x0_cpu_sleep __P((int));
void sa11x0_setup __P((char *));
#endif
void sa1_cache_flushID __P((void));
void sa1_cache_flushI __P((void));
void sa1_cache_flushD __P((void));
void sa1_cache_cleanID __P((void));
void sa1_cache_cleanD __P((void));
void sa1_cache_purgeID __P((void));
void sa1_cache_purgeD __P((void));
void sa1_cache_syncI __P((void));
#endif
#ifdef CPU_ARM9
void arm9_icache_sync_all __P((void));
void arm9_dcache_wbinv_all __P((void));
void arm9_idcache_wbinv_all __P((void));
void arm9_context_switch __P((void));
void arm9_setup __P((char *));
extern unsigned arm9_dcache_sets_max;
extern unsigned arm9_dcache_sets_inc;
extern unsigned arm9_dcache_index_max;
extern unsigned arm9_dcache_index_inc;
#endif
void arm10_context_switch __P((void));
void arm10_setup __P((char *));
#endif
#ifdef CPU_ARM11
void arm11_context_switch __P((void));
void arm11_tlb_flushID __P((void));
void arm11_tlb_flushI __P((void));
void arm11_tlb_flushD __P((void));
void arm11_drain_writebuf __P((void));
#endif
void armv5_ec_icache_sync_all __P((void));
void armv5_ec_dcache_wbinv_all __P((void));
void armv5_ec_idcache_wbinv_all __P((void));
#endif
void armv5_icache_sync_all __P((void));
void armv5_dcache_wbinv_all __P((void));
void armv5_idcache_wbinv_all __P((void));
extern unsigned armv5_dcache_sets_max;
extern unsigned armv5_dcache_sets_inc;
extern unsigned armv5_dcache_index_max;
extern unsigned armv5_dcache_index_inc;
#endif
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
void armv4_tlb_flushID __P((void));
void armv4_tlb_flushI __P((void));
void armv4_tlb_flushD __P((void));
void armv4_drain_writebuf __P((void));
#endif
#if defined(CPU_IXP12X0)
void ixp12x0_drain_readbuf __P((void));
void ixp12x0_context_switch __P((void));
void ixp12x0_setup __P((char *));
#endif
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
void xscale_cpwait __P((void));
void xscale_cpu_sleep __P((int));
void xscale_cache_flushID __P((void));
void xscale_cache_flushI __P((void));
void xscale_cache_flushD __P((void));
void xscale_cache_cleanID __P((void));
void xscale_cache_cleanD __P((void));
void xscale_cache_clean_minidata __P((void));
void xscale_cache_purgeID __P((void));
void xscale_cache_purgeD __P((void));
void xscale_cache_syncI __P((void));
void xscale_context_switch __P((void));
void xscale_setup __P((char *));
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
/*
* Macros for manipulating CPU interrupts
*/
#ifdef __PROG32
{
__asm volatile(
"mrs %0, cpsr\n" /* Get the CPSR */
"bic %1, %0, %2\n" /* Clear bits */
"eor %1, %1, %3\n" /* XOR bits */
"msr cpsr_c, %1\n" /* Set the control field of CPSR */
return ret;
}
#else /* ! __PROG32 */
#endif /* __PROG32 */
#ifdef __PROG32
/* Functions to manipulate the CPSR. */
#else
/* Functions to manipulate the processor control bits in r15. */
#endif /* __PROG32 */
/*
* Functions to manipulate cpu r13
* (in arm/arm32/setstack.S)
*/
/*
* Miscellany
*/
int get_pc_str_offset __P((void));
/*
* CPU functions from locore.S
*/
/*
* Cache info variables.
*/
/* PRIMARY CACHE VARIABLES */
extern int arm_picache_size;
extern int arm_picache_line_size;
extern int arm_picache_ways;
extern int arm_pdcache_size; /* and unified */
extern int arm_pdcache_line_size;
extern int arm_pdcache_ways;
extern int arm_pcache_type;
extern int arm_pcache_unified;
extern int arm_dcache_align;
extern int arm_dcache_align_mask;
#endif /* _KERNEL */
#endif /* _ARM32_CPUFUNC_H_ */
/* End of cpufunc.h */