4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync/** @file
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Header file for Pci shell Debug1 function.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync are licensed and made available under the terms and conditions of the BSD License
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync which accompanies this distribution. The full text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync http://opensource.org/licenses/bsd-license.php
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync**/
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#ifndef _EFI_SHELL_PCI_H_
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define _EFI_SHELL_PCI_H_
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef enum {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciDevice,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciP2pBridge,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciCardBusBridge,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciUndefined
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync} PCI_HEADER_TYPE;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define HEADER_TYPE_MULTI_FUNCTION 0x80
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define MAX_BUS_NUMBER 255
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define MAX_DEVICE_NUMBER 31
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define MAX_FUNCTION_NUMBER 7
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define EFI_PCI_CAPABILITY_ID_PCIX 0x07
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define CALC_EFI_PCI_ADDRESS(Bus, Dev, Func, Reg) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((UINT64) ((((UINTN) Bus) << 24) + (((UINTN) Dev) << 16) + (((UINTN) Func) << 8) + ((UINTN) Reg)))
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define CALC_EFI_PCIEX_ADDRESS(Bus, Dev, Func, ExReg) ( \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (UINT64) ((((UINTN) Bus) << 24) + (((UINTN) Dev) << 16) + (((UINTN) Func) << 8) + (LShiftU64 ((UINT64) ExReg, 32))) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync );
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define INDEX_OF(Field) ((UINT8 *) (Field) - (UINT8 *) mConfigSpace)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_0 0x00000001
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_1 0x00000002
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_2 0x00000004
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_3 0x00000008
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_4 0x00000010
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_5 0x00000020
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_6 0x00000040
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_7 0x00000080
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_8 0x00000100
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_9 0x00000200
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_10 0x00000400
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_11 0x00000800
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_12 0x00001000
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_13 0x00002000
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_14 0x00004000
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCI_BIT_15 0x00008000
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// PCIE device/port types
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_PCIE_ENDPOINT 0
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_LEGACY_PCIE_ENDPOINT 1
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_ROOT_COMPLEX_ROOT_PORT 4
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_SWITCH_UPSTREAM_PORT 5
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_SWITCH_DOWNSTREAM_PORT 6
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_PCIE_TO_PCIX_BRIDGE 7
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_PCIX_TO_PCIE_BRIDGE 8
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_ROOT_COMPLEX_INTEGRATED_PORT 9
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_ROOT_COMPLEX_EVENT_COLLECTOR 10
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_DEVICE_PORT_TYPE_MAX 11
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define IS_PCIE_ENDPOINT(DevicePortType) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((DevicePortType) == PCIE_PCIE_ENDPOINT || \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (DevicePortType) == PCIE_LEGACY_PCIE_ENDPOINT || \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (DevicePortType) == PCIE_ROOT_COMPLEX_INTEGRATED_PORT)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define IS_PCIE_SWITCH(DevicePortType) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) || \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (DevicePortType == PCIE_SWITCH_DOWNSTREAM_PORT))
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Capabilities Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_VERSION(PcieCapReg) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieCapReg) & 0x0f)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_DEVICEPORT_TYPE(PcieCapReg) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieCapReg) >> 4) & 0x0f)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SLOT_IMPLEMENTED(PcieCapReg) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieCapReg) >> 8) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_INT_MSG_NUM(PcieCapReg) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieCapReg) >> 9) & 0x1f)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Device Capabilities Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_MAX_PAYLOAD(PcieDeviceCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieDeviceCap) & 0x7)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PHANTOM_FUNC(PcieDeviceCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceCap) >> 3) & 0x3)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_EXTENDED_TAG(PcieDeviceCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceCap) >> 5) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_L0SLATENCY(PcieDeviceCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceCap) >> 6) & 0x7)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_L1LATENCY(PcieDeviceCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceCap) >> 9) & 0x7)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ERR_REPORTING(PcieDeviceCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceCap) >> 15) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SLOT_POWER_VALUE(PcieDeviceCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceCap) >> 18) & 0x0ff)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SLOT_POWER_SCALE(PcieDeviceCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceCap) >> 26) & 0x3)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_FUNC_LEVEL_RESET(PcieDeviceCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceCap) >> 28) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Device Control Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_COR_ERR_REPORTING_ENABLE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieDeviceControl) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 1) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_FATAL_ERR_REPORTING_ENABLE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 2) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 3) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_RELAXED_ORDERING_ENABLE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 4) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_MAX_PAYLOAD_SIZE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 5) & 0x7)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_EXTENDED_TAG_ENABLE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 8) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PHANTOM_FUNC_ENABLE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 9) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_AUX_PM_ENABLE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 10) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_NO_SNOOP_ENABLE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 11) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_MAX_READ_REQ_SIZE(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 12) & 0x7)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_BRG_CONF_RETRY(PcieDeviceControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceControl) >> 15) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Device Status Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_COR_ERR_DETECTED(PcieDeviceStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieDeviceStatus) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_NONFAT_ERR_DETECTED(PcieDeviceStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceStatus) >> 1) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_FATAL_ERR_DETECTED(PcieDeviceStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceStatus) >> 2) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_UNSUP_REQ_DETECTED(PcieDeviceStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceStatus) >> 3) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_AUX_POWER_DETECTED(PcieDeviceStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceStatus) >> 4) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_TRANSACTION_PENDING(PcieDeviceStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieDeviceStatus) >> 5) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Link Capabilities Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SUP_LINK_SPEEDS(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieLinkCap) & 0x0f)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkCap) >> 4) & 0x3f)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ASPM_SUPPORT(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkCap) >> 10) & 0x3)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_L0S_LATENCY(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkCap) >> 12) & 0x7)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_L1_LATENCY(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkCap) >> 15) & 0x7)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_CLOCK_PM(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkCap) >> 18) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SUP_DOWN_ERR_REPORTING(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkCap) >> 19) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_LINK_ACTIVE_REPORTING(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkCap) >> 20) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_LINK_BWD_NOTIF_CAP(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkCap) >> 21) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PORT_NUMBER(PcieLinkCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkCap) >> 24) & 0x0ff)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Link Control Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ASPM_CONTROL(PcieLinkControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieLinkControl) & 0x3)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_RCB(PcieLinkControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkControl) >> 3) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_LINK_DISABLE(PcieLinkControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkControl) >> 4) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_COMMON_CLK_CONF(PcieLinkControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkControl) >> 6) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_EXT_SYNC(PcieLinkControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkControl) >> 7) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_CLK_PWR_MNG(PcieLinkControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkControl) >> 8) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_HW_AUTO_WIDTH_DISABLE(PcieLinkControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkControl) >> 9) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_LINK_BDW_MNG_INT_EN(PcieLinkControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkControl) >> 10) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_LINK_AUTO_BDW_INT_EN(PcieLinkControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkControl) >> 11) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Link Status Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_CUR_LINK_SPEED(PcieLinkStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieLinkStatus) & 0x0f)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_NEGO_LINK_WIDTH(PcieLinkStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkStatus) >> 4) & 0x3f)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_LINK_TRAINING(PcieLinkStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkStatus) >> 11) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SLOT_CLK_CONF(PcieLinkStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkStatus) >> 12) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_DATA_LINK_ACTIVE(PcieLinkStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkStatus) >> 13) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_LINK_BDW_MNG_STAT(PcieLinkStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkStatus) >> 14) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_LINK_AUTO_BDW_STAT(PcieLinkStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieLinkStatus) >> 15) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Slot Capabilities Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ATT_BUT_PRESENT(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieSlotCap) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PWR_CTRLLER_PRESENT(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 1) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_MRL_SENSOR_PRESENT(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 2) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ATT_IND_PRESENT(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 3) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PWD_IND_PRESENT(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 4) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_HOTPLUG_SUPPRISE(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 5) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_HOTPLUG_CAPABLE(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 6) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SLOT_PWR_LIMIT_VALUE(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 7) & 0x0ff)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SLOT_PWR_LIMIT_SCALE(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 15) & 0x3)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ELEC_INTERLOCK_PRESENT(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 17) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_NO_COMM_COMPLETED_SUP(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 18) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PHY_SLOT_NUM(PcieSlotCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotCap) >> 19) & 0x1fff)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Slot Control Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ATT_BUT_ENABLE(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieSlotControl) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PWR_FLT_DETECT_ENABLE(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 1) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 2) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PRES_DETECT_CHANGE_ENABLE(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 3) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_COMM_CMPL_INT_ENABLE(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 4) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_HOTPLUG_INT_ENABLE(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 5) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ATT_IND_CTRL(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 6) & 0x3)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PWR_IND_CTRL(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 8) & 0x3)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PWR_CTRLLER_CTRL(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 10) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ELEC_INTERLOCK_CTRL(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 11) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_DLINK_STAT_CHANGE_ENABLE(PcieSlotControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotControl) >> 12) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Slot Status Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ATT_BUT_PRESSED(PcieSlotStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieSlotStatus) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PWR_FLT_DETECTED(PcieSlotStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotStatus) >> 1) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_MRL_SENSOR_CHANGED(PcieSlotStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotStatus) >> 2) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PRES_DETECT_CHANGED(PcieSlotStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotStatus) >> 3) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_COMM_COMPLETED(PcieSlotStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotStatus) >> 4) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_MRL_SENSOR_STATE(PcieSlotStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotStatus) >> 5) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PRES_DETECT_STATE(PcieSlotStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotStatus) >> 6) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_ELEC_INTERLOCK_STATE(PcieSlotStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotStatus) >> 7) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_DLINK_STAT_CHANGED(PcieSlotStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieSlotStatus) >> 8) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Root Control Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SYSERR_ON_CORERR_EN(PcieRootControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieRootControl) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SYSERR_ON_NONFATERR_EN(PcieRootControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieRootControl) >> 1) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_SYSERR_ON_FATERR_EN(PcieRootControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieRootControl) >> 2) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PME_INT_ENABLE(PcieRootControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieRootControl) >> 3) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_CRS_SW_VIS_ENABLE(PcieRootControl) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieRootControl) >> 4) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Root Capabilities Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_CRS_SW_VIS(PcieRootCap) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieRootCap) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Root Status Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PME_REQ_ID(PcieRootStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ((PcieRootStatus) & 0x0ffff)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PME_STATUS(PcieRootStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieRootStatus) >> 16) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#define PCIE_CAP_PME_PENDING(PcieRootStatus) \
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (((PcieRootStatus) >> 17) & 0x1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#pragma pack(1)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Common part of the PCI configuration space header for devices, P2P bridges,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// and cardbus bridges
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 VendorId;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 DeviceId;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 Command;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 Status;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 RevisionId;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 ClassCode[3];
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 CacheLineSize;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 PrimaryLatencyTimer;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 HeaderType;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 Bist;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync} PCI_COMMON_HEADER;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// PCI configuration space header for devices(after the common part)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 Bar[6]; // Base Address Registers
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 CardBusCISPtr; // CardBus CIS Pointer
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 SubVendorId; // Subsystem Vendor ID
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 SubSystemId; // Subsystem ID
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 ROMBar; // Expansion ROM Base Address
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 CapabilitiesPtr; // Capabilities Pointer
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 Reserved[3];
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 Reserved1;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 InterruptLine; // Interrupt Line
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 InterruptPin; // Interrupt Pin
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 MinGnt; // Min_Gnt
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 MaxLat; // Max_Lat
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync} PCI_DEVICE_HEADER;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// PCI configuration space header for pci-to-pci bridges(after the common part)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 Bar[2]; // Base Address Registers
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 PrimaryBus; // Primary Bus Number
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 SecondaryBus; // Secondary Bus Number
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 SubordinateBus; // Subordinate Bus Number
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 SecondaryLatencyTimer; // Secondary Latency Timer
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 IoBase; // I/O Base
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 IoLimit; // I/O Limit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 SecondaryStatus; // Secondary Status
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 MemoryBase; // Memory Base
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 MemoryLimit; // Memory Limit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 PrefetchableMemBase; // Pre-fetchable Memory Base
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 PrefetchableMemLimit; // Pre-fetchable Memory Limit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 PrefetchableBaseUpper; // Pre-fetchable Base Upper 32 bits
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 PrefetchableLimitUpper; // Pre-fetchable Limit Upper 32 bits
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 IoBaseUpper; // I/O Base Upper 16 bits
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 IoLimitUpper; // I/O Limit Upper 16 bits
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 CapabilitiesPtr; // Capabilities Pointer
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 Reserved[3];
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 ROMBar; // Expansion ROM Base Address
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 InterruptLine; // Interrupt Line
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 InterruptPin; // Interrupt Pin
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 BridgeControl; // Bridge Control
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync} PCI_BRIDGE_HEADER;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// PCI configuration space header for cardbus bridges(after the common part)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 CardBusSocketReg; // Cardus Socket/ExCA Base
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Address Register
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync //
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 CapabilitiesPtr; // 14h in pci-cardbus bridge.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 Reserved;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 SecondaryStatus; // Secondary Status
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 PciBusNumber; // PCI Bus Number
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 CardBusBusNumber; // CardBus Bus Number
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 SubordinateBusNumber; // Subordinate Bus Number
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 CardBusLatencyTimer; // CardBus Latency Timer
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 MemoryBase0; // Memory Base Register 0
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 MemoryLimit0; // Memory Limit Register 0
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 MemoryBase1;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 MemoryLimit1;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 IoBase0;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 IoLimit0; // I/O Base Register 0
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 IoBase1; // I/O Limit Register 0
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 IoLimit1;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 InterruptLine; // Interrupt Line
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 InterruptPin; // Interrupt Pin
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 BridgeControl; // Bridge Control
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync} PCI_CARDBUS_HEADER;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Data region after PCI configuration header(for cardbus bridge)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync//
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 SubVendorId; // Subsystem Vendor ID
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 SubSystemId; // Subsystem ID
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 LegacyBase; // Optional 16-Bit PC Card Legacy
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Mode Base Address
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync //
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 Data[46];
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync} PCI_CARDBUS_DATA;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef union {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCI_DEVICE_HEADER Device;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCI_BRIDGE_HEADER Bridge;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCI_CARDBUS_HEADER CardBus;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync} NON_COMMON_UNION;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCI_COMMON_HEADER Common;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync NON_COMMON_UNION NonCommon;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 Data[48];
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync} PCI_CONFIG_SPACE;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 PcieCapId;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT8 NextCapPtr;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 PcieCapReg;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 PcieDeviceCap;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 DeviceControl;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 DeviceStatus;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 LinkCap;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 LinkControl;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 LinkStatus;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 SlotCap;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 SlotControl;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 SlotStatus;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 RsvdP;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT16 RootControl;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync UINT32 RootStatus;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync} PCIE_CAP_STURCTURE;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#pragma pack()
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync#endif // _PCI_H_