4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Main file for Pci shell Debug1 function.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync are licensed and made available under the terms and conditions of the BSD License
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync which accompanies this distribution. The full text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Printable strings for Pci class code
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CHAR16 *BaseClass; // Pointer to the PCI base class string
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CHAR16 *SubClass; // Pointer to the PCI sub class string
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CHAR16 *PIFClass; // Pointer to the PCI programming interface string
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// a structure holding a single entry, which also points to its lower level
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync struct PCI_CLASS_ENTRY_TAG *LowerLevelClass; // Subclass or I/F if any
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Declarations of entries which contain printable strings for class codes
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// in PCI configuration space
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Base class strings entries
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Pre 2.0 device",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Mass Storage Controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Network Controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Display Controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Multimedia Device",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Memory Controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Bridge Device",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Simple Communications Controllers",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Base System Peripherals",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Input Devices",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Docking Stations",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Processors",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Serial Bus Controllers",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Wireless Controllers",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Intelligent IO Controllers",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Satellite Communications Controllers",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Encryption/Decryption Controllers",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Data Acquisition & Signal Processing Controllers",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Device does not fit in any defined classes",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Subclass strings entries
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"All devices other than VGA",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"VGA-compatible devices",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"SCSI controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"IDE controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Floppy disk controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"IPI controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"RAID controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other mass storage controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Ethernet controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Token ring controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"FDDI controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"ATM controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"ISDN controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other network controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"VGA/8514 controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"XGA controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"3D controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other display controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Video device",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Audio device",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Computer Telephony device",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other multimedia device",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"RAM memory controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Flash memory controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other memory controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"PCI/Micro Channel bridge",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"NuBus bridge",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"CardBus bridge",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"RACEway bridge",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other bridge type",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Serial controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Parallel port",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Multiport serial controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other communication device",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"DMA controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"System timer",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"RTC controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Generic PCI Hot-Plug controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other system peripheral",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Keyboard controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Digitizer (pen)",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Mouse controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Scanner controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Gameport controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other input controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Generic docking station",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other type of docking station",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Pentium",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"PowerPC",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Co-processor",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other processor",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Firewire(IEEE 1394)",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"ACCESS.bus",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Fibre Channel",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"System Management Bus",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other bus type",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"iRDA compatible controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Consumer IR controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"RF controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other type of wireless controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"I2O Architecture",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Network & computing Encrypt/Decrypt",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Entertainment Encrypt/Decrypt",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"DPIO modules",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Other DAQ & SP controllers",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Programming Interface entries
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"OM-primary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"PI-primary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"OM-primary, OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"PI-primary, OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"OM/PI-primary, OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"OM-primary, PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"PI-primary, PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"OM/PI-primary, PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"OM-primary, OM/PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"PI-primary, OM/PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, OM-primary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, PI-primary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, OM-primary, OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, PI-primary, OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, OM/PI-primary, OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, OM-primary, PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, PI-primary, PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, OM/PI-primary, PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, OM-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, OM-primary, OM/PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Master, PI-primary, OM/PI-secondary",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"VGA compatible",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"8514 compatible",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Subtractive decode",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Generic XT-compatible",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"16450-compatible",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"16550-compatible",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"16650-compatible",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"16750-compatible",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"16850-compatible",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"16950-compatible",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Bi-directional",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"ECP 1.X-compliant",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"IEEE 1284",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"IEEE 1284 target (not a controller)",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Generic",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Hayes-compatible 16450",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Hayes-compatible 16550",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Hayes-compatible 16650",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Hayes-compatible 16750",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Generic 8259",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"IO APIC",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"IO(x) APIC interrupt controller",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Generic 8237",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Generic 8254",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Generic",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Generic",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Universal Host Controller spec",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Open Host Controller spec",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"No specific programming interface",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"(Not Host Controller)",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Using 1394 OpenHCI spec",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Message FIFO at offset 40h",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Generates printable Unicode strings that represent PCI device class,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync subclass and programmed I/F based on a value passed to the function.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] ClassCode Value representing the PCI "Class Code" register read from a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCI device. The encodings are:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bits 23:16 - Base Class Code
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bits 15:8 - Sub-Class Code
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bits 7:0 - Programming Interface
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync printable class strings corresponding to ClassCode. The
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync caller must not modify the strings that are pointed by
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync the fields in ClassStrings.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Assume no strings found
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Go through all entries of the base class, until the entry with a matching
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // base class code is found. If reaches an entry with a null description
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // text, the last entry is met, which means no text for the base class was
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // found, so no more action is needed.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // A base class was found. Assign description, and check if this class has
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // sub-class defined. If sub-class defined, no more action is needed,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // otherwise, continue to find description for the sub-class code.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ClassStrings->BaseClass = CurrentClass[Index].DescText;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // find Subclass entry
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CurrentClass = CurrentClass[Index].LowerLevelClass;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Go through all entries of the sub-class, until the entry with a matching
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // sub-class code is found. If reaches an entry with a null description
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // text, the last entry is met, which means no text for the sub-class was
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // found, so no more action is needed.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // A class was found for the sub-class code. Assign description, and check if
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // this sub-class has programming interface defined. If no, no more action is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // needed, otherwise, continue to find description for the programming
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // interface.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ClassStrings->SubClass = CurrentClass[Index].DescText;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Find programming interface entry
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CurrentClass = CurrentClass[Index].LowerLevelClass;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Go through all entries of the I/F entries, until the entry with a
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // matching I/F code is found. If reaches an entry with a null description
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // text, the last entry is met, which means no text was found, so no more
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // action is needed.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // A class was found for the I/F code. Assign description, done!
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ClassStrings->PIFClass = CurrentClass[Index].DescText;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print strings that represent PCI device class, subclass and programmed I/F.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync configuation space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IncludePIF If the printed string should include the programming I/F part
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Get name from class code
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Only print base class and sub class name
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print base class, sub class, and programming inferface name
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"%s - %s",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function finds out the protocol which is in charge of the given
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync segment, and its bus range covers the current bus number. It lookes
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync each instances of RootBridgeIoProtocol handle, until the one meets the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync criteria is found.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Segment Segment number of device we are dealing with.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Bus Bus number of device we are dealing with.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_INVALID_PARAMETER Invalid parameter.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function gets the protocol interface from the given handle, and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync obtains its address space descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] Descriptors Points to the address space descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function get the next bus range of given address space descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync It also moves the pointer backward a node, to get prepared to be called
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in, out] Descriptors Points to current position of a serial of address space
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] MinBus The lower range of bus number.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] MaxBus The upper range of bus number.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] IsEnd Meet end of the serial of descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the data in PCI configuration space. The part which is common for
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCI device and bridge is interpreted in this function. It calls other
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync functions to interpret data unique for device or bridge.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] ConfigSpace Data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the device specific part of data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Device Data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the bridge specific part of data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Bridge Bridge specific data region in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the Base Address Register(Bar) in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Bar Points to the Base Address Register intended to interpret.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Command Points to the register Command.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in, out] Index The Index.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the cardbus specific part of data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] CardBus CardBus specific region of PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain each meaningful bit of register Status. The definition of Status is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync slightly different depending on the PCI header type.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Status Points to the content of register Status.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] MainStatus Indicates if this register is main status(not secondary
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] HeaderType Header type of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain each meaningful bit of register Command.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Command Points to the content of register Command.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain each meaningful bit of register Bridge Control.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] BridgeControl Points to the content of register Bridge Control.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] HeaderType The headertype.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print each capability structure.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev The pointer to the deivce.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address The address to start at.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] CapPtr The offset from the address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Display Pcie device structure.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev The pointer to the root pci protocol.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address The Address to start at.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] CapabilityPtr The offset from the address to start.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the capability information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device capability information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device control information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device status information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device link information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device link control information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device link status information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device slot information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device slot control information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device slot status information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device root information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device root capability information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device root status information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef enum {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef enum {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsynctypedef struct
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync// Global Variables
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"PCI Express Endpoint",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Legacy PCI Express Endpoint",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Unknown Type",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Unknonw Type",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Root Port of PCI Express Root Complex",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Upstream Port of PCI Express Switch",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Downstream Port of PCI Express Switch",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"PCI Express to PCI/PCI-X Bridge",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"PCI/PCI-X to PCI Express Bridge",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Root Complex Integrated Endpoint",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Root Complex Event Collector"
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Less than 64ns",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"64ns to less than 128ns",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"128ns to less than 256ns",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"256ns to less than 512ns",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"512ns to less than 1us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"1us to less than 2us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"2us-4us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"More than 4us"
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Less than 1us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"1us to less than 2us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"2us to less than 4us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"4us to less than 8us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"8us to less than 16us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"16us to less than 32us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"32us-64us",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"More than 64us"
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Disabled",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"L0s Entry Enabled",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"L1 Entry Enabled",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"L0s and L1 Entry Enabled"
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L"Reserved",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Function for 'pci' command.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] ImageHandle Handle to the Image (NULL if Internal).
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] SystemTable Pointer to the System Table (NULL if Internal).
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // initialize the shell lib (we must be in non-auto-init...)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // parse the command line
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // space for handles and call it again.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Argument Count == 1(no other argument): enumerate all pci functions
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // For each handle, which decides a segment and a bus number range,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // enumerate all devices on it.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // No document say it's impossible for a RootBridgeIo protocol handle
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // to have more than one address space descriptors, so find out every
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // bus range and for each of them do device enumeration.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // For each devices, enumerate all functions it contains
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // For each function, read its configuration space and print summary
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // If VendorId = 0xffff, there does not exist a device at this
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // location. For each device, if there is any function on it,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // there must be 1 function at Function 0. So if Func = 0, there
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // will be no more functions in the same device, so we can break
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // loop to deal with the next device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_TITLE), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P1), gShellDebug1HiiHandle,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync -1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_P2), gShellDebug1HiiHandle,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (ScreenCount >= ScreenSize && ScreenSize != 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // If ScreenSize == 0 we have the console redirected so don't
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // block updates
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // If this is not a multi-function device, we can leave the loop
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // to deal with the next device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (Func == 0 && ((PciHeader.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00)) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // devices on all bus, we can leave loop.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // The first Argument(except "-i") is assumed to be Bus number, second
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // to be Device number, and third to be Func number.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Find the protocol interface who's in charge of current segment, and its
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // bus range covers the current bus
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Address = CALC_EFI_PCI_ADDRESS (Bus, Device, Func, 0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Dump standard header of configuration space
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync SizeOfHeader = sizeof (ConfigSpace.Common) + sizeof (ConfigSpace.NonCommon);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Dump device dependent Part of configuration space
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // If "-i" appears in command line, interpret data in configuration space
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Status = PciExplainData (&ConfigSpace, Address, IoDev);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function finds out the protocol which is in charge of the given
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync segment, and its bus range covers the current bus number. It lookes
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync each instances of RootBridgeIoProtocol handle, until the one meets the
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync criteria is found.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Segment Segment number of device we are dealing with.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Bus Bus number of device we are dealing with.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_INVALID_PARAMETER Invalid parameter.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Go through all handles, until the one meets the criteria is found
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Status = PciGetProtocolAndResource (HandleBuf[Index], IoDev, &Descriptors);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // When Descriptors == NULL, the Configuration() is not implemented,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // so we only check the Segment number
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (Descriptors == NULL && Segment == (*IoDev)->SegmentNumber) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function gets the protocol interface from the given handle, and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync obtains its address space descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] Descriptors Points to the address space descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Get inferface from protocol
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Call Configuration() to get address space descriptors
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Status = (*IoDev)->Configuration (*IoDev, (VOID**)Descriptors);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync This function get the next bus range of given address space descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync It also moves the pointer backward a node, to get prepared to be called
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in, out] Descriptors Points to current position of a serial of address space
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] MinBus The lower range of bus number.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] MaxBus The upper range of bus number.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[out] IsEnd Meet end of the serial of descriptors.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR **Descriptors,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // When *Descriptors is NULL, Configuration() is not implemented, so assume
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // range is 0~PCI_MAX_BUS
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // *Descriptors points to one or more address space descriptors, which
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // ends with a end tagged descriptor. Examine each of the descriptors,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // if a bus typed one is found and its bus range covers bus, this handle
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // is the handle we are looking for.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync while ((*Descriptors)->Desc != ACPI_END_TAG_DESCRIPTOR) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if ((*Descriptors)->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if ((*Descriptors)->Desc == ACPI_END_TAG_DESCRIPTOR) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the data in PCI configuration space. The part which is common for
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCI device and bridge is interpreted in this function. It calls other
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync functions to interpret data unique for device or bridge.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] ConfigSpace Data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print Vendor Id and Device Id
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_VID_DID), gShellDebug1HiiHandle,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Command
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Status
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciExplainStatus (&(Common->Status), TRUE, PciUndefined);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Revision ID
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_RID), gShellDebug1HiiHandle,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register BIST
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP_NO), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Cache Line Size
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Latency Timer
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Header Type
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync HeaderType = (PCI_HEADER_TYPE)(UINT8) (Common->HeaderType & 0x7f);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_PCI_DEVICE), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_P2P_BRIDGE), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Class Code
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CLASS), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciPrintClassCode ((UINT8 *) Common->ClassCode, TRUE);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Interpret remaining part of PCI configuration header depending on
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // HeaderType
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CapPtr = ConfigSpace->NonCommon.Device.CapabilitiesPtr;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CapPtr = ConfigSpace->NonCommon.Bridge.CapabilitiesPtr;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CapPtr = ConfigSpace->NonCommon.CardBus.CapabilitiesPtr;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // If Status bit4 is 1, dump or explain capability structure
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if ((Common->Status) & EFI_PCI_STATUS_CAPABILITY) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciExplainCapabilityStruct (IoDev, Address, CapPtr);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the device specific part of data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Device Data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // exist. If these no Bar for this function, print "none", otherwise
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // list detail information about this Bar.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BarCount = sizeof (Device->Bar) / sizeof (Device->Bar[0]);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L" --------------------------------------------------------------------------");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"\n --------------------------------------------------------------------------");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Expansion ROM Base Address
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Cardbus CIS ptr
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Sub-vendor ID and subsystem ID
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Capabilities Ptr
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Interrupt Line and interrupt pin
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Min_Gnt and Max_Lat
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the bridge specific part of data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Bridge Bridge specific data region in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print Base Address Registers. When Bar = 0, this Bar does not
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // exist. If these no Bar for this function, print "none", otherwise
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // list detail information about this Bar.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync BarCount = sizeof (Bridge->Bar) / sizeof (Bridge->Bar[0]);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_START_TYPE_2), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L" --------------------------------------------------------------------------");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NONE), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"\n --------------------------------------------------------------------------");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Expansion register ROM Base Address
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print Bus Numbers(Primary, Secondary, and Subordinate
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L" ------------------------------------------------------\n");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Secondary Latency Timer
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Secondary Status
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciExplainStatus (&(Bridge->SecondaryStatus), FALSE, PciP2pBridge);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print I/O and memory ranges this bridge forwards. There are 3 resource
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // types: I/O, memory, and pre-fetchable memory. For each resource type,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // base and limit address are listed.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"----------------------------------------------------------------------\n");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // IO Base & Limit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoAddress32 = (Bridge->IoBaseUpper << 16 | Bridge->IoBase << 8);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoAddress32 = (Bridge->IoLimitUpper << 16 | Bridge->IoLimit << 8);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR), gShellDebug1HiiHandle, IoAddress32);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Memory Base & Limit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Pre-fetch-able Memory Base & Limit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Capabilities Pointer
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Bridge Control
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciExplainBridgeControl (&(Bridge->BridgeControl), PciP2pBridge);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Interrupt Line & PIN
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the Base Address Register(Bar) in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Bar Points to the Base Address Register intended to interpret.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Command Points to the register Command.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in, out] Index The Index.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // According the bar type, list detail about this bar, for example: 32 or
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // 64 bits; pre-fetchable or not.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // This bar is of memory type
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) == 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_32_BITS), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync } else if ((*Bar & PCI_BIT_1) == 0 && (*Bar & PCI_BIT_2) != 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_64_BITS), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Reserved
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEM_2), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_YES), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // This bar is of io type
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Get BAR length(or the amount of resource this bar demands for). To get
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Bar length, first we should temporarily disable I/O and memory access
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // of this function(by set bits in the register Command), then write all
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // "1"s to this bar. The bar value read back is the amount of resource
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // this bar demands for.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Disable io & mem access
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &NewCommand);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Read after write the BAR to get the size
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 1, &NewBar32);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 1, &OldBar32);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoDev->Pci.Read (IoDev, EfiPciWidthUint32, RegAddress, 2, &NewBar64);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoDev->Pci.Write (IoDev, EfiPciWidthUint32, RegAddress, 2, &OldBar64);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Enable io & mem access
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoDev->Pci.Write (IoDev, EfiPciWidthUint16, RegAddress, 1, &OldCommand);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32), gShellDebug1HiiHandle, NewBar32);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, RShiftU64 (NewBar64, 32));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync RShiftU64 ((NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1), 32)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_3), gShellDebug1HiiHandle, NewBar32);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain the cardbus specific part of data in PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] CardBus CardBus specific region of PCI configuration space.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address Address used to access configuration space of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev Handle used to access configuration space of PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print Secondary Status
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciExplainStatus (&(CardBus->SecondaryStatus), FALSE, PciCardBusBridge);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print Bus Numbers(Primary bus number, CardBus bus number, and
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Subordinate bus number
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L" ------------------------------------------------------\n");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print CardBus Latency Timer
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print Memory/Io ranges this cardbus bridge forwards
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"----------------------------------------------------------------------\n");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CardBus->BridgeControl & PCI_BIT_8 ? L" Prefetchable" : L"Non-Prefetchable",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CardBus->BridgeControl & PCI_BIT_9 ? L" Prefetchable" : L"Non-Prefetchable",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Io32Bit = (BOOLEAN) (CardBus->IoBase0 & PCI_BIT_0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CardBus->IoBase0 & (Io32Bit ? 0xfffffffc : 0x0000fffc),
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (CardBus->IoLimit0 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Io32Bit = (BOOLEAN) (CardBus->IoBase1 & PCI_BIT_0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CardBus->IoBase1 & (Io32Bit ? 0xfffffffc : 0x0000fffc),
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (CardBus->IoLimit1 & (Io32Bit ? 0xffffffff : 0x0000ffff)) | 0x00000003
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Interrupt Line & PIN
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print register Bridge Control
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciExplainBridgeControl (&(CardBus->BridgeControl), PciCardBusBridge);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print some registers in data region of PCI configuration space for cardbus
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync CardBusData = (PCI_CARDBUS_DATA *) ((UINT8 *) CardBus + sizeof (PCI_CARDBUS_HEADER));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain each meaningful bit of register Status. The definition of Status is
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync slightly different depending on the PCI header type.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Status Points to the content of register Status.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] MainStatus Indicates if this register is main status(not secondary
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] HeaderType Header type of this PCI device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Bit 5 is meaningless for CardBus Bridge
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Bit 9 and bit 10 together decides the DEVSEL timing
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) == 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync } else if ((*Status & PCI_BIT_9) != 0 && (*Status & PCI_BIT_10) == 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MEDIUM), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync } else if ((*Status & PCI_BIT_9) == 0 && (*Status & PCI_BIT_10) != 0) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SLOW), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RESERVED_2), gShellDebug1HiiHandle);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain each meaningful bit of register Command.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Command Points to the content of register Command.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Print the binary value of register Command
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Explain register Command bit by bit
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Explain each meaningful bit of register Bridge Control.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] BridgeControl Points to the content of register Bridge Control.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] HeaderType The headertype.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The command completed successfully.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Register Bridge Control has some slight differences between P2P bridge
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // and Cardbus bridge from bit 6 to bit 11.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (*BridgeControl & PCI_BIT_8)!=0 ? L"2^10" : L"2^15"
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync (*BridgeControl & PCI_BIT_9)!=0 ? L"2^10" : L"2^15"
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print each capability structure.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev The pointer to the deivce.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address The address to start at.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] CapPtr The offset from the address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Go through the Capability list
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync while ((CapabilityPtr >= 0x40) && ((CapabilityPtr & 0x03) == 0x00)) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IoDev->Pci.Read (IoDev, EfiPciWidthUint16, RegAddress, 1, &CapabilityEntry);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Explain PciExpress data
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PciExplainPciExpress (IoDev, Address, CapabilityPtr);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Explain other capabilities here
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the capability information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Capability Version(3:0): %E0x%04x%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if ((UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) < PCIE_DEVICE_PORT_TYPE_MAX) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DevicePortType = DevicePortTypeTable[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg)];
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Device/PortType(7:4): %E%s%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // 'Slot Implemented' is only valid for:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // a) Root Port of PCI Express Root Complex, or
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // b) Downstream Port of PCI Express Switch
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_ROOT_COMPLEX_ROOT_PORT ||
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_SWITCH_DOWNSTREAM_PORT) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Slot Implemented(8): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Interrupt Message Number(13:9): %E0x%05x%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device capability information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap) + 7));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Phantom Functions Supported(4:3): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L0sLatency = (UINT8) PCIE_CAP_L0SLATENCY (PcieDeviceCap);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L1Latency = (UINT8) PCIE_CAP_L1LATENCY (PcieDeviceCap);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L" Endpoint L0s Acceptable Latency(8:6): ");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"%EMaximum of %d ns%N\n", 1 << (L0sLatency + 6));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"%EMaximum of %d us%N\n", 1 << (L0sLatency - 3));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L" Endpoint L1 Acceptable Latency(11:9): ");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"%EMaximum of %d us%N\n", 1 << (L1Latency + 1));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Role-based Error Reporting(15): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Only valid for Upstream Port:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // a) Captured Slot Power Limit Value
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // b) Captured Slot Power Scale
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync SlotPwrLmtScaleTable[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap)]
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Function Level Reset Capability is only valid for Endpoint
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Function Level Reset Capability(28): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device control information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Correctable Error Reporting Enable(0): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Fatal Error Reporting Enable(2): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Unsupported Request Reporting Enable(3): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Enable Relaxed Ordering(4): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) < 6) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl) + 7));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Extended Tag Field Enable(8): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Phantom Functions Enable(9): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Enable No Snoop(11): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) < 6) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl) + 7));
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg) == PCIE_PCIE_TO_PCIX_BRIDGE) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Bridge Configuration Retry Enable(15): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device status information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Correctable Error Detected(0): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Non-Fatal Error Detected(1): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Fatal Error Detected(2): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Unsupported Request Detected(3): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" AUX Power Detected(4): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Transactions Pending(5): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device link information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Supported Link Speeds(3:0): %E%s supported%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Maximum Link Width(9:4): %Ex%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Active State Power Management Support(11:10): %E%s Supported%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" L0s Exit Latency(14:12): %E%s%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L0sLatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" L1 Exit Latency(17:15): %E%s%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L1LatencyStrTable[PCIE_CAP_L0S_LATENCY (PcieLinkCap)]
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Clock Power Management(18): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Surprise Down Error Reporting Capable(19): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Link Bandwidth Notification Capability(21): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Port Number(31:24): %E0x%02x%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device link control information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap->PcieCapReg);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Active State Power Management Control(1:0): %E%s%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ASPMCtrlStrTable[PCIE_CAP_ASPM_CONTROL (PcieLinkControl)]
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // RCB is not applicable to switches
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Link Disable is reserved on
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // a) Endpoints
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // b) PCI Express to PCI/PCI-X bridges
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // c) Upstream Ports of Switches
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Link Disable(4): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Common Clock Configuration(6): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Extended Synch(7): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Enable Clock Power Management(8): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Hardware Autonomous Width Disable(9): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device link status information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Current Link Speed(3:0): %E%s%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Negotiated Link Width(9:4): %Ex%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Link Training(11): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Slot Clock Configuration(12): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Data Link Layer Link Active(13): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Link Bandwidth Management Status(14): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Link Autonomous Bandwidth Status(15): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device slot information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Attention Button Present(0): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Power Controller Present(1): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" MRL Sensor Present(2): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Attention Indicator Present(3): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Power Indicator Present(4): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Hot-Plug Surprise(5): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Hot-Plug Capable(6): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Slot Power Limit Value(14:7): %E0x%02x%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Slot Power Limit Scale(16:15): %E%s%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync SlotPwrLmtScaleTable[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap)]
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Electromechanical Interlock Present(17): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" No Command Completed Support(18): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Physical Slot Number(31:19): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device slot control information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Attention Button Pressed Enable(0): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Power Fault Detected Enable(1): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" MRL Sensor Changed Enable(2): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Presence Detect Changed Enable(3): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Command Completed Interrupt Enable(4): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Hot-Plug Interrupt Enable(5): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Attention Indicator Control(7:6): %E%s%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IndicatorTable[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl)]
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Power Indicator Control(9:8): %E%s%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync IndicatorTable[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl)]
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L" Power Controller Control(10): %EPower ");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Electromechanical Interlock Control(11): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Data Link Layer State Changed Enable(12): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device slot status information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Attention Button Pressed(0): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Power Fault Detected(1): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" MRL Sensor Changed(2): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Presence Detect Changed(3): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Command Completed(4): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus)) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" Data Link Layer State Changed(8): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device root information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" System Error on Correctable Error Enable(0): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" System Error on Fatal Error Enable(2): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" PME Interrupt Enable(3): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" CRS Software Visibility Enable(4): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device root capability information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" CRS Software Visibility(0): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print out information of the device root status information.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] PciExpressCap The pointer to the structure about the device.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @retval EFI_SUCCESS The operation was successful.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" PME Requester ID(15:0): %E0x%04x%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" PME Status(16): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync L" PME Pending(17): %E%d%N\n",
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Display Pcie device structure.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] IoDev The pointer to the root pci protocol.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] Address The Address to start at.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync @param[in] CapabilityPtr The offset from the address to start.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DevicePortType = (UINT8) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap.PcieCapReg);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"\nPci Express device capability structure:\n");
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync for (Index = 0; PcieExplainList[Index].Type < PcieExplainTypeMax; Index++) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync RegAddr = ((UINT8 *) &PciExpressCap) + PcieExplainList[Index].Offset;
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Link registers should not be used by
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // a) Root Complex Integrated Endpoint
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // b) Root Complex Event Collector
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (DevicePortType == PCIE_ROOT_COMPLEX_INTEGRATED_PORT ||
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync DevicePortType == PCIE_ROOT_COMPLEX_EVENT_COLLECTOR) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Slot registers are only valid for
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // a) Root Port of PCI Express Root Complex
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // b) Downstream Port of PCI Express Switch
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // and when SlotImplemented bit is set in PCIE cap register.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap.PcieCapReg)) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Root registers are only valid for
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Root Port of PCI Express Root Complex
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Pciex_Address = CALC_EFI_PCIEX_ADDRESS (Bus, Dev, Func, 0x100);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ExRegBuffer = (UINT8 *) AllocateZeroPool (ExtendRegSize);
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // PciRootBridgeIo protocol should support pci express extend space IO
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // (Begins at offset 0x100)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync // Start outputing PciEx extend space( 0xFF-0xFFF)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");