/** @file
Main file for Pci shell Debug1 function.
Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "UefiShellDebug1CommandsLib.h"
#include <Protocol/PciRootBridgeIo.h>
#include <Library/ShellLib.h>
#include <IndustryStandard/Pci.h>
#include <IndustryStandard/Acpi.h>
#include "Pci.h"
//
// Printable strings for Pci class code
//
typedef struct {
//
// a structure holding a single entry, which also points to its lower level
// class
//
typedef struct PCI_CLASS_ENTRY_TAG {
//
// Declarations of entries which contain printable strings for class codes
// in PCI configuration space
//
//
// Base class strings entries
//
{
0x00,
L"Pre 2.0 device",
},
{
0x01,
L"Mass Storage Controller",
},
{
0x02,
L"Network Controller",
},
{
0x03,
L"Display Controller",
},
{
0x04,
L"Multimedia Device",
},
{
0x05,
L"Memory Controller",
},
{
0x06,
L"Bridge Device",
},
{
0x07,
L"Simple Communications Controllers",
},
{
0x08,
L"Base System Peripherals",
},
{
0x09,
L"Input Devices",
},
{
0x0a,
L"Docking Stations",
},
{
0x0b,
L"Processors",
},
{
0x0c,
L"Serial Bus Controllers",
},
{
0x0d,
L"Wireless Controllers",
},
{
0x0e,
L"Intelligent IO Controllers",
},
{
0x0f,
L"Satellite Communications Controllers",
},
{
0x10,
L"Encryption/Decryption Controllers",
},
{
0x11,
L"Data Acquisition & Signal Processing Controllers",
},
{
0xff,
L"Device does not fit in any defined classes",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
//
// Subclass strings entries
//
{
0x00,
L"",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"All devices other than VGA",
},
{
0x01,
L"VGA-compatible devices",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"SCSI controller",
},
{
0x01,
L"IDE controller",
},
{
0x02,
L"Floppy disk controller",
},
{
0x03,
L"IPI controller",
},
{
0x04,
L"RAID controller",
},
{
0x80,
L"Other mass storage controller",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Ethernet controller",
},
{
0x01,
L"Token ring controller",
},
{
0x02,
L"FDDI controller",
},
{
0x03,
L"ATM controller",
},
{
0x04,
L"ISDN controller",
},
{
0x80,
L"Other network controller",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"VGA/8514 controller",
},
{
0x01,
L"XGA controller",
},
{
0x02,
L"3D controller",
},
{
0x80,
L"Other display controller",
},
{
0x00,
NULL,
/* null string ends the list */PCIBlankEntry
}
};
{
0x00,
L"Video device",
},
{
0x01,
L"Audio device",
},
{
0x02,
L"Computer Telephony device",
},
{
0x80,
L"Other multimedia device",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"RAM memory controller",
},
{
0x01,
L"Flash memory controller",
},
{
0x80,
L"Other memory controller",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
},
{
0x01,
},
{
0x02,
},
{
0x03,
},
{
0x04,
},
{
0x05,
},
{
0x06,
L"NuBus bridge",
},
{
0x07,
L"CardBus bridge",
},
{
0x08,
L"RACEway bridge",
},
{
0x80,
L"Other bridge type",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Serial controller",
},
{
0x01,
L"Parallel port",
},
{
0x02,
L"Multiport serial controller",
},
{
0x03,
L"Modem",
},
{
0x80,
L"Other communication device",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"PIC",
},
{
0x01,
L"DMA controller",
},
{
0x02,
L"System timer",
},
{
0x03,
L"RTC controller",
},
{
0x04,
L"Generic PCI Hot-Plug controller",
},
{
0x80,
L"Other system peripheral",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Keyboard controller",
},
{
0x01,
L"Digitizer (pen)",
},
{
0x02,
L"Mouse controller",
},
{
0x03,
L"Scanner controller",
},
{
0x04,
L"Gameport controller",
},
{
0x80,
L"Other input controller",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Generic docking station",
},
{
0x80,
L"Other type of docking station",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"386",
},
{
0x01,
L"486",
},
{
0x02,
L"Pentium",
},
{
0x10,
L"Alpha",
},
{
0x20,
L"PowerPC",
},
{
0x30,
L"MIPS",
},
{
0x40,
L"Co-processor",
},
{
0x80,
L"Other processor",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Firewire(IEEE 1394)",
},
{
0x01,
L"ACCESS.bus",
},
{
0x02,
L"SSA",
},
{
0x03,
L"USB",
},
{
0x04,
L"Fibre Channel",
},
{
0x05,
L"System Management Bus",
},
{
0x80,
L"Other bus type",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"iRDA compatible controller",
},
{
0x01,
L"Consumer IR controller",
},
{
0x10,
L"RF controller",
},
{
0x80,
L"Other type of wireless controller",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"I2O Architecture",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"TV",
},
{
0x01,
L"Audio",
},
{
0x02,
L"Voice",
},
{
0x03,
L"Data",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
},
{
0x01,
},
{
0x80,
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"DPIO modules",
},
{
0x80,
L"Other DAQ & SP controllers",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
//
// Programming Interface entries
//
{
0x00,
L"",
},
{
0x01,
L"OM-primary",
},
{
0x02,
L"PI-primary",
},
{
0x03,
L"OM/PI-primary",
},
{
0x04,
L"OM-secondary",
},
{
0x05,
L"OM-primary, OM-secondary",
},
{
0x06,
L"PI-primary, OM-secondary",
},
{
0x07,
L"OM/PI-primary, OM-secondary",
},
{
0x08,
L"OM-secondary",
},
{
0x09,
L"OM-primary, PI-secondary",
},
{
0x0a,
L"PI-primary, PI-secondary",
},
{
0x0b,
L"OM/PI-primary, PI-secondary",
},
{
0x0c,
L"OM-secondary",
},
{
0x0d,
L"OM-primary, OM/PI-secondary",
},
{
0x0e,
L"PI-primary, OM/PI-secondary",
},
{
0x0f,
L"OM/PI-primary, OM/PI-secondary",
},
{
0x80,
L"Master",
},
{
0x81,
L"Master, OM-primary",
},
{
0x82,
L"Master, PI-primary",
},
{
0x83,
L"Master, OM/PI-primary",
},
{
0x84,
L"Master, OM-secondary",
},
{
0x85,
L"Master, OM-primary, OM-secondary",
},
{
0x86,
L"Master, PI-primary, OM-secondary",
},
{
0x87,
L"Master, OM/PI-primary, OM-secondary",
},
{
0x88,
L"Master, OM-secondary",
},
{
0x89,
L"Master, OM-primary, PI-secondary",
},
{
0x8a,
L"Master, PI-primary, PI-secondary",
},
{
0x8b,
L"Master, OM/PI-primary, PI-secondary",
},
{
0x8c,
L"Master, OM-secondary",
},
{
0x8d,
L"Master, OM-primary, OM/PI-secondary",
},
{
0x8e,
L"Master, PI-primary, OM/PI-secondary",
},
{
0x8f,
L"Master, OM/PI-primary, OM/PI-secondary",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"VGA compatible",
},
{
0x01,
L"8514 compatible",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"",
},
{
0x01,
L"Subtractive decode",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Generic XT-compatible",
},
{
0x01,
L"16450-compatible",
},
{
0x02,
L"16550-compatible",
},
{
0x03,
L"16650-compatible",
},
{
0x04,
L"16750-compatible",
},
{
0x05,
L"16850-compatible",
},
{
0x06,
L"16950-compatible",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"",
},
{
0x01,
L"Bi-directional",
},
{
0x02,
L"ECP 1.X-compliant",
},
{
0x03,
L"IEEE 1284",
},
{
0xfe,
L"IEEE 1284 target (not a controller)",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Generic",
},
{
0x01,
L"Hayes-compatible 16450",
},
{
0x02,
L"Hayes-compatible 16550",
},
{
0x03,
L"Hayes-compatible 16650",
},
{
0x04,
L"Hayes-compatible 16750",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Generic 8259",
},
{
0x01,
L"ISA",
},
{
0x02,
L"EISA",
},
{
0x10,
L"IO APIC",
},
{
0x20,
L"IO(x) APIC interrupt controller",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Generic 8237",
},
{
0x01,
L"ISA",
},
{
0x02,
L"EISA",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Generic 8254",
},
{
0x01,
L"ISA",
},
{
0x02,
L"EISA",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Generic",
},
{
0x01,
L"ISA",
},
{
0x02,
L"EISA",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Generic",
},
{
0x10,
L"",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Universal Host Controller spec",
},
{
0x10,
L"Open Host Controller spec",
},
{
0x80,
L"No specific programming interface",
},
{
0xfe,
L"(Not Host Controller)",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"",
},
{
0x10,
L"Using 1394 OpenHCI spec",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
{
0x00,
L"Message FIFO at offset 40h",
},
{
0x01,
L"",
},
{
0x00,
NULL,
/* null string ends the list */NULL
}
};
/**
Generates printable Unicode strings that represent PCI device class,
subclass and programmed I/F based on a value passed to the function.
@param[in] ClassCode Value representing the PCI "Class Code" register read from a
PCI device. The encodings are:
bits 23:16 - Base Class Code
bits 15:8 - Sub-Class Code
bits 7:0 - Programming Interface
@param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
printable class strings corresponding to ClassCode. The
caller must not modify the strings that are pointed by
the fields in ClassStrings.
**/
)
{
//
// Assume no strings found
//
Index = 0;
//
// Go through all entries of the base class, until the entry with a matching
// base class code is found. If reaches an entry with a null description
// text, the last entry is met, which means no text for the base class was
// found, so no more action is needed.
//
return ;
}
Index++;
}
//
// A base class was found. Assign description, and check if this class has
// sub-class defined. If sub-class defined, no more action is needed,
// otherwise, continue to find description for the sub-class code.
//
return ;
}
//
// find Subclass entry
//
Index = 0;
//
// Go through all entries of the sub-class, until the entry with a matching
// sub-class code is found. If reaches an entry with a null description
// text, the last entry is met, which means no text for the sub-class was
// found, so no more action is needed.
//
return ;
}
Index++;
}
//
// A class was found for the sub-class code. Assign description, and check if
// this sub-class has programming interface defined. If no, no more action is
// needed, otherwise, continue to find description for the programming
// interface.
//
return ;
}
//
// Find programming interface entry
//
Index = 0;
//
// Go through all entries of the I/F entries, until the entry with a
// matching I/F code is found. If reaches an entry with a null description
// text, the last entry is met, which means no text was found, so no more
// action is needed.
//
return ;
}
Index++;
}
//
// A class was found for the I/F code. Assign description, done!
//
return ;
}
/**
Print strings that represent PCI device class, subclass and programmed I/F.
@param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
configuation space.
@param[in] IncludePIF If the printed string should include the programming I/F part
**/
)
{
ClassCode = 0;
ClassCode |= ClassCodePtr[0];
//
// Get name from class code
//
if (IncludePIF) {
//
// Only print base class and sub class name
//
);
} else {
//
// Print base class, sub class, and programming inferface name
//
PCI_CLASS_STRING_LIMIT * sizeof (CHAR16),
L"%s - %s",
);
}
}
/**
This function finds out the protocol which is in charge of the given
segment, and its bus range covers the current bus number. It lookes
each instances of RootBridgeIoProtocol handle, until the one meets the
criteria is found.
@param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
@param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
@param[in] Segment Segment number of device we are dealing with.
@param[in] Bus Bus number of device we are dealing with.
@param[out] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
@retval EFI_INVALID_PARAMETER Invalid parameter.
**/
);
/**
This function gets the protocol interface from the given handle, and
obtains its address space descriptors.
@param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
@param[out] IoDev Handle used to access configuration space of PCI device.
@param[out] Descriptors Points to the address space descriptors.
@retval EFI_SUCCESS The command completed successfully
**/
);
/**
This function get the next bus range of given address space descriptors.
It also moves the pointer backward a node, to get prepared to be called
again.
@param[in, out] Descriptors Points to current position of a serial of address space
descriptors.
@param[out] MinBus The lower range of bus number.
@param[out] MaxBus The upper range of bus number.
@param[out] IsEnd Meet end of the serial of descriptors.
@retval EFI_SUCCESS The command completed successfully.
**/
);
/**
Explain the data in PCI configuration space. The part which is common for
PCI device and bridge is interpreted in this function. It calls other
functions to interpret data unique for device or bridge.
@param[in] ConfigSpace Data in PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
);
/**
Explain the device specific part of data in PCI configuration space.
@param[in] Device Data in PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
);
/**
Explain the bridge specific part of data in PCI configuration space.
@param[in] Bridge Bridge specific data region in PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
);
/**
Explain the Base Address Register(Bar) in PCI configuration space.
@param[in] Bar Points to the Base Address Register intended to interpret.
@param[in] Command Points to the register Command.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@param[in, out] Index The Index.
@retval EFI_SUCCESS The command completed successfully.
**/
);
/**
Explain the cardbus specific part of data in PCI configuration space.
@param[in] CardBus CardBus specific region of PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
);
/**
Explain each meaningful bit of register Status. The definition of Status is
slightly different depending on the PCI header type.
@param[in] Status Points to the content of register Status.
@param[in] MainStatus Indicates if this register is main status(not secondary
status).
@param[in] HeaderType Header type of this PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
);
/**
Explain each meaningful bit of register Command.
@param[in] Command Points to the content of register Command.
@retval EFI_SUCCESS The command completed successfully.
**/
);
/**
Explain each meaningful bit of register Bridge Control.
@param[in] BridgeControl Points to the content of register Bridge Control.
@param[in] HeaderType The headertype.
@retval EFI_SUCCESS The command completed successfully.
**/
);
/**
Print each capability structure.
@param[in] IoDev The pointer to the deivce.
@param[in] Address The address to start at.
@param[in] CapPtr The offset from the address.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Display Pcie device structure.
@param[in] IoDev The pointer to the root pci protocol.
@param[in] Address The Address to start at.
@param[in] CapabilityPtr The offset from the address to start.
**/
);
/**
Print out information of the capability information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device capability information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device control information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device status information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device link information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device link control information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device link status information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device slot information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device slot control information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device slot status information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device root information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device root capability information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
/**
Print out information of the device root status information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
);
typedef enum {
typedef enum {
typedef struct
{
{
0x00,
NULL,
},
{
0x01,
NULL,
},
{
0x02,
},
{
0x04,
},
{
0x08,
},
{
0x0a,
},
{
0x0c,
},
{
0x10,
},
{
0x12,
},
{
0x14,
},
{
0x18,
},
{
0x1a,
},
{
0x1c,
},
{
0x1e,
},
{
0x20,
},
{
0,
0,
NULL,
}
};
//
// Global Variables
//
{L"-s", TypeValue},
{L"-i", TypeFlag},
};
L"PCI Express Endpoint",
L"Legacy PCI Express Endpoint",
L"Unknown Type",
L"Unknonw Type",
L"Root Port of PCI Express Root Complex",
L"Upstream Port of PCI Express Switch",
L"Downstream Port of PCI Express Switch",
L"Root Complex Integrated Endpoint",
L"Root Complex Event Collector"
};
L"Less than 64ns",
L"64ns to less than 128ns",
L"128ns to less than 256ns",
L"256ns to less than 512ns",
L"512ns to less than 1us",
L"1us to less than 2us",
L"2us-4us",
L"More than 4us"
};
L"Less than 1us",
L"1us to less than 2us",
L"2us to less than 4us",
L"4us to less than 8us",
L"8us to less than 16us",
L"16us to less than 32us",
L"32us-64us",
L"More than 64us"
};
L"Disabled",
L"L0s Entry Enabled",
L"L1 Entry Enabled",
L"L0s and L1 Entry Enabled"
};
L"1.0x",
L"0.1x",
L"0.01x",
L"0.001x"
};
L"Reserved",
L"On",
L"Blink",
L"Off"
};
/**
Function for 'pci' command.
@param[in] ImageHandle Handle to the Image (NULL if Internal).
@param[in] SystemTable Pointer to the System Table (NULL if Internal).
**/
)
{
Address = 0;
Size = 0;
//
// initialize the shell lib (we must be in non-auto-init...)
//
Status = ShellInitialize();
Status = CommandInit();
//
// parse the command line
//
} else {
}
} else {
goto Done;
}
goto Done;
}
goto Done;
}
//
// Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
// call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
// space for handles and call it again.
//
HandleBufSize = sizeof (EFI_HANDLE);
goto Done;
}
NULL,
);
if (Status == EFI_BUFFER_TOO_SMALL) {
goto Done;
}
NULL,
);
}
goto Done;
}
//
// Argument Count == 1(no other argument): enumerate all pci functions
//
);
ScreenCount = 0;
ScreenSize -= 4;
ScreenSize -= 1;
}
PrintTitle = TRUE;
//
// For each handle, which decides a segment and a bus number range,
// enumerate all devices on it.
//
&IoDev,
);
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);
goto Done;
}
//
// No document say it's impossible for a RootBridgeIo protocol handle
// to have more than one address space descriptors, so find out every
// bus range and for each of them do device enumeration.
//
while (TRUE) {
goto Done;
}
if (IsEnd) {
break;
}
//
// For each devices, enumerate all functions it contains
//
//
// For each function, read its configuration space and print summary
//
if (ShellGetExecutionBreakFlag ()) {
goto Done;
}
1,
);
//
// If VendorId = 0xffff, there does not exist a device at this
// location. For each device, if there is any function on it,
// there must be 1 function at Function 0. So if Func = 0, there
// will be no more functions in the same device, so we can break
// loop to deal with the next device.
//
break;
}
if (PrintTitle) {
PrintTitle = FALSE;
}
);
Bus,
);
);
ScreenCount += 2;
//
// If ScreenSize == 0 we have the console redirected so don't
// block updates
//
ScreenCount = 0;
}
//
// If this is not a multi-function device, we can leave the loop
// to deal with the next device.
//
break;
}
}
}
}
}
//
// If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
// we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
// devices on all bus, we can leave loop.
//
if (Descriptors == NULL) {
break;
}
}
}
goto Done;
}
ExplainData = FALSE;
Segment = 0;
Bus = 0;
Device = 0;
Func = 0;
ExplainData = TRUE;
}
}
//
// The first Argument(except "-i") is assumed to be Bus number, second
// to be Device number, and third to be Func number.
//
if (Bus > MAX_BUS_NUMBER) {
goto Done;
}
}
if (Device > MAX_DEVICE_NUMBER){
goto Done;
}
}
if (Func > MAX_FUNCTION_NUMBER){
goto Done;
}
}
//
// Find the protocol interface who's in charge of current segment, and its
// bus range covers the current bus
//
Bus,
);
);
goto Done;
}
sizeof (ConfigSpace),
);
goto Done;
}
-1,
-1,
NULL,
Bus,
Func,
Bus,
);
//
// Dump standard header of configuration space
//
//
// Dump device dependent Part of configuration space
//
DumpHex (
2,
sizeof (ConfigSpace) - SizeOfHeader,
);
//
// If "-i" appears in command line, interpret data in configuration space
//
if (ExplainData) {
}
}
Done:
}
}
mConfigSpace = NULL;
return ShellStatus;
}
/**
This function finds out the protocol which is in charge of the given
segment, and its bus range covers the current bus number. It lookes
each instances of RootBridgeIoProtocol handle, until the one meets the
criteria is found.
@param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
@param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
@param[in] Segment Segment number of device we are dealing with.
@param[in] Bus Bus number of device we are dealing with.
@param[out] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
@retval EFI_INVALID_PARAMETER Invalid parameter.
**/
)
{
//
// Go through all handles, until the one meets the criteria is found
//
return Status;
}
//
// When Descriptors == NULL, the Configuration() is not implemented,
// so we only check the Segment number
//
return EFI_SUCCESS;
}
continue;
}
while (TRUE) {
return Status;
}
if (IsEnd) {
break;
}
break;
}
}
}
if (FoundInterface) {
return EFI_SUCCESS;
} else {
return EFI_INVALID_PARAMETER;
}
}
/**
This function gets the protocol interface from the given handle, and
obtains its address space descriptors.
@param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
@param[out] IoDev Handle used to access configuration space of PCI device.
@param[out] Descriptors Points to the address space descriptors.
@retval EFI_SUCCESS The command completed successfully
**/
)
{
//
// Get inferface from protocol
//
);
return Status;
}
//
// Call Configuration() to get address space descriptors
//
if (Status == EFI_UNSUPPORTED) {
*Descriptors = NULL;
return EFI_SUCCESS;
} else {
return Status;
}
}
/**
This function get the next bus range of given address space descriptors.
It also moves the pointer backward a node, to get prepared to be called
again.
@param[in, out] Descriptors Points to current position of a serial of address space
descriptors.
@param[out] MinBus The lower range of bus number.
@param[out] MaxBus The upper range of bus number.
@param[out] IsEnd Meet end of the serial of descriptors.
@retval EFI_SUCCESS The command completed successfully.
**/
)
{
//
// When *Descriptors is NULL, Configuration() is not implemented, so assume
// range is 0~PCI_MAX_BUS
//
if ((*Descriptors) == NULL) {
*MinBus = 0;
*MaxBus = PCI_MAX_BUS;
return EFI_SUCCESS;
}
//
// *Descriptors points to one or more address space descriptors, which
// ends with a end tagged descriptor. Examine each of the descriptors,
// if a bus typed one is found and its bus range covers bus, this handle
// is the handle we are looking for.
//
(*Descriptors)++;
return (EFI_SUCCESS);
}
(*Descriptors)++;
}
}
return EFI_SUCCESS;
}
/**
Explain the data in PCI configuration space. The part which is common for
PCI device and bridge is interpreted in this function. It calls other
functions to interpret data unique for device or bridge.
@param[in] ConfigSpace Data in PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
)
{
Print (L"\n");
//
// Print Vendor Id and Device Id
//
);
//
// Print register Command
//
//
// Print register Status
//
//
// Print register Revision ID
//
);
//
// Print register BIST
//
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_BIST), gShellDebug1HiiHandle, INDEX_OF (&(Common->Bist)));
ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_LINE_CAP), gShellDebug1HiiHandle, 0x0f & Common->Bist);
} else {
}
//
// Print register Cache Line Size
//
);
//
// Print register Latency Timer
//
);
//
// Print register Header Type
//
);
} else {
}
switch (HeaderType) {
case PciDevice:
break;
case PciP2pBridge:
break;
case PciCardBusBridge:
break;
default:
}
//
// Print register Class Code
//
Print (L"\n");
if (ShellGetExecutionBreakFlag()) {
return EFI_SUCCESS;
}
//
// Interpret remaining part of PCI configuration header depending on
// HeaderType
//
CapPtr = 0;
switch (HeaderType) {
case PciDevice:
);
break;
case PciP2pBridge:
);
break;
case PciCardBusBridge:
);
break;
case PciUndefined:
default:
break;
}
//
// If Status bit4 is 1, dump or explain capability structure
//
}
return Status;
}
/**
Explain the device specific part of data in PCI configuration space.
@param[in] Device Data in PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
)
{
//
// Print Base Address Registers(Bar). When Bar = 0, this Bar does not
// exist. If these no Bar for this function, print "none", otherwise
// list detail information about this Bar.
//
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDR), gShellDebug1HiiHandle, INDEX_OF (Device->Bar));
continue;
}
if (!BarExist) {
Print (L" --------------------------------------------------------------------------");
}
Status = PciExplainBar (
);
break;
}
}
if (!BarExist) {
} else {
Print (L"\n --------------------------------------------------------------------------");
}
//
// Print register Expansion ROM Base Address
//
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED), gShellDebug1HiiHandle, INDEX_OF (&(Device->ROMBar)));
} else {
);
}
//
// Print register Cardbus CIS ptr
//
);
//
// Print register Sub-vendor ID and subsystem ID
//
);
);
//
// Print register Capabilities Ptr
//
);
//
// Print register Interrupt Line and interrupt pin
//
);
);
//
// Print register Min_Gnt and Max_Lat
//
);
);
return EFI_SUCCESS;
}
/**
Explain the bridge specific part of data in PCI configuration space.
@param[in] Bridge Bridge specific data region in PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
)
{
//
// Print Base Address Registers. When Bar = 0, this Bar does not
// exist. If these no Bar for this function, print "none", otherwise
// list detail information about this Bar.
//
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BASE_ADDRESS), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->Bar)));
continue;
}
if (!BarExist) {
Print (L" --------------------------------------------------------------------------");
}
Status = PciExplainBar (
);
break;
}
}
if (!BarExist) {
} else {
Print (L"\n --------------------------------------------------------------------------");
}
//
// Expansion register ROM Base Address
//
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM), gShellDebug1HiiHandle, INDEX_OF (&(Bridge->ROMBar)));
} else {
);
}
//
// Print Bus Numbers(Primary, Secondary, and Subordinate
//
);
Print (L" ------------------------------------------------------\n");
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->PrimaryBus);
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SecondaryBus);
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BRIDGE), gShellDebug1HiiHandle, Bridge->SubordinateBus);
//
// Print register Secondary Latency Timer
//
);
//
// Print register Secondary Status
//
//
// Print I/O and memory ranges this bridge forwards. There are 3 resource
// types: I/O, memory, and pre-fetchable memory. For each resource type,
// base and limit address are listed.
//
Print (L"----------------------------------------------------------------------\n");
//
// IO Base & Limit
//
IoAddress32 &= 0xfffff000;
);
IoAddress32 |= 0x00000fff;
//
// Memory Base & Limit
//
);
);
//
// Pre-fetch-able Memory Base & Limit
//
);
);
//
// Print register Capabilities Pointer
//
);
//
// Print register Bridge Control
//
//
// Print register Interrupt Line & PIN
//
);
);
return EFI_SUCCESS;
}
/**
Explain the Base Address Register(Bar) in PCI configuration space.
@param[in] Bar Points to the Base Address Register intended to interpret.
@param[in] Command Points to the register Command.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@param[in, out] Index The Index.
@retval EFI_SUCCESS The command completed successfully.
**/
)
{
Bar64 = 0;
NewBar32 = 0;
NewBar64 = 0;
//
// According the bar type, list detail about this bar, for example: 32 or
// 64 bits; pre-fetchable or not.
//
//
// This bar is of memory type
//
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
Bar64 = 0x0;
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_2), gShellDebug1HiiHandle, RShiftU64 ((Bar64 & 0xfffffffffffffff0ULL), 32));
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_3), gShellDebug1HiiHandle, (UINT32) (Bar64 & 0xfffffffffffffff0ULL));
*Index += 1;
} else {
//
// Reserved
//
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_BAR), gShellDebug1HiiHandle, *Bar & 0xfffffff0);
}
} else {
}
} else {
//
// This bar is of io type
//
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_ONE_VAR_4), gShellDebug1HiiHandle, *Bar & 0xfffffffc);
Print (L"I/O ");
}
//
// Get BAR length(or the amount of resource this bar demands for). To get
// Bar length, first we should temporarily disable I/O and memory access
// of this function(by set bits in the register Command), then write all
// "1"s to this bar. The bar value read back is the amount of resource
// this bar demands for.
//
//
// Disable io & mem access
//
OldCommand = *Command;
//
// Read after write the BAR to get the size
//
if (IsBar32) {
NewBar32 = 0xffffffff;
if (IsMem) {
} else {
}
} else {
OldBar64 = 0x0;
NewBar64 = 0xffffffffffffffffULL;
if (IsMem) {
} else {
}
}
//
// Enable io & mem access
//
if (IsMem) {
if (IsBar32) {
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_2), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffff0) - 1);
} else {
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, RShiftU64 (NewBar64, 32));
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) NewBar64);
Print (L" ");
);
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_RSHIFT), gShellDebug1HiiHandle, (UINT32) (NewBar64 + (Bar64 & 0xfffffffffffffff0ULL) - 1));
}
} else {
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEWBAR_32_4), gShellDebug1HiiHandle, NewBar32 + (*Bar & 0xfffffffc) - 1);
}
return EFI_SUCCESS;
}
/**
Explain the cardbus specific part of data in PCI configuration space.
@param[in] CardBus CardBus specific region of PCI configuration space.
@param[in] Address Address used to access configuration space of this PCI device.
@param[in] IoDev Handle used to access configuration space of PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
)
{
);
//
// Print Secondary Status
//
//
// Print Bus Numbers(Primary bus number, CardBus bus number, and
// Subordinate bus number
//
);
Print (L" ------------------------------------------------------\n");
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS), gShellDebug1HiiHandle, CardBus->PciBusNumber);
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_2), gShellDebug1HiiHandle, CardBus->CardBusBusNumber);
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_CARDBUS_3), gShellDebug1HiiHandle, CardBus->SubordinateBusNumber);
//
// Print CardBus Latency Timer
//
);
//
//
Print (L"----------------------------------------------------------------------\n");
);
);
);
);
//
// Print register Interrupt Line & PIN
//
);
//
// Print register Bridge Control
//
//
// Print some registers in data region of PCI configuration space for cardbus
// bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
// Address.
//
);
);
return EFI_SUCCESS;
}
/**
Explain each meaningful bit of register Status. The definition of Status is
slightly different depending on the PCI header type.
@param[in] Status Points to the content of register Status.
@param[in] MainStatus Indicates if this register is main status(not secondary
status).
@param[in] HeaderType Header type of this PCI device.
@retval EFI_SUCCESS The command completed successfully.
**/
)
{
if (MainStatus) {
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
} else {
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS), gShellDebug1HiiHandle, INDEX_OF (Status), *Status);
}
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES), gShellDebug1HiiHandle, (*Status & PCI_BIT_4) != 0);
//
// Bit 5 is meaningless for CardBus Bridge
//
if (HeaderType == PciCardBusBridge) {
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);
} else {
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_66_CAPABLE_2), gShellDebug1HiiHandle, (*Status & PCI_BIT_5) != 0);
}
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_FAST_BACK), gShellDebug1HiiHandle, (*Status & PCI_BIT_7) != 0);
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_MASTER_DATA), gShellDebug1HiiHandle, (*Status & PCI_BIT_8) != 0);
//
// Bit 9 and bit 10 together decides the DEVSEL timing
//
} else {
}
(*Status & PCI_BIT_11) != 0
);
(*Status & PCI_BIT_12) != 0
);
(*Status & PCI_BIT_13) != 0
);
if (MainStatus) {
(*Status & PCI_BIT_14) != 0
);
} else {
(*Status & PCI_BIT_14) != 0
);
}
(*Status & PCI_BIT_15) != 0
);
return EFI_SUCCESS;
}
/**
Explain each meaningful bit of register Command.
@param[in] Command Points to the content of register Command.
@retval EFI_SUCCESS The command completed successfully.
**/
)
{
//
// Print the binary value of register Command
//
ShellPrintHiiEx(-1, -1, NULL,STRING_TOKEN (STR_PCI2_COMMAND), gShellDebug1HiiHandle, INDEX_OF (Command), *Command);
//
// Explain register Command bit by bit
//
);
);
);
);
);
);
);
);
);
);
return EFI_SUCCESS;
}
/**
Explain each meaningful bit of register Bridge Control.
@param[in] BridgeControl Points to the content of register Bridge Control.
@param[in] HeaderType The headertype.
@retval EFI_SUCCESS The command completed successfully.
**/
)
{
);
(*BridgeControl & PCI_BIT_0) != 0
);
(*BridgeControl & PCI_BIT_1) != 0
);
(*BridgeControl & PCI_BIT_2) != 0
);
(*BridgeControl & PCI_BIT_3) != 0
);
(*BridgeControl & PCI_BIT_5) != 0
);
//
// Register Bridge Control has some slight differences between P2P bridge
// and Cardbus bridge from bit 6 to bit 11.
//
if (HeaderType == PciP2pBridge) {
(*BridgeControl & PCI_BIT_6) != 0
);
(*BridgeControl & PCI_BIT_7) != 0
);
);
);
(*BridgeControl & PCI_BIT_10) != 0
);
(*BridgeControl & PCI_BIT_11) != 0
);
} else {
(*BridgeControl & PCI_BIT_6) != 0
);
(*BridgeControl & PCI_BIT_7) != 0
);
(*BridgeControl & PCI_BIT_10) != 0
);
}
return EFI_SUCCESS;
}
/**
Print each capability structure.
@param[in] IoDev The pointer to the deivce.
@param[in] Address The address to start at.
@param[in] CapPtr The offset from the address.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
//
// Go through the Capability list
//
//
// Explain PciExpress data
//
if (EFI_PCI_CAPABILITY_ID_PCIEXP == CapabilityID) {
return EFI_SUCCESS;
}
//
// Explain other capabilities here
//
}
return EFI_SUCCESS;
}
/**
Print out information of the capability information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" Capability Version(3:0): %E0x%04x%N\n",
);
} else {
DevicePortType = L"Unknown Type";
}
Print (
);
//
// 'Slot Implemented' is only valid for:
// a) Root Port of PCI Express Root Complex, or
// b) Downstream Port of PCI Express Switch
//
Print (
L" Slot Implemented(8): %E%d%N\n",
);
}
Print (
L" Interrupt Message Number(13:9): %E0x%05x%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device capability information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (L" Max_Payload_Size Supported(2:0): ");
} else {
Print (L"%EUnknown%N\n");
}
Print (
L" Phantom Functions Supported(4:3): %E%d%N\n",
);
Print (
L" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",
);
//
// Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
//
if (IS_PCIE_ENDPOINT (DevicePortType)) {
Print (L" Endpoint L0s Acceptable Latency(8:6): ");
if (L0sLatency < 4) {
} else {
if (L0sLatency < 7) {
} else {
Print (L"%ENo limit%N\n");
}
}
Print (L" Endpoint L1 Acceptable Latency(11:9): ");
if (L1Latency < 7) {
} else {
Print (L"%ENo limit%N\n");
}
}
Print (
L" Role-based Error Reporting(15): %E%d%N\n",
);
//
// Only valid for Upstream Port:
// a) Captured Slot Power Limit Value
// b) Captured Slot Power Scale
//
if (DevicePortType == PCIE_SWITCH_UPSTREAM_PORT) {
Print (
L" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",
);
Print (
L" Captured Slot Power Limit Scale(27:26): %E%s%N\n",
);
}
//
// Function Level Reset Capability is only valid for Endpoint
//
if (IS_PCIE_ENDPOINT (DevicePortType)) {
Print (
L" Function Level Reset Capability(28): %E%d%N\n",
);
}
return EFI_SUCCESS;
}
/**
Print out information of the device control information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" Correctable Error Reporting Enable(0): %E%d%N\n",
);
Print (
L" Non-Fatal Error Reporting Enable(1): %E%d%N\n",
);
Print (
L" Fatal Error Reporting Enable(2): %E%d%N\n",
);
Print (
L" Unsupported Request Reporting Enable(3): %E%d%N\n",
);
Print (
L" Enable Relaxed Ordering(4): %E%d%N\n",
);
Print (L" Max_Payload_Size(7:5): ");
} else {
Print (L"%EUnknown%N\n");
}
Print (
L" Extended Tag Field Enable(8): %E%d%N\n",
);
Print (
L" Phantom Functions Enable(9): %E%d%N\n",
);
Print (
L" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",
);
Print (
L" Enable No Snoop(11): %E%d%N\n",
);
Print (L" Max_Read_Request_Size(14:12): ");
} else {
Print (L"%EUnknown%N\n");
}
//
//
Print (
L" Bridge Configuration Retry Enable(15): %E%d%N\n",
);
}
return EFI_SUCCESS;
}
/**
Print out information of the device status information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" Correctable Error Detected(0): %E%d%N\n",
);
Print (
L" Non-Fatal Error Detected(1): %E%d%N\n",
);
Print (
L" Fatal Error Detected(2): %E%d%N\n",
);
Print (
L" Unsupported Request Detected(3): %E%d%N\n",
);
Print (
L" AUX Power Detected(4): %E%d%N\n",
);
Print (
L" Transactions Pending(5): %E%d%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device link information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) {
case 1:
SupLinkSpeeds = L"2.5 GT/s";
break;
case 2:
SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s";
break;
default:
SupLinkSpeeds = L"Unknown";
break;
}
Print (
L" Supported Link Speeds(3:0): %E%s supported%N\n",
);
Print (
L" Maximum Link Width(9:4): %Ex%d%N\n",
);
switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {
case 1:
AspmValue = L"L0s Entry";
break;
case 3:
AspmValue = L"L0s and L1";
break;
default:
AspmValue = L"Reserved";
break;
}
Print (
L" Active State Power Management Support(11:10): %E%s Supported%N\n",
);
Print (
L" L0s Exit Latency(14:12): %E%s%N\n",
);
Print (
L" L1 Exit Latency(17:15): %E%s%N\n",
);
Print (
L" Clock Power Management(18): %E%d%N\n",
);
Print (
L" Surprise Down Error Reporting Capable(19): %E%d%N\n",
);
Print (
L" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",
);
Print (
L" Link Bandwidth Notification Capability(21): %E%d%N\n",
);
Print (
L" Port Number(31:24): %E0x%02x%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device link control information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" Active State Power Management Control(1:0): %E%s%N\n",
);
//
// RCB is not applicable to switches
//
if (!IS_PCIE_SWITCH(DevicePortType)) {
Print (
L" Read Completion Boundary (RCB)(3): %E%d byte%N\n",
);
}
//
// Link Disable is reserved on
// a) Endpoints
// c) Upstream Ports of Switches
//
if (!IS_PCIE_ENDPOINT (DevicePortType) &&
Print (
L" Link Disable(4): %E%d%N\n",
);
}
Print (
L" Common Clock Configuration(6): %E%d%N\n",
);
Print (
L" Extended Synch(7): %E%d%N\n",
);
Print (
L" Enable Clock Power Management(8): %E%d%N\n",
);
Print (
L" Hardware Autonomous Width Disable(9): %E%d%N\n",
);
Print (
L" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",
);
Print (
L" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device link status information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {
case 1:
SupLinkSpeeds = L"2.5 GT/s";
break;
case 2:
SupLinkSpeeds = L"5.0 GT/s";
break;
default:
SupLinkSpeeds = L"Reserved";
break;
}
Print (
L" Current Link Speed(3:0): %E%s%N\n",
);
Print (
L" Negotiated Link Width(9:4): %Ex%d%N\n",
);
Print (
L" Link Training(11): %E%d%N\n",
);
Print (
L" Slot Clock Configuration(12): %E%d%N\n",
);
Print (
L" Data Link Layer Link Active(13): %E%d%N\n",
);
Print (
L" Link Bandwidth Management Status(14): %E%d%N\n",
);
Print (
L" Link Autonomous Bandwidth Status(15): %E%d%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device slot information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" Attention Button Present(0): %E%d%N\n",
);
Print (
L" Power Controller Present(1): %E%d%N\n",
);
Print (
L" MRL Sensor Present(2): %E%d%N\n",
);
Print (
L" Attention Indicator Present(3): %E%d%N\n",
);
Print (
L" Power Indicator Present(4): %E%d%N\n",
);
Print (
L" Hot-Plug Surprise(5): %E%d%N\n",
);
Print (
L" Hot-Plug Capable(6): %E%d%N\n",
);
Print (
L" Slot Power Limit Value(14:7): %E0x%02x%N\n",
);
Print (
L" Slot Power Limit Scale(16:15): %E%s%N\n",
);
Print (
L" Electromechanical Interlock Present(17): %E%d%N\n",
);
Print (
L" No Command Completed Support(18): %E%d%N\n",
);
Print (
L" Physical Slot Number(31:19): %E%d%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device slot control information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" Attention Button Pressed Enable(0): %E%d%N\n",
);
Print (
L" Power Fault Detected Enable(1): %E%d%N\n",
);
Print (
L" MRL Sensor Changed Enable(2): %E%d%N\n",
);
Print (
L" Presence Detect Changed Enable(3): %E%d%N\n",
);
Print (
L" Command Completed Interrupt Enable(4): %E%d%N\n",
);
Print (
L" Hot-Plug Interrupt Enable(5): %E%d%N\n",
);
Print (
L" Attention Indicator Control(7:6): %E%s%N\n",
);
Print (
L" Power Indicator Control(9:8): %E%s%N\n",
);
Print (L" Power Controller Control(10): %EPower ");
if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl)) {
Print (L"Off%N\n");
} else {
Print (L"On%N\n");
}
Print (
L" Electromechanical Interlock Control(11): %E%d%N\n",
);
Print (
L" Data Link Layer State Changed Enable(12): %E%d%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device slot status information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" Attention Button Pressed(0): %E%d%N\n",
);
Print (
L" Power Fault Detected(1): %E%d%N\n",
);
Print (
L" MRL Sensor Changed(2): %E%d%N\n",
);
Print (
L" Presence Detect Changed(3): %E%d%N\n",
);
Print (
L" Command Completed(4): %E%d%N\n",
);
Print (L" MRL Sensor State(5): %EMRL ");
if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus)) {
Print (L" Opened%N\n");
} else {
Print (L" Closed%N\n");
}
Print (L" Presence Detect State(6): ");
if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus)) {
Print (L"%ECard Present in slot%N\n");
} else {
Print (L"%ESlot Empty%N\n");
}
Print (L" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
Print (L"Engaged%N\n");
} else {
Print (L"Disengaged%N\n");
}
Print (
L" Data Link Layer State Changed(8): %E%d%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device root information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" System Error on Correctable Error Enable(0): %E%d%N\n",
);
Print (
L" System Error on Non-Fatal Error Enable(1): %E%d%N\n",
);
Print (
L" System Error on Fatal Error Enable(2): %E%d%N\n",
);
Print (
L" PME Interrupt Enable(3): %E%d%N\n",
);
Print (
L" CRS Software Visibility Enable(4): %E%d%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device root capability information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" CRS Software Visibility(0): %E%d%N\n",
);
return EFI_SUCCESS;
}
/**
Print out information of the device root status information.
@param[in] PciExpressCap The pointer to the structure about the device.
@retval EFI_SUCCESS The operation was successful.
**/
)
{
Print (
L" PME Requester ID(15:0): %E0x%04x%N\n",
);
Print (
L" PME Status(16): %E%d%N\n",
);
Print (
L" PME Pending(17): %E%d%N\n",
);
return EFI_SUCCESS;
}
/**
Display Pcie device structure.
@param[in] IoDev The pointer to the root pci protocol.
@param[in] Address The Address to start at.
@param[in] CapabilityPtr The offset from the address to start.
**/
)
{
sizeof (PciExpressCap) / sizeof (UINT32),
);
Print (L"\nPci Express device capability structure:\n");
if (ShellGetExecutionBreakFlag()) {
goto Done;
}
case FieldWidthUINT8:
break;
case FieldWidthUINT16:
break;
case FieldWidthUINT32:
break;
default:
RegValue = 0;
break;
}
);
continue;
}
case PcieExplainTypeLink:
//
// Link registers should not be used by
// a) Root Complex Integrated Endpoint
// b) Root Complex Event Collector
//
continue;
}
break;
case PcieExplainTypeSlot:
//
// Slot registers are only valid for
// a) Root Port of PCI Express Root Complex
// b) Downstream Port of PCI Express Switch
// and when SlotImplemented bit is set in PCIE cap register.
//
if ((DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT &&
continue;
}
break;
case PcieExplainTypeRoot:
//
// Root registers are only valid for
// Root Port of PCI Express Root Complex
//
if (DevicePortType != PCIE_ROOT_COMPLEX_ROOT_PORT) {
continue;
}
break;
default:
break;
}
}
//
// PciRootBridgeIo protocol should support pci express extend space IO
// (Begins at offset 0x100)
//
(ExtendRegSize) / sizeof (UINT32),
(VOID *) (ExRegBuffer)
);
return EFI_UNSUPPORTED;
}
//
// Start outputing PciEx extend space( 0xFF-0xFFF)
//
Print (L"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");
if (ExRegBuffer != NULL) {
DumpHex (
2,
0x100,
(VOID *) (ExRegBuffer)
);
}
Done:
return EFI_SUCCESS;
}