/** @file
This contains the installation function for the driver.
Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "8259.h"
//
// Global for the Legacy 8259 Protocol that is produced by this driver
//
};
//
// Global for the handle that the Legacy 8259 Protocol is installed
//
//
// Worker Functions
//
/**
@param[in] Mask low byte for master PIC mask register,
high byte for slave PIC mask register.
**/
)
{
}
/**
@param[out] Mask low byte for master PIC mask register,
high byte for slave PIC mask register.
**/
)
{
}
}
}
//
// Legacy 8259 Protocol Interface Functions
//
/**
Sets the base address for the 8259 master and slave PICs.
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
@param[in] MasterBase Interrupt vectors for IRQ0-IRQ7.
@param[in] SlaveBase Interrupt vectors for IRQ8-IRQ15.
@retval EFI_SUCCESS The 8259 PIC was programmed successfully.
@retval EFI_DEVICE_ERROR There was an error while writing to the 8259 PIC.
**/
)
{
//
// Set vector base for slave PIC
//
if (SlaveBase != mSlaveBase) {
//
// Initialization sequence is needed for setting vector base.
//
//
// Preserve interrtup mask register before initialization sequence
// because it will be cleared during intialization
//
//
// ICW1: cascade mode, ICW4 write required
//
//
// ICW2: new vector base (must be multiple of 8)
//
//
// ICW3: slave indentification code must be 2
//
//
// ICW4: fully nested mode, non-buffered mode, normal EOI, IA processor
//
//
// Restore interrupt mask register
//
}
//
// Set vector base for master PIC
//
if (MasterBase != mMasterBase) {
//
// Initialization sequence is needed for setting vector base.
//
//
// Preserve interrtup mask register before initialization sequence
// because it will be cleared during intialization
//
//
// ICW1: cascade mode, ICW4 write required
//
//
// ICW2: new vector base (must be multiple of 8)
//
//
// ICW3: slave PIC is cascaded on IRQ2
//
//
// ICW4: fully nested mode, non-buffered mode, normal EOI, IA processor
//
//
// Restore interrupt mask register
//
}
return EFI_SUCCESS;
}
/**
Gets the current 16-bit real mode and 32-bit protected-mode IRQ masks.
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
@param[out] LegacyMask 16-bit mode interrupt mask for IRQ0-IRQ15.
@param[out] ProtectedMask 32-bit mode interrupt mask for IRQ0-IRQ15.
@retval EFI_SUCCESS The 8259 PIC was programmed successfully.
@retval EFI_DEVICE_ERROR There was an error while reading the 8259 PIC.
**/
)
{
if (LegacyMask != NULL) {
}
if (LegacyEdgeLevel != NULL) {
}
if (ProtectedMask != NULL) {
}
if (ProtectedEdgeLevel != NULL) {
}
return EFI_SUCCESS;
}
/**
Sets the current 16-bit real mode and 32-bit protected-mode IRQ masks.
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
@param[in] LegacyMask 16-bit mode interrupt mask for IRQ0-IRQ15.
@param[in] ProtectedMask 32-bit mode interrupt mask for IRQ0-IRQ15.
@retval EFI_SUCCESS The 8259 PIC was programmed successfully.
@retval EFI_DEVICE_ERROR There was an error while writing the 8259 PIC.
**/
)
{
if (LegacyMask != NULL) {
}
if (LegacyEdgeLevel != NULL) {
}
if (ProtectedMask != NULL) {
}
if (ProtectedEdgeLevel != NULL) {
}
return EFI_SUCCESS;
}
/**
Sets the mode of the PICs.
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
@param[in] Mode 16-bit real or 32-bit protected mode.
@param[in] Mask The value with which to set the interrupt mask.
@retval EFI_SUCCESS The mode was set successfully.
@retval EFI_INVALID_PARAMETER The mode was not set.
**/
)
{
return EFI_SUCCESS;
}
if (Mode == Efi8259LegacyMode) {
//
// be changed through this protocol, so we can track them in the
// corresponding module variables.
//
//
// Update the Mask for the new mode
//
mLegacyModeMask = *Mask;
}
//
//
}
//
//
return EFI_SUCCESS;
}
if (Mode == Efi8259ProtectedMode) {
//
//
//
// Always force Timer to be enabled after return from 16-bit code.
// This always insures that on next entry, timer is counting.
//
mLegacyModeMask &= 0xFFFE;
//
// Update the Mask for the new mode
//
}
//
//
}
//
//
return EFI_SUCCESS;
}
return EFI_INVALID_PARAMETER;
}
/**
Translates the IRQ into a vector.
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
@param[in] Irq IRQ0-IRQ15.
@param[out] Vector The vector that is assigned to the IRQ.
@retval EFI_SUCCESS The Vector that matches Irq was returned.
@retval EFI_INVALID_PARAMETER Irq is not valid.
**/
)
{
return EFI_INVALID_PARAMETER;
}
if (Irq <= Efi8259Irq7) {
} else {
}
return EFI_SUCCESS;
}
/**
Enables the specified IRQ.
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
@param[in] Irq IRQ0-IRQ15.
@param[in] LevelTriggered 0 = Edge triggered; 1 = Level triggered.
@retval EFI_SUCCESS The Irq was enabled on the 8259 PIC.
@retval EFI_INVALID_PARAMETER The Irq is not valid.
**/
)
{
return EFI_INVALID_PARAMETER;
}
if (LevelTriggered) {
} else {
}
return EFI_SUCCESS;
}
/**
Disables the specified IRQ.
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
@param[in] Irq IRQ0-IRQ15.
@retval EFI_SUCCESS The Irq was disabled on the 8259 PIC.
@retval EFI_INVALID_PARAMETER The Irq is not valid.
**/
)
{
return EFI_INVALID_PARAMETER;
}
return EFI_SUCCESS;
}
/**
Reads the PCI configuration space to get the interrupt number that is assigned to the card.
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
@param[in] PciHandle PCI function for which to return the vector.
@param[out] Vector IRQ number that corresponds to the interrupt line.
@retval EFI_SUCCESS The interrupt line value was read successfully.
**/
)
{
);
return EFI_INVALID_PARAMETER;
}
1,
);
//
// Interrupt line is same location for standard PCI cards, standard
// bridge and CardBus bridge.
//
*Vector = InterruptLine;
return EFI_SUCCESS;
}
/**
Issues the End of Interrupt (EOI) commands to PICs.
@param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.
@param[in] Irq The interrupt for which to issue the EOI command.
@retval EFI_SUCCESS The EOI command was issued.
@retval EFI_INVALID_PARAMETER The Irq is not valid.
**/
)
{
return EFI_INVALID_PARAMETER;
}
if (Irq >= Efi8259Irq8) {
}
return EFI_SUCCESS;
}
/**
Driver Entry point.
@param[in] ImageHandle ImageHandle of the loaded driver.
@param[in] SystemTable Pointer to the EFI System Table.
@retval EFI_SUCCESS One or more of the drivers returned a success code.
@retval !EFI_SUCCESS Error installing Legacy 8259 Protocol.
**/
)
{
//
// Initialze mask values from PCDs
//
//
// Clear all pending interrupt
//
}
//
// Set the 8259 Master base to 0x68 and the 8259 Slave base to 0x70
//
Status = Interrupt8259SetVectorBase (&mInterrupt8259, PROTECTED_MODE_BASE_VECTOR_MASTER, PROTECTED_MODE_BASE_VECTOR_SLAVE);
//
// Set all 8259 interrupts to edge triggered and disabled
//
//
// Install 8259 Protocol onto a new handle
//
);
return Status;
}