/** @file
The definition for UHCI register operation routines.
Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _EFI_UHCI_REG_H_
#define _EFI_UHCI_REG_H_
//
// UHCI register offset
//
//
// Register offset and PCI related staff
//
#define USBCMD_OFFSET 0
//
// Packet IDs
//
//
// USB port status and control bit definition.
//
//
// UHCI Spec said it must implement 2 ports each host at least,
// and if more, check whether the bit7 of PORTSC is always 1.
// So here assume the max of port number each host is 16.
//
//
// Command register bit definitions
//
//
// USB Status register bit definitions
//
/**
Read a UHCI register.
@param PciIo The EFI_PCI_IO_PROTOCOL to use.
@param Offset Register offset to USB_BAR_INDEX.
@return Content of register.
**/
);
/**
Write data to UHCI register.
@param PciIo The EFI_PCI_IO_PROTOCOL to use.
@param Offset Register offset to USB_BAR_INDEX.
@param Data Data to write.
@return None.
**/
);
/**
Set a bit of the UHCI Register.
@param PciIo The EFI_PCI_IO_PROTOCOL to use.
@param Offset Register offset to USB_BAR_INDEX.
@param Bit The bit to set.
@return None.
**/
);
/**
Clear a bit of the UHCI Register.
@param PciIo The PCI_IO protocol to access the PCI.
@param Offset Register offset to USB_BAR_INDEX.
@param Bit The bit to clear.
@return None.
**/
);
/**
Clear all the interrutp status bits, these bits
are Write-Clean.
@param Uhc The UHCI device.
@return None.
**/
);
/**
Stop the host controller.
@param Uhc The UHCI device.
@param Timeout Max time allowed.
@retval EFI_SUCCESS The host controller is stopped.
@retval EFI_TIMEOUT Failed to stop the host controller.
**/
);
/**
Check whether the host controller operates well.
@param PciIo The PCI_IO protocol to use.
@retval TRUE Host controller is working.
@retval FALSE Host controller is halted or system error.
**/
);
/**
Set the UHCI frame list base address. It can't use
UhciWriteReg which access memory in UINT16.
@param PciIo The EFI_PCI_IO_PROTOCOL to use.
@param Addr Address to set.
@return None.
**/
);
/**
Disable USB Emulation.
@param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.
@return None.
**/
);
#endif