/** @file
Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "LegacyBiosInterface.h"
#include <IndustryStandard/Pci30.h>
typedef struct {
} BRIDGE_TABLE;
/**
Query shadowed legacy ROM parameters registered by RomShadow() previously.
@param PciHandle PCI device whos ROM has been shadowed
@param DiskStart DiskStart value from EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
@param DiskEnd DiskEnd value from EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
@param RomShadowAddress Address where ROM was shadowed
@param ShadowedSize Runtime size of ROM
@retval EFI_SUCCESS Query Logging successful.
@retval EFI_NOT_FOUND No logged data found about PciHandle.
**/
)
{
//
// Get the PCI I/O Protocol on PciHandle
//
);
return Status;
}
//
// Get the location of the PCI device
//
PciIo->GetLocation (
&PciBus,
);
break;
}
}
return EFI_NOT_FOUND;
}
}
}
if (RomShadowAddress != NULL) {
}
if (ShadowedSize != NULL) {
}
return EFI_SUCCESS;
}
/**
Every legacy ROM that is shadowed by the Legacy BIOS driver will be
registered into this API so that the policy code can know what has
happend
@param PciHandle PCI device whos ROM is being shadowed
@param ShadowAddress Address that ROM was shadowed
@param ShadowedSize Runtime size of ROM
@param DiskStart DiskStart value from
EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
@param DiskEnd DiskEnd value from
EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
@retval EFI_SUCCESS Logging successful.
@retval EFI_OUT_OF_RESOURCES No remaining room for registering another option
ROM.
**/
)
{
//
// See if there is room to register another option ROM
//
if (mRomCount >= ROM_MAX_ENTRIES) {
return EFI_OUT_OF_RESOURCES;
}
//
// Get the PCI I/O Protocol on PciHandle
//
);
return Status;
}
//
// Get the location of the PCI device
//
PciIo->GetLocation (
);
mRomCount++;
return EFI_SUCCESS;
}
/**
Return EFI_SUCCESS if PciHandle has had a legacy BIOS ROM shadowed. This
information represents every call to RomShadow ()
@param PciHandle PCI device to get status for
@retval EFI_SUCCESS Legacy ROM loaded for this device
@retval EFI_NOT_FOUND No Legacy ROM loaded for this device
**/
)
{
//
// Get the PCI I/O Protocol on PciHandle
//
);
return Status;
}
//
// Get the location of the PCI device
//
PciIo->GetLocation (
&Segment,
&Bus,
&Device,
);
//
// See if the option ROM from PciHandle has been previously posted
//
) {
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
}
/**
Find the PC-AT ROM Image in the raw PCI Option ROM. Also return the
related information from the header.
@param Csm16Revision The PCI interface version of underlying CSM16
@param VendorId Vendor ID of the PCI device
@param DeviceId Device ID of the PCI device
@param Rom On input pointing to beginning of the raw PCI OpROM
On output pointing to the first legacy PCI OpROM
@param ImageSize On input is the size of Raw PCI Rom
On output is the size of the first legacy PCI ROM
@param MaxRuntimeImageLength The max runtime image length only valid if OpRomRevision >= 3
@param OpRomRevision Revision of the PCI Rom
@param ConfigUtilityCodeHeader Pointer to Configuration Utility Code Header
@retval EFI_SUCCESS Successfully find the legacy PCI ROM
@retval EFI_NOT_FOUND Failed to find the legacy PCI ROM
**/
)
{
if (*ImageSize < sizeof (EFI_PCI_ROM_HEADER)) {
return EFI_NOT_FOUND;
}
BackupImage = NULL;
*ImageSize < RomHeader.Raw - (UINT8 *) *Rom + RomHeader.Generic->PcirOffset + sizeof (PCI_DATA_STRUCTURE)) {
break;
}
//
// Check signature in the PCI Data Structure.
//
break;
}
break;
}
//
// Checking the device list
//
while (*DeviceIdList != 0) {
if (*DeviceIdList == DeviceId) {
break;
}
DeviceIdList ++;
}
}
}
if (Match) {
if (Csm16Revision >= 0x0300) {
//
// Case 1: CSM16 3.0
//
//
// case 1.1: meets OpRom 3.0
// Perfect!!!
//
break;
} else {
//
// case 1.2: meets OpRom 2.x
// Store it and try to find the OpRom 3.0
//
}
} else {
//
// Case 2: CSM16 2.x
//
//
// case 2.1: meets OpRom 3.0
// Store it and try to find the OpRom 2.x
//
} else {
//
// case 2.2: meets OpRom 2.x
// Perfect!!!
//
break;
}
}
} else {
DEBUG ((EFI_D_ERROR, "GetPciLegacyRom - OpRom not match (%04x-%04x)\n", (UINTN)VendorId, (UINTN)DeviceId));
}
}
break;
} else {
}
}
if (BackupImage == NULL) {
return EFI_NOT_FOUND;
}
//
// The versions of CSM16 and OpRom don't match exactly
//
}
if (MaxRuntimeImageLength != NULL) {
*MaxRuntimeImageLength = 0;
} else {
}
}
if (OpRomRevision != NULL) {
//
// Optional return PCI Data Structure revision
//
} else {
*OpRomRevision = 0;
}
}
if (ConfigUtilityCodeHeader != NULL) {
//
// Optional return ConfigUtilityCodeHeaderOffset supported by the PC-AT ROM
//
} else {
}
}
return EFI_SUCCESS;
}
/**
Build a table of bridge info for PIRQ translation.
@param RoutingTable RoutingTable obtained from Platform.
@param RoutingTableEntries Number of RoutingTable entries.
@retval EFI_SUCCESS New Subordinate bus.
@retval EFI_NOT_FOUND No more Subordinate busses.
**/
)
{
BridgeIndex = 0x00;
SlotBridgeIndex = 0x00;
//
// Assumption is table is built from low bus to high bus numbers.
//
NULL,
);
return EFI_NOT_FOUND;
}
);
continue;
}
0,
sizeof (PciConfigHeader) / sizeof (UINT32),
);
PciIo->GetLocation (
);
//
// Test whether we have found the Bridge in the slot, must be the one that directly interfaced to the board
// Once we find one, store it in the SlotBridges[]
//
if ((RoutingTable[Index1].Slot != 0) && (Bridges[BridgeIndex].PrimaryBus == RoutingTable[Index1].Bus)
break;
}
}
++BridgeIndex;
}
}
//
// Pack up Bridges by removing those useless ones
//
if (((Bridges[Index].PciBus == SlotBridges[Index1].PrimaryBus) && (Bridges[Index].PciDevice == SlotBridges[Index1].PciDevice)) ||
((Bridges[Index].PciBus >= SlotBridges[Index1].SecondaryBus) && (Bridges[Index].PciBus <= SlotBridges[Index1].SubordinateBus))) {
//
// We have found one that meets our criteria
//
Index++;
break;
}
}
//
// This one doesn't meet criteria, pack it
//
if (Index1 >= SlotBridgeIndex) {
}
BridgeIndex--;
}
}
//
// Sort bridges low to high by Secondary bus followed by subordinate bus
//
if (NumberOfBridges > 1) {
Index = 0;
do {
++Index;
} while (Index < NumberOfBridges);
}
) {
}
}
}
}
return EFI_SUCCESS;
}
/**
Find base Bridge for device.
@param Private Legacy BIOS Instance data
@param PciBus Input = Bus of device.
@param PciDevice Input = Device.
@param RoutingTable The platform specific routing table
@param RoutingTableEntries Number of entries in table
@retval EFI_SUCCESS At base bus.
@retval EFI_NOT_FOUND Behind a bridge.
**/
)
{
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
}
/**
Translate PIRQ through busses
@param Private Legacy BIOS Instance data
@param PciBus Input = Bus of device. Output = Translated Bus
@param PciDevice Input = Device. Output = Translated Device
@param PciFunction Input = Function. Output = Translated Function
@param PirqIndex Input = Original PIRQ index. If single function
device then 0, otherwise 0-3.
Output = Translated Index
@retval EFI_SUCCESS Pirq successfully translated.
@retval EFI_NOT_FOUND The device is not behind any known bridge.
**/
)
{
/*
This routine traverses the PCI busses from base slot
and translates the PIRQ register to the appropriate one.
Example:
Bus 0, Device 1 is PCI-PCI bridge that all PCI slots reside on.
Primary bus# = 0
Secondary bus # = 1
Subordinate bus # is highest bus # behind this bus
Bus 1, Device 0 is Slot 0 and is not a bridge.
Bus 1, Device 1 is Slot 1 and is a bridge.
Slot PIRQ routing is A,B,C,D.
Primary bus # = 1
Secondary bus # = 2
Subordinate bus # = 5
Bus 2, Device 6 is a bridge. It has no bridges behind it.
Primary bus # = 2
Secondary bus # = 3
Subordinate bus # = 3
Bridge PIRQ routing is C,D,A,B
Bus 2, Device 7 is a bridge. It has 1 bridge behind it.
Primary bus # = 2
Secondary bus = 4 Device 6 takes bus 2.
Subordinate bus = 5.
Bridge PIRQ routing is D,A,B,C
Bus 4, Device 2 is a bridge. It has no bridges behind it.
Primary bus # = 4
Secondary bus # = 5
Subordinate bus = 5
Bridge PIRQ routing is B,C,D,A
Bus 5, Device 1 is to be programmed.
Device PIRQ routing is C,D,A,B
Search busses starting from slot bus for final bus >= Secondary bus and
final bus <= Suborninate bus. Assumption is bus entries increase in bus
number.
Starting PIRQ is A,B,C,D.
Bus 2, Device 7 satisfies search criteria. Rotate (A,B,C,D) left by device
7 modulo 4 giving (D,A,B,C).
Bus 4, Device 2 satisfies search criteria. Rotate (D,A,B,C) left by 2 giving
(B,C,D,A).
No other busses match criteria. Device to be programmed is Bus 5, Device 1.
Rotate (B,C,D,A) by 1 giving C,D,A,B. Translated PIRQ is C.
*/
BridgeIndex = 0x00;
LocalDevice = *PciDevice;
BaseDevice = *PciDevice;
//
// LocalPirqIndex list PIRQs in rotated fashion
// = 0 A,B,C,D
// = 1 B,C,D,A
// = 2 C,D,A,B
// = 3 D,A,B,C
//
//
// Check if device behind this bridge
//
if ((LocalBus >= Bridges[SBridgeIndex].SecondaryBus) && (LocalBus <= Bridges[SBridgeIndex].SubordinateBus)) {
//
// If BaseIndexFlag = FALSE then have found base bridge, i.e
// bridge in slot. Save info for use by IRQ routing table.
//
if (!BaseIndexFlag) {
} else {
}
//
// Check if at device. If not get new PCI location & PIRQ
//
//
// Translate PIRQ
//
break;
}
}
}
//
// In case we fail to find the Bridge just above us, this is some potential error and we want to warn the user
//
if(BridgeIndex >= NumberOfBridges){
DEBUG ((EFI_D_ERROR, "Cannot Find IRQ Routing for Bus %d, Device %d, Function %d\n", *PciBus, *PciDevice, *PciFunction));
}
*PciDevice = BaseDevice;
return EFI_SUCCESS;
}
/**
Copy the $PIR table as required.
@param Private Legacy BIOS Instance data
@param RoutingTable Pointer to IRQ routing table
@param RoutingTableEntries IRQ routing table entries
@param PirqTable Pointer to $PIR table
@param PirqTableSize Length of table
**/
)
{
//
// Copy $PIR table, if it exists.
//
0xE0000,
0x20000,
);
//
// Allocate at F segment according to PCI IRQ Routing Table Specification
//
//
// 16-byte boundary alignment requirement according to
// PCI IRQ Routing Table Specification
//
&Regs,
NULL,
0
);
} else {
DEBUG ((EFI_D_INFO, "PIRQ table in legacy region - %x\n", Private->Legacy16Table->IrqRoutingTablePointer));
CopyMem (
);
}
0xE0000,
0x20000,
);
}
mHandleCount = 0;
}
/**
Dump EFI_LEGACY_INSTALL_PCI_HANDLER structure information.
@param PciHandle The pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure
**/
)
{
return;
}
/**
Copy the $PIR table as required.
@param Private Legacy BIOS Instance data
@param PciIo Pointer to PCI_IO protocol
@param PciIrq Pci IRQ number
@param PciConfigHeader Type00 Pci configuration header
**/
)
{
PrimaryMaster = 0;
SecondaryMaster = 0;
//
// Disable interrupt in PIC, in case shared, to prevent an
// interrupt from occuring.
//
&LegMask,
NULL,
NULL,
);
&LegMask,
NULL,
NULL,
);
PciIo->GetLocation (
&PciBus,
);
//
// Use native mode base address registers in two cases:
// 1. Programming Interface (PI) register indicates Primary Controller is
// in native mode OR
// 2. PCI device Sub Class Code is not IDE
//
if (((PciConfigHeader->Hdr.ClassCode[0] & 0x01) != 0) || (PciConfigHeader->Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {
Private->IntThunk->PciHandler.PrimaryControl = (UINT16) ((PciConfigHeader->Device.Bar[1] & 0xfffc) + 2);
} else {
}
//
// Secondary controller data
//
Private->IntThunk->PciHandler.SecondaryBusMaster = (UINT16) ((PciConfigHeader->Device.Bar[4] & 0xfffc) + 8);
//
// Clear pending interrupts in Bus Master registers
//
}
//
// Use native mode base address registers in two cases:
// 1. Programming Interface (PI) register indicates Secondary Controller is
// in native mode OR
// 2. PCI device Sub Class Code is not IDE
//
if (((PciConfigHeader->Hdr.ClassCode[0] & 0x04) != 0) || (PciConfigHeader->Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {
Private->IntThunk->PciHandler.SecondaryControl = (UINT16) ((PciConfigHeader->Device.Bar[3] & 0xfffc) + 2);
} else {
}
//
// Clear pending interrupts in IDE Command Block Status reg before we
// Thunk to CSM16 below. Don't want a pending Interrupt before we
// install the handlers as wierd corruption would occur and hang system.
//
//
// Read IDE CMD blk status reg to clear out any pending interrupts.
// Do here for Primary and Secondary IDE channels
//
0xE0000,
0x20000,
);
&Regs,
NULL,
0
);
0xE0000,
0x20000,
);
}
/**
Program the interrupt routing register in all the PCI devices. On a PC AT system
this register contains the 8259 IRQ vector that matches it's PCI interrupt.
@param Private Legacy BIOS Instance data
@retval EFI_SUCCESS Succeed.
@retval EFI_ALREADY_STARTED All PCI devices have been processed.
**/
)
{
//
// Note - This routine use to return immediately if Private->PciInterruptLine
// was true. Routine changed since resets etc can cause not all
// PciIo protocols to be registered the first time through.
// New algorithm is to do the copy $PIR table on first pass and save
// HandleCount on first pass. If subsequent passes LocateHandleBuffer gives
// a larger handle count then proceed with body of function else return
// EFI_ALREADY_STARTED. In addition check if PCI device InterruptLine != 0.
// If zero then function unprogrammed else skip function.
//
(VOID *) &RoutingTable,
NULL,
);
if (!Private->PciInterruptLine) {
);
}
NULL,
);
return EFI_NOT_FOUND;
}
if (HandleCount == mHandleCount) {
return EFI_ALREADY_STARTED;
}
if (mHandleCount == 0x00) {
}
//
// If VGA then only do VGA to allow drives fore time to spin up
// otherwise assign PCI IRQs to all potential devices.
//
continue;
} else {
//
// Force code to go through all handles next time called if video.
// This will catch case where HandleCount doesn't change but want
// to get drive info etc.
//
mHandleCount = 0x00;
}
);
//
// Test whether the device can be enabled or not.
// If it can't be enabled, then just skip it to avoid further operation.
//
0,
sizeof (PciConfigHeader) / sizeof (UINT32),
);
//
// Note PciIo->Attributes does not program the PCI command register
//
0,
);
);
}
continue;
}
PciIo->GetLocation (
&PciBus,
);
//
// Translate PIRQ index back thru busses to slot bus with InterruptPin
// zero based
//
InterruptPin -= 1;
Status = GetBaseBus (
);
if (Status == EFI_NOT_FOUND) {
&PciBus,
);
}
//
// Translate InterruptPin(0-3) into PIRQ
//
(PciDevice << 3),
);
//
// TranslatePirq() should never fail or we are in trouble
// If it does return failure status, check your PIRQ routing table to see if some item is missing or incorrect
//
continue;
}
);
//
// Check if device has an OPROM associated with it.
// If not invoke special 16-bit function, to allow 16-bit
// code to install an interrupt handler.
//
NULL,
NULL,
);
//
// Device has no OPROM associated with it and is a mass storage
// device. It needs to have an PCI IRQ handler installed. To
// correctly install the handler we need to insure device is
// connected. The device may just have register itself but not
// been connected. Re-read PCI config space after as it can
// change
//
//
// Get IDE Handle. If matches handle then skip ConnectController
// since ConnectController may force native mode and we don't
// want that for primary IDE controller
//
0,
);
0,
sizeof (PciConfigHeader) / sizeof (UINT32),
);
for (MassStorageHandleIndex = 0; MassStorageHandleIndex < MassStorageHandleCount; MassStorageHandleIndex++) {
//
// InstallLegacyIrqHandler according to Platform requirement
//
);
break;
}
}
}
//
// Write InterruptPin and enable 8259.
//
0x3c,
1,
);
Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask = (UINT16) (Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask | (UINT16) (1 << PciIrq));
&LegMask,
NULL,
);
&LegMask,
NULL,
);
}
}
return EFI_SUCCESS;
}
/**
Find & verify PnP Expansion header in ROM image
@param Private Protocol instance pointer.
@param FirstHeader 1 = Find first header, 0 = Find successive headers
@param PnpPtr Input Rom start if FirstHeader =1, Current Header
otherwise Output Next header, if it exists
@retval EFI_SUCCESS Next Header found at BasePnpPtr
@retval EFI_NOT_FOUND No more headers
**/
)
{
LocalPnpPtr = *PnpPtr;
if (FirstHeader == FIRST_INSTANCE) {
//
// Offset 0x1a gives offset to PnP expansion header for the first
// instance, there after the structure gives the offset to the next
// structure
//
} else {
}
//
// Search for PnP table in Shadowed ROM
//
*PnpPtr = LocalPnpPtr;
return EFI_SUCCESS;
} else {
return EFI_NOT_FOUND;
}
}
/**
Update list of Bev or BCV table entries.
@param Private Protocol instance pointer.
Handle to PCI IO for this device
@param PciIo Instance of PCI I/O Protocol
@retval EFI_SUCCESS Always should succeed.
**/
)
{
Segment = 0;
Bus = 0;
Device = 0;
Function = 0;
Class = 0;
//
// controller).
//
//
// OPROMs like PXE may not be tied to a piece of hardware and thus
// don't have a PciIo associated with them
//
PciIo->GetLocation (
&Segment,
&Bus,
&Device,
);
0x0b,
1,
);
if (Class == PCI_CLASS_MASS_STORAGE) {
} else {
if (Class == PCI_CLASS_NETWORK) {
}
}
}
while (TRUE) {
break;
}
//
// There can be additional $PnP headers within the OPROM.
// Example: SCSI can have one per drive.
//
//
// Have seen case where PXE base code have PnP expansion ROM
// header but no Bcv or Bev vectors.
//
++BbsIndex;
}
++BbsIndex;
}
if ((PnpPtr == (LEGACY_PNP_EXPANSION_HEADER *) PciPtr) || (PnpPtr > (LEGACY_PNP_EXPANSION_HEADER *) RomEnd)) {
break;
}
}
}
return EFI_SUCCESS;
}
/**
Shadow all the PCI legacy ROMs. Use data from the Legacy BIOS Protocol
to chose the order. Skip any devices that have already have legacy
BIOS run.
@param Private Protocol instance pointer.
@retval EFI_SUCCESS Succeed.
@retval EFI_UNSUPPORTED Cannot get VGA device handle.
**/
)
{
//
// Make the VGA device first
//
0,
);
return EFI_UNSUPPORTED;
}
VgaHandle = HandleBuffer[0];
NULL,
);
return Status;
}
//
// Place the VGA handle as first.
//
FirstHandle = HandleBuffer[0];
break;
}
}
//
// Allocate memory to save Command WORD from each device. We do this
// to restore devices to same state as EFI after switching to legacy.
//
);
return EFI_OUT_OF_RESOURCES;
}
//
// Disconnect all EFI devices first. This covers cases where alegacy BIOS
// may control multiple PCI devices.
//
);
//
// Save command register for "connect" loop
//
0,
sizeof (PciConfigHeader) / sizeof (UINT32),
);
//
// Skip any device that already has a legacy ROM run
//
continue;
}
//
// Stop EFI Drivers with oprom.
//
NULL,
);
}
//
// For every device that has not had a legacy ROM started. Start a legacy ROM.
//
);
//
// Here make sure if one VGA have been shadowed,
// then wil not shadowed another one.
//
0,
&Pci
);
//
// Only one Video OPROM can be given control in BIOS phase. If there are multiple Video devices,
// one will work in legacy mode (OPROM will be given control) and
// other Video devices will work in native mode (OS driver will handle these devices).
//
continue;
}
//
// Skip any device that already has a legacy ROM run
//
continue;
}
//
// Install legacy ROM
//
NULL,
&Flags,
NULL,
NULL,
);
continue;
}
}
//
// Restore Command register so legacy has same devices enabled or disabled
// as EFI.
// If Flags = NO_ROM use command register as is. This covers the
// following cases:
// Device has no ROMs associated with it.
// Device has ROM associated with it but was already
// installed.
// = ROM_FOUND but not VALID_LEGACY_ROM, disable it.
// = ROM_FOUND and VALID_LEGACY_ROM, enable it.
//
if ((Flags & VALID_LEGACY_ROM) == 0) {
} else {
//
// For several VGAs, only one of them can be enabled.
//
0,
);
);
}
}
}
}
0x04,
1,
);
}
return EFI_SUCCESS;
}
/**
Test to see if a legacy PCI ROM exists for this device. Optionally return
the Legacy ROM instance for this PCI device.
@param This Protocol instance pointer.
@param PciHandle The PCI PC-AT OPROM from this devices ROM BAR will
be loaded
@param RomImage Return the legacy PCI ROM for this device
@param RomSize Size of ROM Image
@param Flags Indicates if ROM found and if PC-AT.
@retval EFI_SUCCESS Legacy Option ROM availible for this device
@retval EFI_UNSUPPORTED Legacy Option ROM not supported.
**/
)
{
return LegacyBiosCheckPciRomEx (
This,
NULL,
NULL,
);
}
/**
Routine Description:
Test to see if a legacy PCI ROM exists for this device. Optionally return
the Legacy ROM instance for this PCI device.
@param[in] This Protocol instance pointer.
@param[in] PciHandle The PCI PC-AT OPROM from this devices ROM BAR will be loaded
@param[out] RomImage Return the legacy PCI ROM for this device
@param[out] RomSize Size of ROM Image
@param[out] RuntimeImageLength Runtime size of ROM Image
@param[out] Flags Indicates if ROM found and if PC-AT.
@param[out] OpromRevision Revision of the PCI Rom
@param[out] ConfigUtilityCodeHeaderPointer of Configuration Utility Code Header
@return EFI_SUCCESS Legacy Option ROM availible for this device
@return EFI_ALREADY_STARTED This device is already managed by its Oprom
@return EFI_UNSUPPORTED Legacy Option ROM not supported.
**/
)
{
);
return EFI_UNSUPPORTED;
}
//
// See if the option ROM for PciHandle has already been executed
//
return EFI_SUCCESS;
}
//
// Check for PCI ROM Bar
//
if (LocalRomSize != 0) {
}
//
// PCI specification states you should check VendorId and Device Id.
//
0,
sizeof (PciConfigHeader) / sizeof (UINT32),
);
);
return EFI_UNSUPPORTED;
}
*Flags |= VALID_LEGACY_ROM;
//
// See if Configuration Utility Code Header valid
//
if (LocalConfigUtilityCodeHeader != NULL) {
*Flags |= ROM_WITH_CONFIG;
}
if (ConfigUtilityCodeHeader != NULL) {
}
}
*RomSize = LocalRomSize;
}
return EFI_SUCCESS;
}
/**
Load a legacy PC-AT OPROM on the PciHandle device. Return information
about how many disks were added by the OPROM and the shadow address and
size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:
@retval EFI_SUCCESS Legacy ROM loaded for this device
@retval EFI_NOT_FOUND No PS2 Keyboard found
**/
)
{
//
// Get SimpleTextIn and find PS2 controller
//
NULL,
);
return EFI_NOT_FOUND;
}
//
// Open the IO Abstraction(s) needed to perform the supported test
//
NULL,
);
//
// Use the ISA I/O Protocol to see if Controller is the Keyboard
// controller
//
if (IsaIo->ResourceList->Device.HID != EISA_PNP_ID (0x303) || IsaIo->ResourceList->Device.UID != 0) {
}
gBS->CloseProtocol (
NULL,
);
}
}
}
return EFI_SUCCESS;
}
/**
Load a legacy PC-AT OpROM for VGA controller.
@param Private Driver private data.
@retval EFI_SUCCESS Legacy ROM successfully installed for this device.
@retval EFI_DEVICE_ERROR No VGA device handle found, or native EFI video
driver cannot be successfully disconnected, or VGA
thunk driver cannot be successfully connected.
**/
)
{
//
// EfiLegacyBiosGuild attached to a device implies that there is a legacy
// BIOS associated with that device.
//
// There are 3 cases to consider.
// Case 1: No EFI driver is controlling the video.
// Action: Return EFI_SUCCESS from DisconnectController, search
// video thunk driver, and connect it.
// Case 2: EFI driver is controlling the video and EfiLegacyBiosGuid is
// not on the image handle.
// Action: Disconnect EFI driver.
// ConnectController for video thunk
// Case 3: EFI driver is controlling the video and EfiLegacyBiosGuid is
// on the image handle.
// Action: Do nothing and set Private->VgaInstalled = TRUE.
// Then this routine is not called any more.
//
//
// Get the VGA device.
//
0,
);
return EFI_DEVICE_ERROR;
}
VgaHandle = HandleBuffer[0];
//
// Check whether video thunk driver already starts.
//
);
return Status;
}
);
//
// This should be video thunk driver which is managing video device
// So it need not start again
//
return EFI_SUCCESS;
}
}
}
//
// Kick off the native EFI driver
//
NULL,
);
if (Status != EFI_NOT_FOUND) {
return EFI_DEVICE_ERROR;
} else {
return Status;
}
}
//
// Find all the Thunk Driver
//
HandleBuffer = NULL;
NULL,
);
CopyMem (
sizeof (EFI_HANDLE) * HandleCount
);
//
// Enable the device and make sure VGA cycles are being forwarded to this VGA device
//
);
0,
sizeof (PciConfigHeader) / sizeof (UINT32),
);
0,
);
);
}
if (Status == EFI_SUCCESS) {
//
// Attach the VGA thunk driver.
// Assume the video is installed. This prevents potential of infinite recursion.
//
NULL,
);
}
//
// Reconnect the EFI VGA driver.
//
return EFI_DEVICE_ERROR;
}
return EFI_SUCCESS;
}
/**
Load a legacy PC-AT OpROM.
@param This Protocol instance pointer.
@param Private Driver's private data.
@param PciHandle The EFI handle for the PCI device. It could be
NULL if the OpROM image is not associated with
any device.
@param OpromRevision The revision of PCI PC-AT ROM image.
@param RomImage Pointer to PCI PC-AT ROM image header. It must not
be NULL.
@param ImageSize Size of the PCI PC-AT ROM image.
@param RuntimeImageLength On input is the max runtime image length indicated by the PCIR structure
On output is the actual runtime image length
@param DiskStart Disk number of first device hooked by the ROM. If
DiskStart is the same as DiskEnd no disked were
hooked.
@param DiskEnd Disk number of the last device hooked by the ROM.
@param RomShadowAddress Shadow address of PC-AT ROM
@retval EFI_SUCCESS Legacy ROM loaded for this device
@retval EFI_OUT_OF_RESOURCES No more space for this ROM
**/
)
{
LocalDiskStart = 0;
LocalDiskEnd = 0;
Segment = 0;
Bus = 0;
Device = 0;
Function = 0;
VideoMode = 0;
PhysicalAddress = 0;
//
// CSM16 3.0 meets PCI 3.0 OpROM
// first test if there is enough space for its INIT code
//
);
DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));
return EFI_OUT_OF_RESOURCES;
}
//
// then test if there is enough space for its RT code
//
DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));
return EFI_OUT_OF_RESOURCES;
}
} else {
// CSM16 3.0 meets PCI 2.x OpROM
// CSM16 2.x meets PCI 2.x/3.0 OpROM
// test if there is enough space for its INIT code
//
DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));
return EFI_OUT_OF_RESOURCES;
}
}
0xE0000,
0x20000,
);
);
DEBUG ((EFI_D_INFO, " Shadowing OpROM init/runtime/isize = %x/%x/%x\n", InitAddress, RuntimeAddress, ImageSize));
//
// Read the highest disk number "installed: and assume a new disk will
// show up on the first drive past the current value.
// There are several considerations here:
// 1. Non-BBS compliant drives will change 40:75 but 16-bit CSM will undo
// the change until boot selection time frame.
// 2. BBS compliants drives will not change 40:75 until boot time.
// 3. Onboard IDE controllers will change 40:75
//
//
// Update table since onboard IDE drives found
//
Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = (UINT8) (Private->Disk4075 + 0x80);
}
if (PciHandle != mVgaHandle) {
//
// Store current mode settings since PrepareToScanRom may change mode.
//
}
//
// Notify the platform that we are about to scan the ROM
//
0,
NULL,
);
//
// If Status returned is EFI_UNSUPPORTED then abort due to platform
// policy.
//
if (Status == EFI_UNSUPPORTED) {
goto Done;
}
//
// Report corresponding status code
//
);
//
// Generate number of ticks since midnight for BDA. Some OPROMs require
// this. Place result in 40:6C-6F
//
//
// Multiply result by 18.2 for number of ticks since midnight.
// Use 182/10 to avoid floating point math.
//
//
// Pass in handoff data
//
);
//
// Enable command register.
//
);
PciIo->GetLocation (
&Segment,
&Bus,
&Device,
);
}
//
// Generate DispatchOpRomTable data
//
Private->IntThunk->DispatchOpromTable.PnPInstallationCheckSegment = Private->Legacy16Table->PnPInstallationCheckSegment;
Private->IntThunk->DispatchOpromTable.PnPInstallationCheckOffset = Private->Legacy16Table->PnPInstallationCheckOffset;
Private->IntThunk->DispatchOpromTable.NumberBbsEntries = (UINT8) Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;
Private->IntThunk->DispatchOpromTable.RuntimeSegment = (UINT16)((OpromRevision < 3) ? 0xffff : (RuntimeAddress >> 4));
//
// Skip dispatching ROM for those PCI devices that can not be enabled by PciIo->Attributes
// Otherwise, it may cause the system to hang in some cases
//
if (!EFI_ERROR (PciEnableStatus)) {
&Regs,
NULL,
0
);
} else {
}
if (Private->IntThunk->DispatchOpromTable.NumberBbsEntries != (UINT8) Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries) {
Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries = (UINT8) Private->IntThunk->DispatchOpromTable.NumberBbsEntries;
}
//
// Check if non-BBS compliant drives found
//
}
//
// Skip video mode set, if installing VGA
//
if (PciHandle != mVgaHandle) {
//
// Set mode settings since PrepareToScanRom may change mode
//
}
//
// Regs.X.AX from the adapter initializion is ignored since some adapters
// do not follow the standard of setting AX = 0 on success.
//
//
// The ROM could have updated it's size so we need to read again.
//
//
// If OpROM runs in 2.0 mode
//
if (PhysicalAddress == 0) {
if (*RuntimeImageLength < ImageSize) {
//
// Make area from end of shadowed rom to end of original rom all ffs
//
}
}
//
// Allow platform to perform any required actions after the
// OPROM has been initialized.
//
0,
NULL,
);
//
// If no PCI Handle then no header or Bevs.
//
if ((*RuntimeImageLength != 0) && (!mIgnoreBbsUpdateFlag)) {
);
if (LocalDiskEnd != LocalDiskStart) {
}
}
//
// Mark PCI device as having a legacy BIOS ROM loaded.
//
);
}
//
// Stuff caller's OPTIONAL return parameters.
//
if (RomShadowAddress != NULL) {
}
}
*DiskEnd = LocalDiskEnd;
}
Done:
if (PhysicalAddress != 0) {
//
// Free pages when OpROM is 3.0
//
}
//
// Insure all shadowed areas are locked
//
0xC0000,
0x40000,
);
return Status;
}
/**
Load a legacy PC-AT OPROM on the PciHandle device. Return information
about how many disks were added by the OPROM and the shadow address and
size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:
@param This Protocol instance pointer.
@param PciHandle The PCI PC-AT OPROM from this devices ROM BAR will
be loaded. This value is NULL if RomImage is
non-NULL. This is the normal case.
@param RomImage A PCI PC-AT ROM image. This argument is non-NULL
if there is no hardware associated with the ROM
and thus no PciHandle, otherwise is must be NULL.
Example is PXE base code.
@param Flags Indicates if ROM found and if PC-AT.
@param DiskStart Disk number of first device hooked by the ROM. If
DiskStart is the same as DiskEnd no disked were
hooked.
@param DiskEnd Disk number of the last device hooked by the ROM.
@param RomShadowAddress Shadow address of PC-AT ROM
@param RomShadowedSize Size of RomShadowAddress in bytes
@retval EFI_SUCCESS Legacy ROM loaded for this device
@retval EFI_INVALID_PARAMETER PciHandle not found
@retval EFI_UNSUPPORTED There is no PCI ROM in the ROM BAR or no onboard
ROM
**/
)
{
OpromRevision = 0;
//
// Get last bus number if not already found
//
NULL,
);
LastBus = 0;
);
continue;
}
&PciBus,
);
}
}
0xE0000,
0x20000,
);
0xE0000,
0x20000,
);
}
*Flags = 0;
//
// If PciHandle has OpRom to Execute
// and OpRom are all associated with Hardware
//
);
0,
sizeof (PciConfigHeader) / sizeof (UINT32),
);
//
// if video installed & OPROM is video return
//
if (
(
||
)
&&
(!Private->VgaInstalled)
) {
//
// return EFI_UNSUPPORTED;
//
}
}
//
// To run any legacy image, the VGA needs to be installed first.
// if installing the video, then don't need the thunk as already installed.
//
0,
);
mVgaHandle = HandleBuffer[0];
//
// A return status of EFI_NOT_FOUND is considered valid (No EFI
// driver is controlling video.
//
if (Status != EFI_NOT_FOUND) {
return Status;
}
} else {
}
}
}
//
// See if the option ROM for PciHandle has already been executed
//
(UINTN *) RomShadowedSize
);
return EFI_SUCCESS;
}
);
//
// There is no PCI ROM in the ROM BAR or no onboard ROM
//
return EFI_UNSUPPORTED;
}
} else {
//
// If PciHandle is NULL, and no OpRom is to be associated
//
return EFI_UNSUPPORTED;
}
if (!Private->VgaInstalled) {
//
// A return status of EFI_NOT_FOUND is considered valid (No EFI
// driver is controlling video.
//
if (Status != EFI_NOT_FOUND) {
return Status;
}
} else {
}
}
if (((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE ||
return EFI_UNSUPPORTED;
}
Pcir = (PCI_3_0_DATA_STRUCTURE *)
return EFI_UNSUPPORTED;
}
} else {
OpromRevision = 0;
}
RuntimeImageLength = 0;
} else {
}
}
//
// Shadow and initialize the OpROM.
//
Private->TraceIndex ++;
This,
);
if (RomShadowedSize != NULL) {
}
return Status;
}