/** @file
Header file for IDE Bus Driver's Data Structures
Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _IDE_DATA_H_
#define _IDE_DATA_H_
#include <IndustryStandard/Atapi.h>
//
// common constants
//
typedef enum {
IdePrimary = 0,
typedef enum {
IdeMaster = 0,
typedef enum {
typedef enum {
} SENSE_RESULT;
typedef enum {
//
// IDE Registers
//
typedef union {
typedef union {
typedef union {
//
// IDE registers set
//
typedef struct {
//
// IDE registers' base addresses
//
typedef struct {
//
// Bit definitions in Programming Interface byte of the Class Code field
// in PCI IDE controller's Configuration Space
//
//
// Bus Master Reg
//
//
// Time Out Value For IDE Device Polling
//
//
// ATATIMEOUT is used for waiting time out for ATA device
//
//
// 1 second
//
//
// ATAPITIMEOUT is used for waiting operation
// except read and write time out for ATAPI device
//
//
// 1 second
//
//
// ATAPILONGTIMEOUT is used for waiting read and
// write operation timeout for ATAPI device
//
//
// 2 seconds
//
//
// 5 seconds
//
//
// 10 seconds
//
//
// ATAPI6 related data structure definition
//
//
// The maximum sectors count in 28 bit addressing mode
//
#pragma pack(1)
typedef struct {
} IDE_DMA_PRD;
#pragma pack()
///
/// PIO mode definition
///
typedef enum _ATA_PIO_MODE_ {
} ATA_PIO_MODE;
//
// Multi word DMA definition
//
typedef enum _ATA_MDMA_MODE_ {
//
// UDMA mode definition
//
typedef enum _ATA_UDMA_MODE_ {
#pragma pack(1)
typedef struct {
typedef struct {
#pragma pack()
//
// IORDY Sample Point field value
//
#define ISP_5_CLK 0
//
// Recovery Time field value
//
#define RECVY_4_CLK 0
//
// Slave IDE Timing Register Enable
//
//
// DMA Timing Enable Only Select 1
//
//
// Pre-fetch and Posting Enable Select 1
//
//
// IORDY Sample Point Enable Select 1
//
//
// Fast Timing Bank Drive Select 1
//
//
// DMA Timing Enable Only Select 0
//
//
// Pre-fetch and Posting Enable Select 0
//
//
// IOREY Sample Point Enable Select 0
//
//
// Fast Timing Bank Drive Select 0
//
#endif