/** @file
* IPRT - Assembly Functions.
*/
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* The contents of this file may alternatively be used under the terms
* of the Common Development and Distribution License Version 1.0
* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
* VirtualBox OSE distribution, in which case the provisions of the
* CDDL are applicable instead of those of the GPL.
*
* You may elect to license modified versions of this file under the
* terms and conditions of either the GPL or the CDDL or both.
*/
#ifndef ___iprt_asm_h
#define ___iprt_asm_h
/** @def RT_INLINE_ASM_USES_INTRIN
* Defined as 1 if we're using a _MSC_VER 1400.
* Otherwise defined as 0.
*/
/* Solaris 10 header ugliness */
#ifdef u
# undef u
#endif
#if defined(_MSC_VER) && RT_INLINE_ASM_USES_INTRIN
# include <intrin.h>
/* Emit the intrinsics at all optimization levels. */
# pragma intrinsic(_ReadWriteBarrier)
# pragma intrinsic(_BitScanForward)
# pragma intrinsic(_BitScanReverse)
# pragma intrinsic(_bittestandset)
# pragma intrinsic(_bittestandreset)
# pragma intrinsic(_bittestandcomplement)
# pragma intrinsic(_byteswap_ushort)
# pragma intrinsic(_byteswap_ulong)
# pragma intrinsic(_interlockedbittestandset)
# pragma intrinsic(_interlockedbittestandreset)
# pragma intrinsic(_InterlockedAnd)
# pragma intrinsic(_InterlockedOr)
# pragma intrinsic(_InterlockedIncrement)
# pragma intrinsic(_InterlockedDecrement)
# pragma intrinsic(_InterlockedExchange)
# pragma intrinsic(_InterlockedExchangeAdd)
# pragma intrinsic(_InterlockedCompareExchange)
# pragma intrinsic(_InterlockedCompareExchange64)
# ifdef RT_ARCH_AMD64
# pragma intrinsic(_byteswap_uint64)
# pragma intrinsic(_InterlockedExchange64)
# pragma intrinsic(_InterlockedExchangeAdd64)
# pragma intrinsic(_InterlockedAnd64)
# pragma intrinsic(_InterlockedOr64)
# pragma intrinsic(_InterlockedIncrement64)
# pragma intrinsic(_InterlockedDecrement64)
# endif
#endif
/** @defgroup grp_rt_asm ASM - Assembly Routines
* @ingroup grp_rt
*
* @remarks The difference between ordered and unordered atomic operations are that
* the former will complete outstanding reads and writes before continuing
* while the latter doesn't make any promises about the order. Ordered
* operations doesn't, it seems, make any 100% promise wrt to whether
* the operation will complete before any subsequent memory access.
* (please, correct if wrong.)
*
* ASMAtomicSomething operations are all ordered, while ASMAtomicUoSomething
* are unordered (note the Uo).
*
* @remarks Some remarks about __volatile__: Without this keyword gcc is allowed to reorder
* or even optimize assembler instructions away. For instance, in the following code
* the second rdmsr instruction is optimized away because gcc treats that instruction
* as deterministic:
*
* @code
* static inline uint64_t rdmsr_low(int idx)
* {
* uint32_t low;
* __asm__ ("rdmsr" : "=a"(low) : "c"(idx) : "edx");
* }
* ...
* uint32_t msr1 = rdmsr_low(1);
* foo(msr1);
* msr1 = rdmsr_low(1);
* bar(msr1);
* @endcode
*
* The input parameter of rdmsr_low is the same for both calls and therefore gcc will
* use the result of the first call as input parameter for bar() as well. For rdmsr this
* is not acceptable as this instruction is _not_ deterministic. This applies to reading
* machine status information in general.
*
* @{
*/
/** @def RT_INLINE_ASM_GCC_4_3_X_X86
* Used to work around some 4.3.x register allocation issues in this version of
* the compiler. So far this workaround is still required for 4.4 and 4.5. */
#ifdef __GNUC__
#endif
#ifndef RT_INLINE_ASM_GCC_4_3_X_X86
# define RT_INLINE_ASM_GCC_4_3_X_X86 0
#endif
/** @def RT_INLINE_DONT_USE_CMPXCHG8B
* i686-apple-darwin9-gcc-4.0.1 (GCC) 4.0.1 (Apple Inc. build 5493) screws up
* RTSemRWRequestWrite semsemrw-lockless-generic.cpp in release builds. PIC
* mode, x86.
*
* Some gcc 4.3.x versions may have register allocation issues with cmpxchg8b
* when in PIC mode on x86.
*/
# ifdef DOXYGEN_RUNNING
# else
# define RT_INLINE_DONT_MIX_CMPXCHG8B_AND_PIC \
&& defined(RT_ARCH_X86) \
&& ( RT_INLINE_ASM_GCC_4_3_X_X86 \
|| defined(RT_OS_DARWIN)) )
# endif
#endif
/** @def ASMReturnAddress
* Gets the return address of the current (or calling if you like) function or method.
*/
#ifdef _MSC_VER
# ifdef __cplusplus
extern "C"
# endif
void * _ReturnAddress(void);
# pragma intrinsic(_ReturnAddress)
#else
# error "Unsupported compiler."
#endif
/**
* Compiler memory barrier.
*
* values or any outstanding writes when returning from this function.
*
* This function must be used if non-volatile data is modified by a
* device or the VMM. Typical cases are port access, MMIO access,
* trapping instruction, etc.
*/
#else /* 2003 should have _ReadWriteBarrier() but I guess we're at 2002 level then... */
{
{
}
}
#endif
/** @def ASMBreakpoint
* Debugger Breakpoint.
* @deprecated Use RT_BREAKPOINT instead.
* @internal
*/
/**
* Spinloop hint for platforms that have these, empty function on the other
* platforms.
*
* x86 & AMD64: The PAUSE variant of NOP for helping hyperthreaded CPUs detecting
* spin locks.
*/
DECLASM(void) ASMNopPause(void);
#else
{
# if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
# else
__asm {
_emit 090h
}
# endif
# else
/* dummy */
# endif
}
#endif
/**
* Atomically Exchange an unsigned 8-bit value, ordered.
*
* @returns Current *pu8 value
* @param pu8 Pointer to the 8-bit variable to update.
* @param u8 The 8-bit value to assign to *pu8.
*/
#else
{
: "=m" (*pu8),
: "1" (u8),
"m" (*pu8));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return u8;
}
#endif
/**
* Atomically Exchange a signed 8-bit value, ordered.
*
* @returns Current *pu8 value
* @param pi8 Pointer to the 8-bit variable to update.
* @param i8 The 8-bit value to assign to *pi8.
*/
{
}
/**
* Atomically Exchange a bool value, ordered.
*
* @returns Current *pf value
* @param pf Pointer to the 8-bit variable to update.
* @param f The 8-bit value to assign to *pi8.
*/
{
#ifdef _MSC_VER
#else
#endif
}
/**
* Atomically Exchange an unsigned 16-bit value, ordered.
*
* @returns Current *pu16 value
* @param pu16 Pointer to the 16-bit variable to update.
* @param u16 The 16-bit value to assign to *pu16.
*/
#else
{
: "=m" (*pu16),
"=r" (u16)
: "1" (u16),
"m" (*pu16));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return u16;
}
#endif
/**
* Atomically Exchange a signed 16-bit value, ordered.
*
* @returns Current *pu16 value
* @param pi16 Pointer to the 16-bit variable to update.
* @param i16 The 16-bit value to assign to *pi16.
*/
{
}
/**
* Atomically Exchange an unsigned 32-bit value, ordered.
*
* @returns Current *pu32 value
* @param pu32 Pointer to the 32-bit variable to update.
* @param u32 The 32-bit value to assign to *pu32.
*/
#else
{
: "=m" (*pu32),
"=r" (u32)
: "1" (u32),
"m" (*pu32));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return u32;
}
#endif
/**
* Atomically Exchange a signed 32-bit value, ordered.
*
* @returns Current *pu32 value
* @param pi32 Pointer to the 32-bit variable to update.
* @param i32 The 32-bit value to assign to *pi32.
*/
{
}
/**
* Atomically Exchange an unsigned 64-bit value, ordered.
*
* @returns Current *pu64 value
* @param pu64 Pointer to the 64-bit variable to update.
* @param u64 The 64-bit value to assign to *pu64.
*/
#if (RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN) \
#else
{
# if defined(RT_ARCH_AMD64)
: "=m" (*pu64),
"=r" (u64)
: "1" (u64),
"m" (*pu64));
# else
{
}
# endif
# else /* !RT_ARCH_AMD64 */
"xchgl %%ebx, %3\n\t"
"1:\n\t"
"lock; cmpxchg8b (%5)\n\t"
"jnz 1b\n\t"
"movl %3, %%ebx\n\t"
/*"xchgl %%esi, %5\n\t"*/
: "=A" (u64),
"=m" (*pu64)
: "0" (*pu64),
"m" ( u32EBX ),
"S" (pu64));
# else /* !PIC */
"lock; cmpxchg8b %1\n\t"
"jnz 1b\n\t"
: "=A" (u64),
"=m" (*pu64)
: "0" (*pu64),
# endif
# else
{
}
# endif
# endif /* !RT_ARCH_AMD64 */
return u64;
}
#endif
/**
* Atomically Exchange an signed 64-bit value, ordered.
*
* @returns Current *pi64 value
* @param pi64 Pointer to the 64-bit variable to update.
* @param i64 The 64-bit value to assign to *pi64.
*/
{
}
/**
* Atomically Exchange a pointer value, ordered.
*
* @returns Current *ppv value
* @param ppv Pointer to the pointer variable to update.
* @param pv The pointer value to assign to *ppv.
*/
{
#if ARCH_BITS == 32
#else
# error "ARCH_BITS is bogus"
#endif
}
/**
* Convenience macro for avoiding the annoying casting with ASMAtomicXchgPtr.
*
* @returns Current *pv value
* @param ppv Pointer to the pointer variable to update.
* @param pv The pointer value to assign to *ppv.
* @param Type The type of *ppv, sans volatile.
*/
#ifdef __GNUC__
({\
Type pvTypeCheckedRet = (__typeof__(*(ppv))) ASMAtomicXchgPtr((void * volatile *)ppvTypeChecked, (void *)pvTypeChecked); \
})
#else
#endif
/**
* Atomically Exchange a raw-mode context pointer value, ordered.
*
* @returns Current *ppv value
* @param ppvRC Pointer to the pointer variable to update.
* @param pvRC The pointer value to assign to *ppv.
*/
{
}
/**
* Atomically Exchange a ring-0 pointer value, ordered.
*
* @returns Current *ppv value
* @param ppvR0 Pointer to the pointer variable to update.
* @param pvR0 The pointer value to assign to *ppv.
*/
{
#if R0_ARCH_BITS == 32
#else
# error "R0_ARCH_BITS is bogus"
#endif
}
/**
* Atomically Exchange a ring-3 pointer value, ordered.
*
* @returns Current *ppv value
* @param ppvR3 Pointer to the pointer variable to update.
* @param pvR3 The pointer value to assign to *ppv.
*/
{
#if R3_ARCH_BITS == 32
#else
# error "R3_ARCH_BITS is bogus"
#endif
}
/** @def ASMAtomicXchgHandle
* Atomically Exchange a typical IPRT handle value, ordered.
*
* @param ph Pointer to the value to update.
* @param hNew The new value to assigned to *pu.
* @param phRes Where to store the current *ph value.
*
* @remarks This doesn't currently work for all handles (like RTFILE).
*/
#if HC_ARCH_BITS == 32
do { \
} while (0)
do { \
} while (0)
#else
#endif
/**
* Atomically Exchange a value which size might differ
* between platforms or compilers, ordered.
*
* @param pu Pointer to the variable to update.
* @param uNew The value to assign to *pu.
* @todo This is busted as its missing the result argument.
*/
do { \
switch (sizeof(*(pu))) { \
} \
} while (0)
/**
* Atomically Exchange a value which size might differ
* between platforms or compilers, ordered.
*
* @param pu Pointer to the variable to update.
* @param uNew The value to assign to *pu.
* @param puRes Where to store the current *pu value.
*/
do { \
switch (sizeof(*(pu))) { \
case 1: *(uint8_t *)(puRes) = ASMAtomicXchgU8((volatile uint8_t *)(void *)(pu), (uint8_t)(uNew)); break; \
case 2: *(uint16_t *)(puRes) = ASMAtomicXchgU16((volatile uint16_t *)(void *)(pu), (uint16_t)(uNew)); break; \
case 4: *(uint32_t *)(puRes) = ASMAtomicXchgU32((volatile uint32_t *)(void *)(pu), (uint32_t)(uNew)); break; \
case 8: *(uint64_t *)(puRes) = ASMAtomicXchgU64((volatile uint64_t *)(void *)(pu), (uint64_t)(uNew)); break; \
} \
} while (0)
/**
* Atomically Compare and Exchange an unsigned 8-bit value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pu8 Pointer to the value to update.
* @param u8New The new value to assigned to *pu8.
* @param u8Old The old value to *pu8 compare with.
*/
#else
{
"setz %1\n\t"
: "=m" (*pu8),
"=qm" (u8Ret),
"=a" (u8Old)
: "q" (u8New),
"2" (u8Old),
"m" (*pu8));
return (bool)u8Ret;
}
#endif
/**
* Atomically Compare and Exchange a signed 8-bit value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pi8 Pointer to the value to update.
* @param i8New The new value to assigned to *pi8.
* @param i8Old The old value to *pi8 compare with.
*/
{
}
/**
* Atomically Compare and Exchange a bool value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pf Pointer to the value to update.
* @param fNew The new value to assigned to *pf.
* @param fOld The old value to *pf compare with.
*/
{
}
/**
* Atomically Compare and Exchange an unsigned 32-bit value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pu32 Pointer to the value to update.
* @param u32New The new value to assigned to *pu32.
* @param u32Old The old value to *pu32 compare with.
*/
DECLASM(bool) ASMAtomicCmpXchgU32(volatile uint32_t *pu32, const uint32_t u32New, const uint32_t u32Old);
#else
DECLINLINE(bool) ASMAtomicCmpXchgU32(volatile uint32_t *pu32, const uint32_t u32New, uint32_t u32Old)
{
"setz %1\n\t"
: "=m" (*pu32),
"=qm" (u8Ret),
"=a" (u32Old)
: "r" (u32New),
"2" (u32Old),
"m" (*pu32));
return (bool)u8Ret;
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
# ifdef RT_ARCH_AMD64
# else
# endif
}
return !!u32Ret;
# endif
}
#endif
/**
* Atomically Compare and Exchange a signed 32-bit value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pi32 Pointer to the value to update.
* @param i32New The new value to assigned to *pi32.
* @param i32Old The old value to *pi32 compare with.
*/
DECLINLINE(bool) ASMAtomicCmpXchgS32(volatile int32_t *pi32, const int32_t i32New, const int32_t i32Old)
{
}
/**
* Atomically Compare and exchange an unsigned 64-bit value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pu64 Pointer to the 64-bit variable to update.
* @param u64New The 64-bit value to assign to *pu64.
* @param u64Old The value to compare with.
*/
#if (RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN) \
DECLASM(bool) ASMAtomicCmpXchgU64(volatile uint64_t *pu64, const uint64_t u64New, const uint64_t u64Old);
#else
{
# elif defined(RT_ARCH_AMD64)
"setz %1\n\t"
: "=m" (*pu64),
"=qm" (u8Ret),
"=a" (u64Old)
: "r" (u64New),
"2" (u64Old),
"m" (*pu64));
return (bool)u8Ret;
# else
bool fRet;
{
}
return fRet;
# endif
# else /* !RT_ARCH_AMD64 */
"lock; cmpxchg8b (%6)\n\t"
"setz %%al\n\t"
"movl %4, %%ebx\n\t"
"movzbl %%al, %%eax\n\t"
: "=a" (u32Ret),
"=d" (u32Spill),
"+m" (*pu64)
# else
"=m" (*pu64)
# endif
: "A" (u64Old),
"m" ( u32EBX ),
"S" (pu64));
# else /* !PIC */
"setz %%al\n\t"
"movzbl %%al, %%eax\n\t"
: "=a" (u32Ret),
"=d" (u32Spill),
"+m" (*pu64)
: "A" (u64Old),
# endif
return (bool)u32Ret;
# else
{
}
return !!u32Ret;
# endif
# endif /* !RT_ARCH_AMD64 */
}
#endif
/**
* Atomically Compare and exchange a signed 64-bit value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pi64 Pointer to the 64-bit variable to update.
* @param i64 The 64-bit value to assign to *pu64.
* @param i64Old The value to compare with.
*/
DECLINLINE(bool) ASMAtomicCmpXchgS64(volatile int64_t *pi64, const int64_t i64, const int64_t i64Old)
{
}
/**
* Atomically Compare and Exchange a pointer value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param ppv Pointer to the value to update.
* @param pvNew The new value to assigned to *ppv.
* @param pvOld The old value to *ppv compare with.
*/
DECLINLINE(bool) ASMAtomicCmpXchgPtrVoid(void * volatile *ppv, const void *pvNew, const void *pvOld)
{
#if ARCH_BITS == 32
#else
# error "ARCH_BITS is bogus"
#endif
}
/**
* Atomically Compare and Exchange a pointer value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param ppv Pointer to the value to update.
* @param pvNew The new value to assigned to *ppv.
* @param pvOld The old value to *ppv compare with.
*
* @remarks This is relatively type safe on GCC platforms.
*/
#ifdef __GNUC__
({\
(void *)pvNewTypeChecked, (void *)pvOldTypeChecked); \
fMacroRet; \
})
#else
#endif
/** @def ASMAtomicCmpXchgHandle
* Atomically Compare and Exchange a typical IPRT handle value, ordered.
*
* @param ph Pointer to the value to update.
* @param hNew The new value to assigned to *pu.
* @param hOld The old value to *pu compare with.
* @param fRc Where to store the result.
*
* @remarks This doesn't currently work for all handles (like RTFILE).
*/
#if HC_ARCH_BITS == 32
do { \
(fRc) = ASMAtomicCmpXchgU32((uint32_t volatile *)(ph), (const uint32_t)(hNew), (const uint32_t)(hOld)); \
} while (0)
do { \
(fRc) = ASMAtomicCmpXchgU64((uint64_t volatile *)(ph), (const uint64_t)(hNew), (const uint64_t)(hOld)); \
} while (0)
#else
#endif
/** @def ASMAtomicCmpXchgSize
* Atomically Compare and Exchange a value which size might differ
* between platforms or compilers, ordered.
*
* @param pu Pointer to the value to update.
* @param uNew The new value to assigned to *pu.
* @param uOld The old value to *pu compare with.
* @param fRc Where to store the result.
*/
do { \
switch (sizeof(*(pu))) { \
case 4: (fRc) = ASMAtomicCmpXchgU32((volatile uint32_t *)(void *)(pu), (uint32_t)(uNew), (uint32_t)(uOld)); \
break; \
case 8: (fRc) = ASMAtomicCmpXchgU64((volatile uint64_t *)(void *)(pu), (uint64_t)(uNew), (uint64_t)(uOld)); \
break; \
(fRc) = false; \
break; \
} \
} while (0)
/**
* Atomically Compare and Exchange an unsigned 32-bit value, additionally
* passes back old value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pu32 Pointer to the value to update.
* @param u32New The new value to assigned to *pu32.
* @param u32Old The old value to *pu32 compare with.
* @param pu32Old Pointer store the old value at.
*/
DECLASM(bool) ASMAtomicCmpXchgExU32(volatile uint32_t *pu32, const uint32_t u32New, const uint32_t u32Old, uint32_t *pu32Old);
#else
DECLINLINE(bool) ASMAtomicCmpXchgExU32(volatile uint32_t *pu32, const uint32_t u32New, const uint32_t u32Old, uint32_t *pu32Old)
{
"setz %1\n\t"
: "=m" (*pu32),
"=qm" (u8Ret),
"=a" (*pu32Old)
: "r" (u32New),
"a" (u32Old),
"m" (*pu32));
return (bool)u8Ret;
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
# ifdef RT_ARCH_AMD64
# else
# endif
}
return !!u32Ret;
# endif
}
#endif
/**
* Atomically Compare and Exchange a signed 32-bit value, additionally
* passes back old value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pi32 Pointer to the value to update.
* @param i32New The new value to assigned to *pi32.
* @param i32Old The old value to *pi32 compare with.
* @param pi32Old Pointer store the old value at.
*/
DECLINLINE(bool) ASMAtomicCmpXchgExS32(volatile int32_t *pi32, const int32_t i32New, const int32_t i32Old, int32_t *pi32Old)
{
return ASMAtomicCmpXchgExU32((volatile uint32_t *)pi32, (uint32_t)i32New, (uint32_t)i32Old, (uint32_t *)pi32Old);
}
/**
* Atomically Compare and exchange an unsigned 64-bit value, additionally
* passing back old value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pu64 Pointer to the 64-bit variable to update.
* @param u64New The 64-bit value to assign to *pu64.
* @param u64Old The value to compare with.
* @param pu64Old Pointer store the old value at.
*/
#if (RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN) \
DECLASM(bool) ASMAtomicCmpXchgExU64(volatile uint64_t *pu64, const uint64_t u64New, const uint64_t u64Old, uint64_t *pu64Old);
#else
DECLINLINE(bool) ASMAtomicCmpXchgExU64(volatile uint64_t *pu64, const uint64_t u64New, const uint64_t u64Old, uint64_t *pu64Old)
{
# elif defined(RT_ARCH_AMD64)
"setz %1\n\t"
: "=m" (*pu64),
"=qm" (u8Ret),
"=a" (*pu64Old)
: "r" (u64New),
"a" (u64Old),
"m" (*pu64));
return (bool)u8Ret;
# else
bool fRet;
{
}
return fRet;
# endif
# else /* !RT_ARCH_AMD64 */
/* NB: this code uses a memory clobber description, because the clean
* solution with an output value for *pu64 makes gcc run out of registers.
* This will cause suboptimal code, and anyone with a better solution is
* welcome to improve this. */
"lock; cmpxchg8b %3\n\t"
"xchgl %%ebx, %1\n\t"
: "=A" (u64Ret)
"m" (*pu64),
"0" (u64Old)
: "memory" );
# else /* !PIC */
: "=A" (u64Ret),
"=m" (*pu64)
"m" (*pu64),
"0" (u64Old));
# endif
# else
{
}
return !!u32Ret;
# endif
# endif /* !RT_ARCH_AMD64 */
}
#endif
/**
* Atomically Compare and exchange a signed 64-bit value, additionally
* passing back old value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param pi64 Pointer to the 64-bit variable to update.
* @param i64 The 64-bit value to assign to *pu64.
* @param i64Old The value to compare with.
* @param pi64Old Pointer store the old value at.
*/
DECLINLINE(bool) ASMAtomicCmpXchgExS64(volatile int64_t *pi64, const int64_t i64, const int64_t i64Old, int64_t *pi64Old)
{
return ASMAtomicCmpXchgExU64((volatile uint64_t *)pi64, (uint64_t)i64, (uint64_t)i64Old, (uint64_t *)pi64Old);
}
/** @def ASMAtomicCmpXchgExHandle
* Atomically Compare and Exchange a typical IPRT handle value, ordered.
*
* @param ph Pointer to the value to update.
* @param hNew The new value to assigned to *pu.
* @param hOld The old value to *pu compare with.
* @param fRc Where to store the result.
* @param phOldVal Pointer to where to store the old value.
*
* @remarks This doesn't currently work for all handles (like RTFILE).
*/
#if HC_ARCH_BITS == 32
do { \
(fRc) = ASMAtomicCmpXchgExU32((volatile uint32_t *)(pu), (uint32_t)(uNew), (uint32_t)(uOld), (uint32_t *)(puOldVal)); \
} while (0)
do { \
(fRc) = ASMAtomicCmpXchgExU64((volatile uint64_t *)(pu), (uint64_t)(uNew), (uint64_t)(uOld), (uint64_t *)(puOldVal)); \
} while (0)
#else
#endif
/** @def ASMAtomicCmpXchgExSize
* Atomically Compare and Exchange a value which size might differ
* between platforms or compilers. Additionally passes back old value.
*
* @param pu Pointer to the value to update.
* @param uNew The new value to assigned to *pu.
* @param uOld The old value to *pu compare with.
* @param fRc Where to store the result.
* @param puOldVal Pointer to where to store the old value.
*/
do { \
switch (sizeof(*(pu))) { \
case 4: (fRc) = ASMAtomicCmpXchgExU32((volatile uint32_t *)(void *)(pu), (uint32_t)(uNew), (uint32_t)(uOld), (uint32_t *)(uOldVal)); \
break; \
case 8: (fRc) = ASMAtomicCmpXchgExU64((volatile uint64_t *)(void *)(pu), (uint64_t)(uNew), (uint64_t)(uOld), (uint64_t *)(uOldVal)); \
break; \
(fRc) = false; \
(uOldVal) = 0; \
break; \
} \
} while (0)
/**
* Atomically Compare and Exchange a pointer value, additionally
* passing back old value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param ppv Pointer to the value to update.
* @param pvNew The new value to assigned to *ppv.
* @param pvOld The old value to *ppv compare with.
* @param ppvOld Pointer store the old value at.
*/
DECLINLINE(bool) ASMAtomicCmpXchgExPtrVoid(void * volatile *ppv, const void *pvNew, const void *pvOld, void **ppvOld)
{
#if ARCH_BITS == 32
return ASMAtomicCmpXchgExU32((volatile uint32_t *)(void *)ppv, (uint32_t)pvNew, (uint32_t)pvOld, (uint32_t *)ppvOld);
return ASMAtomicCmpXchgExU64((volatile uint64_t *)(void *)ppv, (uint64_t)pvNew, (uint64_t)pvOld, (uint64_t *)ppvOld);
#else
# error "ARCH_BITS is bogus"
#endif
}
/**
* Atomically Compare and Exchange a pointer value, additionally
* passing back old value, ordered.
*
* @returns true if xchg was done.
* @returns false if xchg wasn't done.
*
* @param ppv Pointer to the value to update.
* @param pvNew The new value to assigned to *ppv.
* @param pvOld The old value to *ppv compare with.
* @param ppvOld Pointer store the old value at.
*
* @remarks This is relatively type safe on GCC platforms.
*/
#ifdef __GNUC__
({\
(void *)pvNewTypeChecked, (void *)pvOldTypeChecked, \
(void **)ppvOldTypeChecked); \
fMacroRet; \
})
#else
ASMAtomicCmpXchgExPtrVoid((void * volatile *)(ppv), (void *)(pvNew), (void *)(pvOld), (void **)(ppvOld))
#endif
/**
* Serialize Instruction.
*/
DECLASM(void) ASMSerializeInstruction(void);
#else
{
# ifdef RT_ARCH_AMD64
__asm__ ("cpuid"
: "=a" (xAX)
: "0" (xAX)
: "rbx", "rcx", "rdx");
__asm__ ("push %%ebx\n\t"
"cpuid\n\t"
"pop %%ebx\n\t"
: "=a" (xAX)
: "0" (xAX)
: "ecx", "edx");
# else
__asm__ ("cpuid"
: "=a" (xAX)
: "0" (xAX)
: "ebx", "ecx", "edx");
# endif
int aInfo[4];
# else
{
}
# endif
}
#endif
/**
* Memory fence, waits for any pending writes and reads to complete.
*/
{
/** @todo use mfence? check if all cpus we care for support it. */
ASMAtomicXchgU32(&u32, 0);
}
/**
* Write fence, waits for any pending writes to complete.
*/
{
/** @todo use sfence? check if all cpus we care for support it. */
}
/**
* Read fence, waits for any pending reads to complete.
*/
{
/** @todo use lfence? check if all cpus we care for support it. */
}
/**
* Atomically reads an unsigned 8-bit value, ordered.
*
* @returns Current *pu8 value
* @param pu8 Pointer to the 8-bit variable to read.
*/
{
return *pu8; /* byte reads are atomic on x86 */
}
/**
* Atomically reads an unsigned 8-bit value, unordered.
*
* @returns Current *pu8 value
* @param pu8 Pointer to the 8-bit variable to read.
*/
{
return *pu8; /* byte reads are atomic on x86 */
}
/**
* Atomically reads a signed 8-bit value, ordered.
*
* @returns Current *pi8 value
* @param pi8 Pointer to the 8-bit variable to read.
*/
{
return *pi8; /* byte reads are atomic on x86 */
}
/**
* Atomically reads a signed 8-bit value, unordered.
*
* @returns Current *pi8 value
* @param pi8 Pointer to the 8-bit variable to read.
*/
{
return *pi8; /* byte reads are atomic on x86 */
}
/**
* Atomically reads an unsigned 16-bit value, ordered.
*
* @returns Current *pu16 value
* @param pu16 Pointer to the 16-bit variable to read.
*/
{
return *pu16;
}
/**
* Atomically reads an unsigned 16-bit value, unordered.
*
* @returns Current *pu16 value
* @param pu16 Pointer to the 16-bit variable to read.
*/
{
return *pu16;
}
/**
* Atomically reads a signed 16-bit value, ordered.
*
* @returns Current *pi16 value
* @param pi16 Pointer to the 16-bit variable to read.
*/
{
return *pi16;
}
/**
* Atomically reads a signed 16-bit value, unordered.
*
* @returns Current *pi16 value
* @param pi16 Pointer to the 16-bit variable to read.
*/
{
return *pi16;
}
/**
* Atomically reads an unsigned 32-bit value, ordered.
*
* @returns Current *pu32 value
* @param pu32 Pointer to the 32-bit variable to read.
*/
{
return *pu32;
}
/**
* Atomically reads an unsigned 32-bit value, unordered.
*
* @returns Current *pu32 value
* @param pu32 Pointer to the 32-bit variable to read.
*/
{
return *pu32;
}
/**
* Atomically reads a signed 32-bit value, ordered.
*
* @returns Current *pi32 value
* @param pi32 Pointer to the 32-bit variable to read.
*/
{
return *pi32;
}
/**
* Atomically reads a signed 32-bit value, unordered.
*
* @returns Current *pi32 value
* @param pi32 Pointer to the 32-bit variable to read.
*/
{
return *pi32;
}
/**
* Atomically reads an unsigned 64-bit value, ordered.
*
* @returns Current *pu64 value
* @param pu64 Pointer to the 64-bit variable to read.
* The memory pointed to must be writable.
* @remark This will fault if the memory is read-only!
*/
#if (RT_INLINE_ASM_EXTERNAL && !defined(RT_ARCH_AMD64)) \
#else
{
# ifdef RT_ARCH_AMD64
/*# if RT_INLINE_ASM_GNU_STYLE
__asm__ __volatile__( "mfence\n\t"
"movq %1, %0\n\t"
: "=r" (u64)
: "m" (*pu64));
# else
__asm
{
mfence
mov rdx, [pu64]
mov rax, [rdx]
mov [u64], rax
}
# endif*/
# else /* !RT_ARCH_AMD64 */
"lock; cmpxchg8b (%5)\n\t"
"movl %3, %%ebx\n\t"
: "=A" (u64),
"+m" (*pu64)
# else
"=m" (*pu64)
# endif
: "0" (0ULL),
"m" (u32EBX),
"c" (0),
"S" (pu64));
# else /* !PIC */
: "=A" (u64),
"+m" (*pu64)
: "0" (0ULL),
"b" (0),
"c" (0));
# endif
# else
{
}
# endif
# endif /* !RT_ARCH_AMD64 */
return u64;
}
#endif
/**
* Atomically reads an unsigned 64-bit value, unordered.
*
* @returns Current *pu64 value
* @param pu64 Pointer to the 64-bit variable to read.
* The memory pointed to must be writable.
* @remark This will fault if the memory is read-only!
*/
#if !defined(RT_ARCH_AMD64) \
&& ( (RT_INLINE_ASM_EXTERNAL && !RT_INLINE_ASM_USES_INTRIN) \
#else
{
# ifdef RT_ARCH_AMD64
/*# if RT_INLINE_ASM_GNU_STYLE
Assert(!((uintptr_t)pu64 & 7));
__asm__ __volatile__("movq %1, %0\n\t"
: "=r" (u64)
: "m" (*pu64));
# else
__asm
{
mov rdx, [pu64]
mov rax, [rdx]
mov [u64], rax
}
# endif */
# else /* !RT_ARCH_AMD64 */
"xor %%ecx,%%ecx\n\t"
"xor %%edx,%%edx\n\t"
"xchgl %%ebx, %3\n\t"
"lock; cmpxchg8b (%4)\n\t"
"movl %3, %%ebx\n\t"
: "=A" (u64),
"+m" (*pu64),
# else
"=m" (*pu64),
# endif
"=c" (u32Spill)
: "m" (u32EBX),
"S" (pu64));
# else /* !PIC */
: "=A" (u64),
"+m" (*pu64)
: "0" (0ULL),
"b" (0),
"c" (0));
# endif
# else
{
}
# endif
# endif /* !RT_ARCH_AMD64 */
return u64;
}
#endif
/**
* Atomically reads a signed 64-bit value, ordered.
*
* @returns Current *pi64 value
* @param pi64 Pointer to the 64-bit variable to read.
* The memory pointed to must be writable.
* @remark This will fault if the memory is read-only!
*/
{
}
/**
* Atomically reads a signed 64-bit value, unordered.
*
* @returns Current *pi64 value
* @param pi64 Pointer to the 64-bit variable to read.
* The memory pointed to must be writable.
* @remark This will fault if the memory is read-only!
*/
{
}
/**
* Atomically reads a size_t value, ordered.
*
* @returns Current *pcb value
* @param pcb Pointer to the size_t variable to read.
*/
{
#if ARCH_BITS == 64
#else
# error "Unsupported ARCH_BITS value"
#endif
}
/**
* Atomically reads a size_t value, unordered.
*
* @returns Current *pcb value
* @param pcb Pointer to the size_t variable to read.
*/
{
#if ARCH_BITS == 64
#else
# error "Unsupported ARCH_BITS value"
#endif
}
/**
* Atomically reads a pointer value, ordered.
*
* @returns Current *pv value
* @param ppv Pointer to the pointer variable to read.
*
* @remarks Please use ASMAtomicReadPtrT, it provides better type safety and
* requires less typing (no casts).
*/
{
#if ARCH_BITS == 32
#else
# error "ARCH_BITS is bogus"
#endif
}
/**
* Convenience macro for avoiding the annoying casting with ASMAtomicReadPtr.
*
* @returns Current *pv value
* @param ppv Pointer to the pointer variable to read.
* @param Type The type of *ppv, sans volatile.
*/
#ifdef __GNUC__
({\
})
#else
#endif
/**
* Atomically reads a pointer value, unordered.
*
* @returns Current *pv value
* @param ppv Pointer to the pointer variable to read.
*
* @remarks Please use ASMAtomicUoReadPtrT, it provides better type safety and
* requires less typing (no casts).
*/
{
#if ARCH_BITS == 32
#else
# error "ARCH_BITS is bogus"
#endif
}
/**
* Convenience macro for avoiding the annoying casting with ASMAtomicUoReadPtr.
*
* @returns Current *pv value
* @param ppv Pointer to the pointer variable to read.
* @param Type The type of *ppv, sans volatile.
*/
#ifdef __GNUC__
({\
})
#else
#endif
/**
* Atomically reads a boolean value, ordered.
*
* @returns Current *pf value
* @param pf Pointer to the boolean variable to read.
*/
{
return *pf; /* byte reads are atomic on x86 */
}
/**
* Atomically reads a boolean value, unordered.
*
* @returns Current *pf value
* @param pf Pointer to the boolean variable to read.
*/
{
return *pf; /* byte reads are atomic on x86 */
}
/**
* Atomically read a typical IPRT handle value, ordered.
*
* @param ph Pointer to the handle variable to read.
* @param phRes Where to store the result.
*
* @remarks This doesn't currently work for all handles (like RTFILE).
*/
#if HC_ARCH_BITS == 32
do { \
} while (0)
do { \
} while (0)
#else
#endif
/**
* Atomically read a typical IPRT handle value, unordered.
*
* @param ph Pointer to the handle variable to read.
* @param phRes Where to store the result.
*
* @remarks This doesn't currently work for all handles (like RTFILE).
*/
#if HC_ARCH_BITS == 32
do { \
} while (0)
do { \
} while (0)
#else
#endif
/**
* Atomically read a value which size might differ
* between platforms or compilers, ordered.
*
* @param pu Pointer to the variable to read.
* @param puRes Where to store the result.
*/
do { \
switch (sizeof(*(pu))) { \
} \
} while (0)
/**
* Atomically read a value which size might differ
* between platforms or compilers, unordered.
*
* @param pu Pointer to the variable to read.
* @param puRes Where to store the result.
*/
do { \
switch (sizeof(*(pu))) { \
} \
} while (0)
/**
* Atomically writes an unsigned 8-bit value, ordered.
*
* @param pu8 Pointer to the 8-bit variable.
* @param u8 The 8-bit value to assign to *pu8.
*/
{
}
/**
* Atomically writes an unsigned 8-bit value, unordered.
*
* @param pu8 Pointer to the 8-bit variable.
* @param u8 The 8-bit value to assign to *pu8.
*/
{
}
/**
* Atomically writes a signed 8-bit value, ordered.
*
* @param pi8 Pointer to the 8-bit variable to read.
* @param i8 The 8-bit value to assign to *pi8.
*/
{
}
/**
* Atomically writes a signed 8-bit value, unordered.
*
* @param pi8 Pointer to the 8-bit variable to write.
* @param i8 The 8-bit value to assign to *pi8.
*/
{
}
/**
* Atomically writes an unsigned 16-bit value, ordered.
*
* @param pu16 Pointer to the 16-bit variable to write.
* @param u16 The 16-bit value to assign to *pu16.
*/
{
}
/**
* Atomically writes an unsigned 16-bit value, unordered.
*
* @param pu16 Pointer to the 16-bit variable to write.
* @param u16 The 16-bit value to assign to *pu16.
*/
{
}
/**
* Atomically writes a signed 16-bit value, ordered.
*
* @param pi16 Pointer to the 16-bit variable to write.
* @param i16 The 16-bit value to assign to *pi16.
*/
{
}
/**
* Atomically writes a signed 16-bit value, unordered.
*
* @param pi16 Pointer to the 16-bit variable to write.
* @param i16 The 16-bit value to assign to *pi16.
*/
{
}
/**
* Atomically writes an unsigned 32-bit value, ordered.
*
* @param pu32 Pointer to the 32-bit variable to write.
* @param u32 The 32-bit value to assign to *pu32.
*/
{
}
/**
* Atomically writes an unsigned 32-bit value, unordered.
*
* @param pu32 Pointer to the 32-bit variable to write.
* @param u32 The 32-bit value to assign to *pu32.
*/
{
}
/**
* Atomically writes a signed 32-bit value, ordered.
*
* @param pi32 Pointer to the 32-bit variable to write.
* @param i32 The 32-bit value to assign to *pi32.
*/
{
}
/**
* Atomically writes a signed 32-bit value, unordered.
*
* @param pi32 Pointer to the 32-bit variable to write.
* @param i32 The 32-bit value to assign to *pi32.
*/
{
}
/**
* Atomically writes an unsigned 64-bit value, ordered.
*
* @param pu64 Pointer to the 64-bit variable to write.
* @param u64 The 64-bit value to assign to *pu64.
*/
{
}
/**
* Atomically writes an unsigned 64-bit value, unordered.
*
* @param pu64 Pointer to the 64-bit variable to write.
* @param u64 The 64-bit value to assign to *pu64.
*/
{
#if ARCH_BITS == 64
#else
#endif
}
/**
* Atomically writes a signed 64-bit value, ordered.
*
* @param pi64 Pointer to the 64-bit variable to write.
* @param i64 The 64-bit value to assign to *pi64.
*/
{
}
/**
* Atomically writes a signed 64-bit value, unordered.
*
* @param pi64 Pointer to the 64-bit variable to write.
* @param i64 The 64-bit value to assign to *pi64.
*/
{
#if ARCH_BITS == 64
#else
#endif
}
/**
* Atomically writes a boolean value, unordered.
*
* @param pf Pointer to the boolean variable to write.
* @param f The boolean value to assign to *pf.
*/
{
}
/**
* Atomically writes a boolean value, unordered.
*
* @param pf Pointer to the boolean variable to write.
* @param f The boolean value to assign to *pf.
*/
{
*pf = f; /* byte writes are atomic on x86 */
}
/**
* Atomically writes a pointer value, ordered.
*
* @param ppv Pointer to the pointer variable to write.
* @param pv The pointer value to assign to *ppv.
*/
{
#if ARCH_BITS == 32
#else
# error "ARCH_BITS is bogus"
#endif
}
/**
* Atomically writes a pointer value, ordered.
*
* @param ppv Pointer to the pointer variable to write.
* @param pv The pointer value to assign to *ppv. If NULL use
* ASMAtomicWriteNullPtr or you'll land in trouble.
*
* @remarks This is relatively type safe on GCC platforms when @a pv isn't
* NULL.
*/
#ifdef __GNUC__
do \
{ \
\
AssertCompile(sizeof(*ppv) == sizeof(void *)); \
AssertCompile(sizeof(pv) == sizeof(void *)); \
\
} while (0)
#else
do \
{ \
AssertCompile(sizeof(*ppv) == sizeof(void *)); \
AssertCompile(sizeof(pv) == sizeof(void *)); \
\
} while (0)
#endif
/**
* Atomically sets a pointer to NULL, ordered.
*
* @param ppv Pointer to the pointer variable that should be set to NULL.
*
* @remarks This is relatively type safe on GCC platforms.
*/
#ifdef __GNUC__
do \
{ \
AssertCompile(sizeof(*ppv) == sizeof(void *)); \
} while (0)
#else
do \
{ \
AssertCompile(sizeof(*ppv) == sizeof(void *)); \
} while (0)
#endif
/**
* Atomically writes a pointer value, unordered.
*
* @returns Current *pv value
* @param ppv Pointer to the pointer variable.
* @param pv The pointer value to assign to *ppv. If NULL use
* ASMAtomicUoWriteNullPtr or you'll land in trouble.
*
* @remarks This is relatively type safe on GCC platforms when @a pv isn't
* NULL.
*/
#ifdef __GNUC__
do \
{ \
\
AssertCompile(sizeof(*ppv) == sizeof(void *)); \
AssertCompile(sizeof(pv) == sizeof(void *)); \
\
*(ppvTypeChecked) = pvTypeChecked; \
} while (0)
#else
do \
{ \
AssertCompile(sizeof(*ppv) == sizeof(void *)); \
AssertCompile(sizeof(pv) == sizeof(void *)); \
} while (0)
#endif
/**
* Atomically sets a pointer to NULL, unordered.
*
* @param ppv Pointer to the pointer variable that should be set to NULL.
*
* @remarks This is relatively type safe on GCC platforms.
*/
#ifdef __GNUC__
do \
{ \
AssertCompile(sizeof(*ppv) == sizeof(void *)); \
*(ppvTypeChecked) = NULL; \
} while (0)
#else
do \
{ \
AssertCompile(sizeof(*ppv) == sizeof(void *)); \
} while (0)
#endif
/**
* Atomically write a typical IPRT handle value, ordered.
*
* @param ph Pointer to the variable to update.
* @param hNew The value to assign to *ph.
*
* @remarks This doesn't currently work for all handles (like RTFILE).
*/
#if HC_ARCH_BITS == 32
do { \
} while (0)
do { \
} while (0)
#else
#endif
/**
* Atomically write a typical IPRT handle value, unordered.
*
* @param ph Pointer to the variable to update.
* @param hNew The value to assign to *ph.
*
* @remarks This doesn't currently work for all handles (like RTFILE).
*/
#if HC_ARCH_BITS == 32
do { \
} while (0)
do { \
} while (0)
#else
#endif
/**
* Atomically write a value which size might differ
* between platforms or compilers, ordered.
*
* @param pu Pointer to the variable to update.
* @param uNew The value to assign to *pu.
*/
do { \
switch (sizeof(*(pu))) { \
} \
} while (0)
/**
* Atomically write a value which size might differ
* between platforms or compilers, unordered.
*
* @param pu Pointer to the variable to update.
* @param uNew The value to assign to *pu.
*/
do { \
switch (sizeof(*(pu))) { \
} \
} while (0)
/**
* Atomically exchanges and adds to a 32-bit value, ordered.
*
* @returns The old value.
* @param pu32 Pointer to the value.
* @param u32 Number to add.
*/
#else
{
return u32;
: "=r" (u32),
"=m" (*pu32)
: "0" (u32),
"m" (*pu32)
: "memory");
return u32;
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
return u32;
# endif
}
#endif
/**
* Atomically exchanges and adds to a signed 32-bit value, ordered.
*
* @returns The old value.
* @param pi32 Pointer to the value.
* @param i32 Number to add.
*/
{
}
/**
* Atomically exchanges and adds to a 64-bit value, ordered.
*
* @returns The old value.
* @param pu64 Pointer to the value.
* @param u64 Number to add.
*/
#else
{
# if RT_INLINE_ASM_USES_INTRIN && defined(RT_ARCH_AMD64)
return u64;
: "=r" (u64),
"=m" (*pu64)
: "0" (u64),
"m" (*pu64)
: "memory");
return u64;
# else
for (;;)
{
break;
ASMNopPause();
}
return u64Old;
# endif
}
#endif
/**
* Atomically exchanges and adds to a signed 64-bit value, ordered.
*
* @returns The old value.
* @param pi64 Pointer to the value.
* @param i64 Number to add.
*/
{
}
/**
* Atomically exchanges and adds to a size_t value, ordered.
*
* @returns The old value.
* @param pcb Pointer to the size_t value.
* @param cb Number to add.
*/
{
#if ARCH_BITS == 64
#else
# error "Unsupported ARCH_BITS value"
#endif
}
/**
* Atomically exchanges and adds a value which size might differ between
* platforms or compilers, ordered.
*
* @param pu Pointer to the variable to update.
* @param uNew The value to add to *pu.
* @param puOld Where to store the old value.
*/
do { \
switch (sizeof(*(pu))) { \
case 4: *(uint32_t *)(puOld) = ASMAtomicAddU32((volatile uint32_t *)(void *)(pu), (uint32_t)(uNew)); break; \
case 8: *(uint64_t *)(puOld) = ASMAtomicAddU64((volatile uint64_t *)(void *)(pu), (uint64_t)(uNew)); break; \
} \
} while (0)
/**
* Atomically exchanges and subtracts to an unsigned 32-bit value, ordered.
*
* @returns The old value.
* @param pu32 Pointer to the value.
* @param u32 Number to subtract.
*/
{
}
/**
* Atomically exchanges and subtracts to a signed 32-bit value, ordered.
*
* @returns The old value.
* @param pi32 Pointer to the value.
* @param i32 Number to subtract.
*/
{
}
/**
* Atomically exchanges and subtracts to an unsigned 64-bit value, ordered.
*
* @returns The old value.
* @param pu64 Pointer to the value.
* @param u64 Number to subtract.
*/
{
}
/**
* Atomically exchanges and subtracts to a signed 64-bit value, ordered.
*
* @returns The old value.
* @param pi64 Pointer to the value.
* @param i64 Number to subtract.
*/
{
}
/**
* Atomically exchanges and subtracts to a size_t value, ordered.
*
* @returns The old value.
* @param pcb Pointer to the size_t value.
* @param cb Number to subtract.
*/
{
#if ARCH_BITS == 64
#else
# error "Unsupported ARCH_BITS value"
#endif
}
/**
* Atomically exchanges and subtracts a value which size might differ between
* platforms or compilers, ordered.
*
* @param pu Pointer to the variable to update.
* @param uNew The value to subtract to *pu.
* @param puOld Where to store the old value.
*/
do { \
switch (sizeof(*(pu))) { \
case 4: *(uint32_t *)(puOld) = ASMAtomicSubU32((volatile uint32_t *)(void *)(pu), (uint32_t)(uNew)); break; \
case 8: *(uint64_t *)(puOld) = ASMAtomicSubU64((volatile uint64_t *)(void *)(pu), (uint64_t)(uNew)); break; \
} \
} while (0)
/**
* Atomically increment a 32-bit value, ordered.
*
* @returns The new value.
* @param pu32 Pointer to the value to increment.
*/
#else
{
return u32;
: "=r" (u32),
"=m" (*pu32)
: "0" (1),
"m" (*pu32)
: "memory");
return u32+1;
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
return u32+1;
# endif
}
#endif
/**
* Atomically increment a signed 32-bit value, ordered.
*
* @returns The new value.
* @param pi32 Pointer to the value to increment.
*/
{
}
/**
* Atomically increment a 64-bit value, ordered.
*
* @returns The new value.
* @param pu64 Pointer to the value to increment.
*/
#else
{
# if RT_INLINE_ASM_USES_INTRIN && defined(RT_ARCH_AMD64)
return u64;
: "=r" (u64),
"=m" (*pu64)
: "0" (1),
"m" (*pu64)
: "memory");
return u64 + 1;
# else
# endif
}
#endif
/**
* Atomically increment a signed 64-bit value, ordered.
*
* @returns The new value.
* @param pi64 Pointer to the value to increment.
*/
{
}
/**
* Atomically increment a size_t value, ordered.
*
* @returns The new value.
* @param pcb Pointer to the value to increment.
*/
{
#if ARCH_BITS == 64
#else
# error "Unsupported ARCH_BITS value"
#endif
}
/**
* Atomically decrement an unsigned 32-bit value, ordered.
*
* @returns The new value.
* @param pu32 Pointer to the value to decrement.
*/
#else
{
return u32;
: "=r" (u32),
"=m" (*pu32)
: "0" (-1),
"m" (*pu32)
: "memory");
return u32-1;
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
return u32-1;
# endif
}
#endif
/**
* Atomically decrement a signed 32-bit value, ordered.
*
* @returns The new value.
* @param pi32 Pointer to the value to decrement.
*/
{
}
/**
* Atomically decrement an unsigned 64-bit value, ordered.
*
* @returns The new value.
* @param pu64 Pointer to the value to decrement.
*/
#else
{
# if RT_INLINE_ASM_USES_INTRIN && defined(RT_ARCH_AMD64)
return u64;
: "=r" (u64),
"=m" (*pu64)
: "0" (~(uint64_t)0),
"m" (*pu64)
: "memory");
return u64-1;
# else
# endif
}
#endif
/**
* Atomically decrement a signed 64-bit value, ordered.
*
* @returns The new value.
* @param pi64 Pointer to the value to decrement.
*/
{
}
/**
* Atomically decrement a size_t value, ordered.
*
* @returns The new value.
* @param pcb Pointer to the value to decrement.
*/
{
#if ARCH_BITS == 64
#else
# error "Unsupported ARCH_BITS value"
#endif
}
/**
* Atomically Or an unsigned 32-bit value, ordered.
*
* @param pu32 Pointer to the pointer variable to OR u32 with.
* @param u32 The value to OR *pu32 with.
*/
#else
{
: "=m" (*pu32)
: "ir" (u32),
"m" (*pu32));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Atomically Or a signed 32-bit value, ordered.
*
* @param pi32 Pointer to the pointer variable to OR u32 with.
* @param i32 The value to OR *pu32 with.
*/
{
}
/**
* Atomically Or an unsigned 64-bit value, ordered.
*
* @param pu64 Pointer to the pointer variable to OR u64 with.
* @param u64 The value to OR *pu64 with.
*/
#else
{
# if RT_INLINE_ASM_USES_INTRIN && defined(RT_ARCH_AMD64)
: "=m" (*pu64)
: "r" (u64),
"m" (*pu64));
# else
for (;;)
{
break;
ASMNopPause();
}
# endif
}
#endif
/**
* Atomically Or a signed 64-bit value, ordered.
*
* @param pi64 Pointer to the pointer variable to OR u64 with.
* @param i64 The value to OR *pu64 with.
*/
{
}
/**
* Atomically And an unsigned 32-bit value, ordered.
*
* @param pu32 Pointer to the pointer variable to AND u32 with.
* @param u32 The value to AND *pu32 with.
*/
#else
{
: "=m" (*pu32)
: "ir" (u32),
"m" (*pu32));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Atomically And a signed 32-bit value, ordered.
*
* @param pi32 Pointer to the pointer variable to AND i32 with.
* @param i32 The value to AND *pi32 with.
*/
{
}
/**
* Atomically And an unsigned 64-bit value, ordered.
*
* @param pu64 Pointer to the pointer variable to AND u64 with.
* @param u64 The value to AND *pu64 with.
*/
#else
{
# if RT_INLINE_ASM_USES_INTRIN && defined(RT_ARCH_AMD64)
: "=m" (*pu64)
: "r" (u64),
"m" (*pu64));
# else
for (;;)
{
break;
ASMNopPause();
}
# endif
}
#endif
/**
* Atomically And a signed 64-bit value, ordered.
*
* @param pi64 Pointer to the pointer variable to AND i64 with.
* @param i64 The value to AND *pi64 with.
*/
{
}
/**
* Atomically OR an unsigned 32-bit value, unordered but interrupt safe.
*
* @param pu32 Pointer to the pointer variable to OR u32 with.
* @param u32 The value to OR *pu32 with.
*/
#else
{
: "=m" (*pu32)
: "ir" (u32),
"m" (*pu32));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Atomically OR a signed 32-bit value, unordered.
*
* @param pi32 Pointer to the pointer variable to OR u32 with.
* @param i32 The value to OR *pu32 with.
*/
{
}
/**
* Atomically OR an unsigned 64-bit value, unordered.
*
* @param pu64 Pointer to the pointer variable to OR u64 with.
* @param u64 The value to OR *pu64 with.
*/
#else
{
# if RT_INLINE_ASM_GNU_STYLE && defined(RT_ARCH_AMD64)
: "=m" (*pu64)
: "r" (u64),
"m" (*pu64));
# else
for (;;)
{
break;
ASMNopPause();
}
# endif
}
#endif
/**
* Atomically Or a signed 64-bit value, unordered.
*
* @param pi64 Pointer to the pointer variable to OR u64 with.
* @param i64 The value to OR *pu64 with.
*/
{
}
/**
* Atomically And an unsigned 32-bit value, unordered.
*
* @param pu32 Pointer to the pointer variable to AND u32 with.
* @param u32 The value to AND *pu32 with.
*/
#else
{
: "=m" (*pu32)
: "ir" (u32),
"m" (*pu32));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Atomically And a signed 32-bit value, unordered.
*
* @param pi32 Pointer to the pointer variable to AND i32 with.
* @param i32 The value to AND *pi32 with.
*/
{
}
/**
* Atomically And an unsigned 64-bit value, unordered.
*
* @param pu64 Pointer to the pointer variable to AND u64 with.
* @param u64 The value to AND *pu64 with.
*/
#else
{
# if RT_INLINE_ASM_GNU_STYLE && defined(RT_ARCH_AMD64)
: "=m" (*pu64)
: "r" (u64),
"m" (*pu64));
# else
for (;;)
{
break;
ASMNopPause();
}
# endif
}
#endif
/**
* Atomically And a signed 64-bit value, unordered.
*
* @param pi64 Pointer to the pointer variable to AND i64 with.
* @param i64 The value to AND *pi64 with.
*/
{
}
/**
* Atomically increment an unsigned 32-bit value, unordered.
*
* @returns the new value.
* @param pu32 Pointer to the variable to increment.
*/
#else
{
: "=r" (u32),
"=m" (*pu32)
: "0" (1),
"m" (*pu32)
: "memory");
return u32 + 1;
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
return u32 + 1;
# endif
}
#endif
/**
* Atomically decrement an unsigned 32-bit value, unordered.
*
* @returns the new value.
* @param pu32 Pointer to the variable to decrement.
*/
#else
{
: "=r" (u32),
"=m" (*pu32)
: "0" (-1),
"m" (*pu32)
: "memory");
return u32 - 1;
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
return u32 - 1;
# endif
}
#endif
/** @def RT_ASM_PAGE_SIZE
* @internal
*/
#if defined(RT_ARCH_SPARC64)
# if defined(PAGE_SIZE) && !defined(NT_INCLUDED)
# if PAGE_SIZE != 0x2000
# error "PAGE_SIZE is not 0x2000!"
# endif
# endif
#else
# if defined(PAGE_SIZE) && !defined(NT_INCLUDED)
# if PAGE_SIZE != 0x1000
# error "PAGE_SIZE is not 0x1000!"
# endif
# endif
#endif
/**
* Zeros a 4K memory page.
*
* @param pv Pointer to the memory block. This must be page aligned.
*/
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
# ifdef RT_ARCH_AMD64
: "=D" (pv),
"=c" (uDummy)
: "0" (pv),
"a" (0)
: "memory");
# else
: "=D" (pv),
"=c" (uDummy)
: "0" (pv),
"a" (0)
: "memory");
# endif
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
# endif
/**
* Zeros a memory block with a 32-bit aligned size.
*
* @param pv Pointer to the memory block.
* @param cb Number of bytes in the block. This MUST be aligned on 32-bit!
*/
#else
{
# ifdef RT_ARCH_AMD64
if (!(cb & 7))
else
# endif
: "=D" (pv),
"=c" (cb)
: "0" (pv),
"a" (0)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Fills a memory block with a 32-bit aligned size.
*
* @param pv Pointer to the memory block.
* @param cb Number of bytes in the block. This MUST be aligned on 32-bit!
* @param u32 The value to fill with.
*/
#else
{
# ifdef RT_ARCH_AMD64
if (!(cb & 7))
else
# endif
: "=D" (pv),
"=c" (cb)
: "0" (pv),
"a" (u32)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Checks if a memory page is all zeros.
*
* @returns true / false.
*
* @param pvPage Pointer to the page. Must be aligned on 16 byte
* boundary
*/
{
# if 0 /*RT_INLINE_ASM_GNU_STYLE - this is actually slower... */
union { RTCCUINTREG r; bool f; } uAX;
# ifdef RT_ARCH_AMD64
"scasq\n\t"
# else
"scasl\n\t"
# endif
"setnc %%al\n\t"
: "=&c" (xCX),
"=&D" (xDI),
"=&a" (uAX.r)
: "mr" (pvPage),
# ifdef RT_ARCH_AMD64
# else
# endif
"1" (pvPage),
"2" (0));
return uAX.f;
# else
for (;;)
{
if (puPtr[0]) return false;
if (puPtr[4]) return false;
if (puPtr[2]) return false;
if (puPtr[6]) return false;
if (puPtr[1]) return false;
if (puPtr[5]) return false;
if (puPtr[3]) return false;
if (puPtr[7]) return false;
if (!--cLeft)
return true;
puPtr += 8;
}
return true;
# endif
}
/**
* Checks if a memory block is filled with the specified byte.
*
* This is a sort of inverted memchr.
*
* @returns Pointer to the byte which doesn't equal u8.
* @returns NULL if all equal to u8.
*
* @param pv Pointer to the memory block.
* @param cb Number of bytes in the block. This MUST be aligned on 32-bit!
* @param u8 The value it's supposed to be filled with.
*
* @todo Fix name, it is a predicate function but it's not returning boolean!
*/
{
/** @todo rewrite this in inline assembly? */
return (void *)pb;
return NULL;
}
/**
* Checks if a memory block is filled with the specified 32-bit value.
*
* This is a sort of inverted memchr.
*
* @returns Pointer to the first value which doesn't equal u32.
* @returns NULL if all equal to u32.
*
* @param pv Pointer to the memory block.
* @param cb Number of bytes in the block. This MUST be aligned on 32-bit!
* @param u32 The value it's supposed to be filled with.
*
* @todo Fix name, it is a predicate function but it's not returning boolean!
*/
{
/** @todo rewrite this in inline assembly? */
return NULL;
}
/**
* Probes a byte pointer for read access.
*
* While the function will not fault if the byte is not read accessible,
* the idea is to do this in a safe place like before acquiring locks
* and such like.
*
* Also, this functions guarantees that an eager compiler is not going
* to optimize the probing away.
*
* @param pvByte Pointer to the byte.
*/
#else
{
/** @todo verify that the compiler actually doesn't optimize this away. (intel & gcc) */
: "=r" (u8)
: "r" (pvByte));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return u8;
}
#endif
/**
* Probes a buffer for read access page by page.
*
* While the function will fault if the buffer is not fully read
* accessible, the idea is to do this in a safe place like before
* acquiring locks and such like.
*
* Also, this functions guarantees that an eager compiler is not going
* to optimize the probing away.
*
* @param pvBuf Pointer to the buffer.
* @param cbBuf The size of the buffer in bytes. Must be >= 1.
*/
{
/** @todo verify that the compiler actually doesn't optimize this away. (intel & gcc) */
/* the first byte */
/* the pages in between pages. */
while (cbBuf > RT_ASM_PAGE_SIZE)
{
pu8 += RT_ASM_PAGE_SIZE;
}
/* the last byte */
}
/** @defgroup grp_inline_bits Bit Operations
* @{
*/
/**
* Sets a bit in a bitmap.
*
* @param pvBitmap Pointer to the bitmap. This should be 32-bit aligned.
* @param iBit The bit to set.
*
* @remarks The 32-bit aligning of pvBitmap is not a strict requirement.
* However, doing so will yield better performance as well as avoiding
* traps accessing the last bits in the bitmap.
*/
#else
{
: "=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Atomically sets a bit in a bitmap, ordered.
*
* @param pvBitmap Pointer to the bitmap. Must be 32-bit aligned, otherwise
* the memory access isn't atomic!
* @param iBit The bit to set.
*/
#else
{
: "=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Clears a bit in a bitmap.
*
* @param pvBitmap Pointer to the bitmap.
* @param iBit The bit to clear.
*
* @remarks The 32-bit aligning of pvBitmap is not a strict requirement.
* However, doing so will yield better performance as well as avoiding
* traps accessing the last bits in the bitmap.
*/
#else
{
: "=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Atomically clears a bit in a bitmap, ordered.
*
* @param pvBitmap Pointer to the bitmap. Must be 32-bit aligned, otherwise
* the memory access isn't atomic!
* @param iBit The bit to toggle set.
* @remarks No memory barrier, take care on smp.
*/
#else
{
: "=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Toggles a bit in a bitmap.
*
* @param pvBitmap Pointer to the bitmap.
* @param iBit The bit to toggle.
*
* @remarks The 32-bit aligning of pvBitmap is not a strict requirement.
* However, doing so will yield better performance as well as avoiding
* traps accessing the last bits in the bitmap.
*/
#else
{
: "=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Atomically toggles a bit in a bitmap, ordered.
*
* @param pvBitmap Pointer to the bitmap. Must be 32-bit aligned, otherwise
* the memory access isn't atomic!
* @param iBit The bit to test and set.
*/
#else
{
: "=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
}
#endif
/**
* Tests and sets a bit in a bitmap.
*
* @returns true if the bit was set.
* @returns false if the bit was clear.
*
* @param pvBitmap Pointer to the bitmap.
* @param iBit The bit to test and set.
*
* @remarks The 32-bit aligning of pvBitmap is not a strict requirement.
* However, doing so will yield better performance as well as avoiding
* traps accessing the last bits in the bitmap.
*/
#else
{
"setc %b0\n\t"
"andl $1, %0\n\t"
"=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return rc.f;
}
#endif
/**
* Atomically tests and sets a bit in a bitmap, ordered.
*
* @returns true if the bit was set.
* @returns false if the bit was clear.
*
* @param pvBitmap Pointer to the bitmap. Must be 32-bit aligned, otherwise
* the memory access isn't atomic!
* @param iBit The bit to set.
*/
#else
{
"setc %b0\n\t"
"andl $1, %0\n\t"
"=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return rc.f;
}
#endif
/**
* Tests and clears a bit in a bitmap.
*
* @returns true if the bit was set.
* @returns false if the bit was clear.
*
* @param pvBitmap Pointer to the bitmap.
* @param iBit The bit to test and clear.
*
* @remarks The 32-bit aligning of pvBitmap is not a strict requirement.
* However, doing so will yield better performance as well as avoiding
* traps accessing the last bits in the bitmap.
*/
#else
{
"setc %b0\n\t"
"andl $1, %0\n\t"
"=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return rc.f;
}
#endif
/**
* Atomically tests and clears a bit in a bitmap, ordered.
*
* @returns true if the bit was set.
* @returns false if the bit was clear.
*
* @param pvBitmap Pointer to the bitmap. Must be 32-bit aligned, otherwise
* the memory access isn't atomic!
* @param iBit The bit to test and clear.
*
* @remarks No memory barrier, take care on smp.
*/
#else
{
"setc %b0\n\t"
"andl $1, %0\n\t"
"=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return rc.f;
}
#endif
/**
* Tests and toggles a bit in a bitmap.
*
* @returns true if the bit was set.
* @returns false if the bit was clear.
*
* @param pvBitmap Pointer to the bitmap.
* @param iBit The bit to test and toggle.
*
* @remarks The 32-bit aligning of pvBitmap is not a strict requirement.
* However, doing so will yield better performance as well as avoiding
* traps accessing the last bits in the bitmap.
*/
#else
{
"setc %b0\n\t"
"andl $1, %0\n\t"
"=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return rc.f;
}
#endif
/**
* Atomically tests and toggles a bit in a bitmap, ordered.
*
* @returns true if the bit was set.
* @returns false if the bit was clear.
*
* @param pvBitmap Pointer to the bitmap. Must be 32-bit aligned, otherwise
* the memory access isn't atomic!
* @param iBit The bit to test and toggle.
*/
#else
{
"setc %b0\n\t"
"andl $1, %0\n\t"
"=m" (*(volatile long *)pvBitmap)
: "Ir" (iBit),
"m" (*(volatile long *)pvBitmap)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return rc.f;
}
#endif
/**
* Tests if a bit in a bitmap is set.
*
* @returns true if the bit is set.
* @returns false if the bit is clear.
*
* @param pvBitmap Pointer to the bitmap.
* @param iBit The bit to test.
*
* @remarks The 32-bit aligning of pvBitmap is not a strict requirement.
* However, doing so will yield better performance as well as avoiding
* traps accessing the last bits in the bitmap.
*/
#else
{
"setc %b0\n\t"
"andl $1, %0\n\t"
: "m" (*(const volatile long *)pvBitmap),
"Ir" (iBit)
: "memory");
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
}
# endif
return rc.f;
}
#endif
/**
* Clears a bit range within a bitmap.
*
* @param pvBitmap Pointer to the bitmap.
* @param iBitStart The First bit to clear.
* @param iBitEnd The first bit not to clear.
*/
{
{
else
{
/* bits in first dword. */
if (iBitStart & 31)
{
pu32++;
}
/* whole dword. */
/* bits in last dword. */
if (iBitEnd & 31)
{
}
}
}
}
/**
* Sets a bit range within a bitmap.
*
* @param pvBitmap Pointer to the bitmap.
* @param iBitStart The First bit to set.
* @param iBitEnd The first bit not to set.
*/
{
{
else
{
/* bits in first dword. */
if (iBitStart & 31)
{
pu32++;
}
/* whole dword. */
/* bits in last dword. */
if (iBitEnd & 31)
{
}
}
}
}
/**
* Finds the first clear bit in a bitmap.
*
* @returns Index of the first zero bit.
* @returns -1 if no clear bit was found.
* @param pvBitmap Pointer to the bitmap.
* @param cBits The number of bits in the bitmap. Multiple of 32.
*/
#else
{
if (cBits)
{
"je 1f\n\t"
# ifdef RT_ARCH_AMD64
"lea -4(%%rdi), %%rdi\n\t"
"xorl (%%rdi), %%eax\n\t"
"subq %5, %%rdi\n\t"
# else
"lea -4(%%edi), %%edi\n\t"
"xorl (%%edi), %%eax\n\t"
"subl %5, %%edi\n\t"
# endif
"shll $3, %%edi\n\t"
"bsfl %%eax, %%edx\n\t"
"addl %%edi, %%edx\n\t"
"1:\t\n"
: "=d" (iBit),
"=&c" (uECX),
"=&D" (uEDI),
"=&a" (uEAX)
: "0" (0xffffffff),
"mr" (pvBitmap),
"2" (pvBitmap),
"3" (0xffffffff));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
# ifdef RT_ARCH_AMD64
# else
# endif
done:
}
# endif
return iBit;
}
return -1;
}
#endif
/**
* Finds the next clear bit in a bitmap.
*
* @returns Index of the first zero bit.
* @returns -1 if no clear bit was found.
* @param pvBitmap Pointer to the bitmap.
* @param cBits The number of bits in the bitmap. Multiple of 32.
* @param iBitPrev The bit returned from the last search.
* The search will start at iBitPrev + 1.
*/
#else
{
if (iBit)
{
/*
* Inspect the 32-bit word containing the unaligned bit.
*/
unsigned long ulBit = 0;
# else
"jnz 1f\n\t"
"movl $-1, %0\n\t"
"1:\n\t"
: "=r" (iBit)
: "r" (u32));
# else
{
done:
}
# endif
if (iBit >= 0)
# endif
/*
* Skip ahead and see if there is anything left to search.
*/
iBitPrev |= 31;
iBitPrev++;
return -1;
}
/*
* 32-bit aligned search, let ASMBitFirstClear do the dirty work.
*/
if (iBit >= 0)
return iBit;
}
#endif
/**
* Finds the first set bit in a bitmap.
*
* @returns Index of the first set bit.
* @returns -1 if no clear bit was found.
* @param pvBitmap Pointer to the bitmap.
* @param cBits The number of bits in the bitmap. Multiple of 32.
*/
#else
{
if (cBits)
{
"je 1f\n\t"
# ifdef RT_ARCH_AMD64
"lea -4(%%rdi), %%rdi\n\t"
"movl (%%rdi), %%eax\n\t"
"subq %5, %%rdi\n\t"
# else
"lea -4(%%edi), %%edi\n\t"
"movl (%%edi), %%eax\n\t"
"subl %5, %%edi\n\t"
# endif
"shll $3, %%edi\n\t"
"bsfl %%eax, %%edx\n\t"
"addl %%edi, %%edx\n\t"
"1:\t\n"
: "=d" (iBit),
"=&c" (uECX),
"=&D" (uEDI),
"=&a" (uEAX)
: "0" (0xffffffff),
"mr" (pvBitmap),
"2" (pvBitmap),
"3" (0));
# else
{
# ifdef RT_ARCH_AMD64
# else
# endif
# ifdef RT_ARCH_AMD64
# else
# endif
done:
}
# endif
return iBit;
}
return -1;
}
#endif
/**
* Finds the next set bit in a bitmap.
*
* @returns Index of the next set bit.
* @returns -1 if no set bit was found.
* @param pvBitmap Pointer to the bitmap.
* @param cBits The number of bits in the bitmap. Multiple of 32.
* @param iBitPrev The bit returned from the last search.
* The search will start at iBitPrev + 1.
*/
#else
{
if (iBit)
{
/*
* Inspect the 32-bit word containing the unaligned bit.
*/
unsigned long ulBit = 0;
# else
"jnz 1f\n\t"
"movl $-1, %0\n\t"
"1:\n\t"
: "=r" (iBit)
: "r" (u32));
# else
{
done:
}
# endif
if (iBit >= 0)
# endif
/*
* Skip ahead and see if there is anything left to search.
*/
iBitPrev |= 31;
iBitPrev++;
return -1;
}
/*
* 32-bit aligned search, let ASMBitFirstClear do the dirty work.
*/
if (iBit >= 0)
return iBit;
}
#endif
/**
* Finds the first bit which is set in the given 32-bit integer.
* Bits are numbered from 1 (least significant) to 32.
*
* @returns index [1..32] of the first set bit.
* @returns 0 if all bits are cleared.
* @param u32 Integer to search for set bits.
* @remark Similar to ffs() in BSD.
*/
#else
{
unsigned long iBit;
iBit++;
else
iBit = 0;
"jnz 1f\n\t"
"xorl %0, %0\n\t"
"jmp 2f\n"
"1:\n\t"
"incl %0\n"
"2:\n\t"
: "=r" (iBit)
: "rm" (u32));
# else
{
done:
}
# endif
return iBit;
}
#endif
/**
* Finds the first bit which is set in the given 32-bit integer.
* Bits are numbered from 1 (least significant) to 32.
*
* @returns index [1..32] of the first set bit.
* @returns 0 if all bits are cleared.
* @param i32 Integer to search for set bits.
* @remark Similar to ffs() in BSD.
*/
{
}
/**
* Finds the last bit which is set in the given 32-bit integer.
* Bits are numbered from 1 (least significant) to 32.
*
* @returns index [1..32] of the last set bit.
* @returns 0 if all bits are cleared.
* @param u32 Integer to search for set bits.
* @remark Similar to fls() in BSD.
*/
#else
{
unsigned long iBit;
iBit++;
else
iBit = 0;
"jnz 1f\n\t"
"xorl %0, %0\n\t"
"jmp 2f\n"
"1:\n\t"
"incl %0\n"
"2:\n\t"
: "=r" (iBit)
: "rm" (u32));
# else
{
done:
}
# endif
return iBit;
}
#endif
/**
* Finds the last bit which is set in the given 32-bit integer.
* Bits are numbered from 1 (least significant) to 32.
*
* @returns index [1..32] of the last set bit.
* @returns 0 if all bits are cleared.
* @param i32 Integer to search for set bits.
* @remark Similar to fls() in BSD.
*/
{
}
/**
* Reverse the byte order of the given 16-bit integer.
*
* @returns Revert
* @param u16 16-bit integer value.
*/
#else
{
# else
{
}
# endif
return u16;
}
#endif
/**
* Reverse the byte order of the given 32-bit integer.
*
* @returns Revert
* @param u32 32-bit integer value.
*/
#else
{
# else
{
}
# endif
return u32;
}
#endif
/**
* Reverse the byte order of the given 64-bit integer.
*
* @returns Revert
* @param u64 64-bit integer value.
*/
{
#if defined(RT_ARCH_AMD64) && RT_INLINE_ASM_USES_INTRIN
#else
#endif
return u64;
}
/**
* Rotate 32-bit unsigned value to the left by @a cShift.
*
* @returns Rotated value.
* @param u32 The value to rotate.
* @param cShift How many bits to rotate by.
*/
{
return u32;
#else
cShift &= 31;
#endif
}
/**
* Rotate 32-bit unsigned value to the right by @a cShift.
*
* @returns Rotated value.
* @param u32 The value to rotate.
* @param cShift How many bits to rotate by.
*/
{
return u32;
#else
cShift &= 31;
#endif
}
/**
* Rotate 64-bit unsigned value to the left by @a cShift.
*
* @returns Rotated value.
* @param u64 The value to rotate.
* @param cShift How many bits to rotate by.
*/
{
return u64;
__asm__ __volatile__("testb $0x20, %%cl\n\t" /* if (cShift >= 0x20) { swap(u64.hi, u64lo); cShift -= 0x20; } */
"jz 1f\n\t"
"xchgl %%eax, %%edx\n\t"
"1:\n\t"
"andb $0x1f, %%cl\n\t" /* if (cShift & 0x1f) { */
"jz 2f\n\t"
"movl %%edx, %2\n\t" /* save the hi value in %3. */
"shldl %%cl,%%eax,%%edx\n\t" /* shift the hi value left, feeding MSBits from the low value. */
"shldl %%cl,%2,%%eax\n\t" /* shift the lo value left, feeding MSBits from the saved hi value. */
"2:\n\t" /* } */
: "0" (u64),
"1" (cShift));
return u64;
#else
cShift &= 63;
#endif
}
/**
* Rotate 64-bit unsigned value to the right by @a cShift.
*
* @returns Rotated value.
* @param u64 The value to rotate.
* @param cShift How many bits to rotate by.
*/
{
return u64;
__asm__ __volatile__("testb $0x20, %%cl\n\t" /* if (cShift >= 0x20) { swap(u64.hi, u64lo); cShift -= 0x20; } */
"jz 1f\n\t"
"xchgl %%eax, %%edx\n\t"
"1:\n\t"
"andb $0x1f, %%cl\n\t" /* if (cShift & 0x1f) { */
"jz 2f\n\t"
"movl %%edx, %2\n\t" /* save the hi value in %3. */
"shrdl %%cl,%%eax,%%edx\n\t" /* shift the hi value right, feeding LSBits from the low value. */
"shrdl %%cl,%2,%%eax\n\t" /* shift the lo value right, feeding LSBits from the saved hi value. */
"2:\n\t" /* } */
: "0" (u64),
"1" (cShift));
return u64;
#else
cShift &= 63;
#endif
}
/** @} */
/** @} */
#endif