hm_vmx.h revision 85da99cc8ab84eea915fd97c406498c5ab285b78
* Foundation, in version 2 as it comes in the "COPYING" file of the * VirtualBox OSE distribution. VirtualBox OSE is distributed in the * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. * The contents of this file may alternatively be used under the terms * of the Common Development and Distribution License Version 1.0 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the * VirtualBox OSE distribution, in which case the provisions of the * CDDL are applicable instead of those of the GPL. * You may elect to license modified versions of this file under the * terms and conditions of either the GPL or the CDDL or both. /** @defgroup grp_vmx vmx Types and Definitions /** @name VMX EPT paging structures * Number of page table entries in the EPT. (PDPTE/PDE/PTE) * EPT Page Directory Pointer Entry. Bit view. * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC, /** Reserved (must be 0). */ /** Available for software. */ /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */ /** Availabe for software. */ /** Bits 12-51 - - EPT - Physical Page number of the next level. */ /** The page shift to get the PML4 index. */ /** The PML4 index mask (apply to a shifted page address). */ /** Unsigned integer view. */ /** 64 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** Pointer to a PML4 table entry. */ /** Pointer to a const PML4 table entry. */ /** Pointer to an EPT PML4 Table. */ /** Pointer to a const EPT PML4 Table. */ * EPT Page Directory Pointer Entry. Bit view. /** Reserved (must be 0). */ /** Available for software. */ /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */ /** Availabe for software. */ /** Bits 12-51 - - EPT - Physical Page number of the next level. */ /** The page shift to get the PDPT index. */ /** The PDPT index mask (apply to a shifted page address). */ * EPT Page Directory Pointer. /** Unsigned integer view. */ /** 64 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** Pointer to an EPT Page Directory Pointer Entry. */ /** Pointer to a const EPT Page Directory Pointer Entry. */ * EPT Page Directory Pointer Table. /** Pointer to an EPT Page Directory Pointer Table. */ /** Pointer to a const EPT Page Directory Pointer Table. */ * EPT Page Directory Table Entry. Bit view. /** Reserved (must be 0). */ /** Big page (must be 0 here). */ /** Available for software. */ /** Physical address of page table. Restricted by maximum physical address width of the cpu. */ /** Availabe for software. */ /** Bits 12-51 - - EPT - Physical Page number of the next level. */ /** The page shift to get the PD index. */ /** The PD index mask (apply to a shifted page address). */ * EPT 2MB Page Directory Table Entry. Bit view. /** EPT Table Memory Type. MBZ for non-leaf nodes. */ /** Ignore PAT memory type */ /** Big page (must be 1 here). */ /** Available for software. */ /** Reserved (must be 0). */ /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */ /** Availabe for software. */ /** Bits 21-51 - - EPT - Physical Page number of the next level. */ * EPT Page Directory Table Entry. /** Unsigned integer view. */ /** 64 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** Pointer to an EPT Page Directory Table Entry. */ /** Pointer to a const EPT Page Directory Table Entry. */ * EPT Page Directory Table. /** Pointer to an EPT Page Directory Table. */ /** Pointer to a const EPT Page Directory Table. */ * EPT Page Table Entry. Bit view. * @remark This is a convenience "misnomer". The bit actually indicates * read access and the CPU will consider an entry with any of the * first three bits set as present. Since all our valid entries * will have this bit set, it can be used as a present indicator * and allow some code sharing. */ /** 2 - Executable bit. */ /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */ /** 6 - Ignore PAT memory type */ /** 11:7 - Available for software. */ /** 51:12 - Physical address of page. Restricted by maximum physical * address width of the cpu. */ /** 63:52 - Available for software. */ /** Bits 12-51 - - EPT - Physical Page number of the next level. */ /** The page shift to get the EPT PTE index. */ /** The EPT PT index mask (apply to a shifted page address). */ /** Unsigned integer view. */ /** 64 bit unsigned integer view. */ /** 32 bit unsigned integer view. */ /** Pointer to an EPT Page Directory Table Entry. */ /** Pointer to a const EPT Page Directory Table Entry. */ /** Pointer to an extended page table. */ /** Pointer to a const extended table. */ /** Invalidate a specific page. */ /** Invalidate one context (specific VPID). */ /** Invalidate all contexts (all VPIDs). */ /** Invalidate a single VPID context retaining global mappings. */ /** Unsupported by VirtualBox. */ /** Unsupported by CPU. */ /** 32bit hackishness. */ /** Invalidate one context (specific EPT). */ /* Invalidate all contexts (all EPTs) */ /** Unsupported by VirtualBox. */ /** Unsupported by CPU. */ /** 32bit hackishness. */ /** Pointer to a const MSR load/store element. */ /** @name VT-x capability qword /** @name VMX Basic Exit Reasons. /** And-mask for setting reserved bits to zero */ /** Or-mask for setting reserved bits to 1 */ /** @name VMX Basic Exit Reasons. /** -1 Invalid exit code */ /** 0 Exception or non-maskable interrupt (NMI). */ /** 1 External interrupt. */ /** 4 Start-up IPI (SIPI). */ /** 5 I/O system-management interrupt (SMI). */ /** 7 Interrupt window. */ /** 10 Guest software attempted to execute CPUID. */ /** 12 Guest software attempted to execute HLT. */ /** 13 Guest software attempted to execute INVD. */ /** 14 Guest software attempted to execute INVLPG. */ /** 15 Guest software attempted to execute RDPMC. */ /** 16 Guest software attempted to execute RDTSC. */ /** 17 Guest software attempted to execute RSM in SMM. */ /** 18 Guest software executed VMCALL. */ /** 19 Guest software executed VMCLEAR. */ /** 20 Guest software executed VMLAUNCH. */ /** 21 Guest software executed VMPTRLD. */ /** 22 Guest software executed VMPTRST. */ /** 23 Guest software executed VMREAD. */ /** 24 Guest software executed VMRESUME. */ /** 25 Guest software executed VMWRITE. */ /** 26 Guest software executed VMXOFF. */ /** 27 Guest software executed VMXON. */ /** 28 Control-register accesses. */ /** 29 Debug-register accesses. */ /** 30 I/O instruction. */ /** 31 RDMSR. Guest software attempted to execute RDMSR. */ /** 32 WRMSR. Guest software attempted to execute WRMSR. */ /** 33 VM-entry failure due to invalid guest state. */ /** 34 VM-entry failure due to MSR loading. */ /** 36 Guest software executed MWAIT. */ /** 37 VM exit due to monitor trap flag. */ /** 39 Guest software attempted to execute MONITOR. */ /** 40 Guest software attempted to execute PAUSE. */ /** 41 VM-entry failure due to machine-check. */ /** 43 TPR below threshold. Guest software executed MOV to CR8. */ /** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */ /** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */ /** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */ /** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */ /** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */ /** 50 INVEPT. Guest software attempted to execute INVEPT. */ /** 51 RDTSCP. Guest software attempted to execute RDTSCP. */ /** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */ /** 53 INVVPID. Guest software attempted to execute INVVPID. */ /** 54 WBINVD. Guest software attempted to execute WBINVD. */ /** 55 XSETBV. Guest software attempted to execute XSETBV. */ /** @name VM Instruction Errors /** 1 VMCALL executed in VMX root operation. */ /** 2 VMCLEAR with invalid physical address. */ /** 3 VMCLEAR with VMXON pointer. */ /** 4 VMLAUNCH with non-clear VMCS. */ /** 5 VMRESUME with non-launched VMCS. */ /** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */ /** 7 VM entry with invalid control field(s). */ /** 8 VM entry with invalid host-state field(s). */ /** 9 VMPTRLD with invalid physical address. */ /** 10 VMPTRLD with VMXON pointer. */ /** 11 VMPTRLD with incorrect VMCS revision identifier. */ /** 13 VMWRITE to read-only VMCS component. */ /** 15 VMXON executed in VMX root operation. */ /** 16 VM entry with invalid executive-VMCS pointer. */ /** 17 VM entry with non-launched executive VMCS. */ /** 18 VM entry with executive-VMCS pointer not VMXON pointer. */ /** 19 VMCALL with non-clear VMCS. */ /** 20 VMCALL with invalid VM-exit control fields. */ /** 22 VMCALL with incorrect MSEG revision identifier. */ /** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */ /** 24 VMCALL with invalid SMM-monitor features. */ /** 25 VM entry with invalid VM-execution control fields in executive VMCS. */ /** 26 VM entry with events blocked by MOV SS. */ /** @name VMX MSRs - Basic VMX information. /** VMCS revision identifier used by the processor. */ /** Width of physical address used for the VMCS. * 0 -> limited to the available amount of physical ram * 1 -> within the first 4 GB /** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */ /** Memory type that must be used for the VMCS. */ /** @name VMX MSRs - Misc VMX info. /** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */ /** Activity states supported by the implementation. */ /** Number of CR3 target values supported by the processor. (0-256) */ /** Maximum nr of MSRs in the VMCS. (N+1)*512. */ /** MSEG revision identifier used by the processor. */ /** @name VMX MSRs - VMCS enumeration field info /** Highest field index. */ /** @name MSR_IA32_VMX_EPT_CAPS; EPT capabilities MSR /** @name Extended Page Table Pointer (EPTP) /** Uncachable EPT paging structure memory type. */ /** Write-back EPT paging structure memory type. */ /** Shift value to get the EPT page walk length (bits 5-3) */ /** Mask value to get the EPT page walk length (bits 5-3) */ /** Default EPT page walk length */ /** @name VMCS field encoding - 16 bits guest fields /** @name VMCS field encoding - 16 bits host fields /** @name VMCS field encoding - 64 bits host fields /** @name VMCS field encoding - 64 Bits control fields /** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */ /** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */ /** Extended page table pointer. */ /** VM-exit phyiscal address. */ /** @name VMCS field encoding - 64 Bits guest fields /** @name VMCS field encoding - 32 Bits control fields /** This field exists only on processors that support the 1-setting of the �use TPR shadow� VM-execution control. */ /** This field exists only on processors that support the 1-setting of the �activate secondary controls� VM-execution control. */ /** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS /** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */ /** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */ /** Activate VMX preemption timer. */ /* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */ /** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS /** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */ /** Use timestamp counter offset. */ /** VM Exit when executing the HLT instruction. */ /** VM Exit when executing the INVLPG instruction. */ /** VM Exit when executing the MWAIT instruction. */ /** VM Exit when executing the RDPMC instruction. */ /** VM Exit when executing the RDTSC/RDTSCP instruction. */ /** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */ /** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */ /** VM Exit on CR8 loads. */ /** VM Exit on CR8 stores. */ /** VM Exit when virtual nmi blocking is disabled. */ /** VM Exit when executing a MOV DRx instruction. */ /** VM Exit when executing IO instructions. */ /** Monitor trap flag. */ /** VM Exit when executing the MONITOR instruction. */ /** VM Exit when executing the PAUSE instruction. */ /** Determines whether the secondary processor based VM-execution controls are used. */ /** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2 /** Virtualize APIC access. */ /** Descriptor table instructions cause VM-exits. */ /** Virtualize x2APIC mode. */ /** VM Exit when executing the WBINVD instruction. */ /** Unrestricted guest execution. */ /** A specified nr of pause loops cause a VM-exit. */ /** @name VMX_VMCS_CTRL_ENTRY_CONTROLS /** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */ /** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */ /** In SMM mode after VM-entry. */ /** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */ /** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */ /** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */ /** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */ /** @name VMX_VMCS_CTRL_EXIT_CONTROLS /** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */ /** Return to long mode after a VM-exit. */ /** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */ /** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */ /** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */ /** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */ /** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */ /** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */ /** This control determines whether the value of the VMX preemption timer is saved on VM exit. */ /** @name VMCS field encoding - 32 Bits read-only fields /** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO /** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */ /** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE /** @name VMCS field encoding - 32 Bits guest state fields /** @name VMX_VMCS_GUEST_ACTIVITY_STATE /** The logical processor is active. */ /** The logical processor is inactive, because executed a HLT instruction. */ /** The logical processor is inactive, because of a triple fault or other serious error. */ /** The logical processor is inactive, because it's waiting for a startup-IPI */ /** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE /** @name VMCS field encoding - 32 Bits host state fields /** @name Natural width control fields /** @name Natural width read-only data fields /** @name VMX_VMCS_RO_EXIT_QUALIFICATION /** 0-2: Debug register number */ /** 3: Reserved; cleared to 0. */ /** 4: Direction of move (0 = write, 1 = read) */ /** 5-7: Reserved; cleared to 0. */ /** 8-11: General purpose register number. */ /** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values /** 0-3: Control register number (0 for CLTS & LMSW) */ /** 6: LMSW operand type */ /** 7: Reserved; cleared to 0. */ /** 8-11: General purpose register number (0 for CLTS & LMSW). */ /** 12-15: Reserved; cleared to 0. */ /** 16-31: LMSW source data (else 0). */ /** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS /** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH /** Task switch caused by a call instruction. */ /** Task switch caused by an iret instruction. */ /** Task switch caused by a jmp instruction. */ /** Task switch caused by an interrupt gate. */ /** @name VMX_EXIT_EPT_VIOLATION /** Set if the violation was caused by a data read. */ /** Set if the violation was caused by a data write. */ /** Set if the violation was caused by an insruction fetch. */ /** AND of the present bit of all EPT structures. */ /** AND of the write bit of all EPT structures. */ /** AND of the execute bit of all EPT structures. */ /** Set if the guest linear address field contains the faulting address. */ /** If bit 7 is one: (reserved otherwise) * 1 - violation due to physical address access. * 0 - violation caused by page walk or access/dirty bit updates /** @name VMX_EXIT_PORT_IO /** 0-2: IO operation width. */ /** 3: IO operation direction. */ /** 4: String IO operation. */ /** 5: Repeated IO operation. */ /** 6: Operand encoding. */ /** 16-31: IO Port (0-0xffff). */ /** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION /** @name VMX_EXIT_QUALIFICATION_IO_ENCODING /** @name VMX_EXIT_APIC_ACCESS /** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */ /** 12-15: Access type. */ /** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types /** Linear read access. */ /** Linear write access. */ /** Linear instruction fetch access. */ /** Linear read/write access during event delivery. */ /** Physical read/write access during event delivery. */ /** Physical access for an instruction fetch or during instruction execution. */ /** @name VMCS field encoding - Natural width guest state fields /** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS /** Hardware breakpoint 0 was met. */ /** Hardware breakpoint 1 was met. */ /** Hardware breakpoint 2 was met. */ /** Hardware breakpoint 3 was met. */ /** At least one data or IO breakpoint was hit. */ /** A debug exception would have been triggered by single-step execution mode. */ /** Bits 4-11, 13 and 15-63 are reserved. */ /** @name VMCS field encoding - Natural width host state fields /** @defgroup grp_vmx_asm vmx assembly helpers * @returns VBox status code * @param pVMXOn Physical address of VMXON structure ".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t" "ir"((
uint32_t)
pVMXOn),
/* don't allow direct memory reference here, */ "ir"((
uint32_t)(
pVMXOn >>
32))
/* this would not work with -fomit-frame-pointer */ _emit 0x24 /* VMXON [esp] */ ".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t" * @returns VBox status code * @param pVMCS Physical address of VM control structure ".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t" "ir"((
uint32_t)
pVMCS),
/* don't allow direct memory reference here, */ "ir"((
uint32_t)(
pVMCS >>
32))
/* this would not work with -fomit-frame-pointer */ _emit 0x24 /* VMCLEAR [esp] */ * @returns VBox status code * @param pVMCS Physical address of VMCS structure ".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t" "ir"((
uint32_t)
pVMCS),
/* don't allow direct memory reference here, */ "ir"((
uint32_t)(
pVMCS >>
32))
/* this will not work with -fomit-frame-pointer */ _emit 0x24 /* VMPTRLD [esp] */ * @returns VBox status code * @param pVMCS Address that will receive the current pointer * @returns VBox status code * @param idxField VMCS index * @param u32Val 32 bits value ".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t" _emit 0x24 /* VMWRITE eax, [esp] */ * @returns VBox status code * @param idxField VMCS index * @param u64Val 16, 32 or 64 bits value #
endif /* HC_ARCH_BITS == 64 */ * Invalidate a page using invept * @returns VBox status code * @param enmFlush Type of flush * @param pDescriptor Descriptor * Invalidate a page using invvpid * @returns VBox status code * @param enmFlush Type of flush * @param pDescriptor Descriptor * @returns VBox status code * @param idxField VMCS index * @param pData Ptr to store VM field value ".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t" _emit 0x24 /* VMREAD eax, [esp] */ * @returns VBox status code * @param idxField VMCS index * @param pData Ptr to store VM field value #
endif /* HC_ARCH_BITS == 64 */ * Gets the last instruction error value from the current VMCS