hm_vmx.h revision 0e9cc3188ccb171a102e6b1fc48ed9919324aa23
/** @file
* HM - VMX Structures and Definitions. (VMM)
*/
/*
* Copyright (C) 2006-2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* The contents of this file may alternatively be used under the terms
* of the Common Development and Distribution License Version 1.0
* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
* VirtualBox OSE distribution, in which case the provisions of the
* CDDL are applicable instead of those of the GPL.
*
* You may elect to license modified versions of this file under the
* terms and conditions of either the GPL or the CDDL or both.
*/
#ifndef ___VBox_vmm_vmx_h
#define ___VBox_vmm_vmx_h
/** @defgroup grp_vmx vmx Types and Definitions
* @ingroup grp_hm
* @{
*/
/** @name VMX EPT paging structures
* @{
*/
/**
*/
#define EPT_PG_ENTRIES X86_PG_PAE_ENTRIES
/**
* EPT Page Directory Pointer Entry. Bit view.
* @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
*/
#pragma pack(1)
typedef struct EPTPML4EBITS
{
/** Present bit. */
/** Writable bit. */
/** Executable bit. */
/** Reserved (must be 0). */
/** Available for software. */
/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
/** Availabe for software. */
} EPTPML4EBITS;
#pragma pack()
/** Bits 12-51 - - EPT - Physical Page number of the next level. */
#define EPT_PML4E_PG_MASK X86_PML4E_PG_MASK
/** The page shift to get the PML4 index. */
#define EPT_PML4_SHIFT X86_PML4_SHIFT
/** The PML4 index mask (apply to a shifted page address). */
#define EPT_PML4_MASK X86_PML4_MASK
/**
* EPT PML4E.
*/
#pragma pack(1)
typedef union EPTPML4E
{
/** Normal view. */
EPTPML4EBITS n;
/** Unsigned integer view. */
X86PGPAEUINT u;
/** 64 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} EPTPML4E;
#pragma pack()
/** Pointer to a PML4 table entry. */
/** Pointer to a const PML4 table entry. */
typedef const EPTPML4E *PCEPTPML4E;
/**
* EPT PML4 Table.
*/
#pragma pack(1)
typedef struct EPTPML4
{
} EPTPML4;
#pragma pack()
/** Pointer to an EPT PML4 Table. */
/** Pointer to a const EPT PML4 Table. */
/**
* EPT Page Directory Pointer Entry. Bit view.
*/
#pragma pack(1)
typedef struct EPTPDPTEBITS
{
/** Present bit. */
/** Writable bit. */
/** Executable bit. */
/** Reserved (must be 0). */
/** Available for software. */
/** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
/** Availabe for software. */
} EPTPDPTEBITS;
#pragma pack()
/** Bits 12-51 - - EPT - Physical Page number of the next level. */
#define EPT_PDPTE_PG_MASK X86_PDPE_PG_MASK
/** The page shift to get the PDPT index. */
#define EPT_PDPT_SHIFT X86_PDPT_SHIFT
/** The PDPT index mask (apply to a shifted page address). */
#define EPT_PDPT_MASK X86_PDPT_MASK_AMD64
/**
* EPT Page Directory Pointer.
*/
#pragma pack(1)
typedef union EPTPDPTE
{
/** Normal view. */
EPTPDPTEBITS n;
/** Unsigned integer view. */
X86PGPAEUINT u;
/** 64 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} EPTPDPTE;
#pragma pack()
/** Pointer to an EPT Page Directory Pointer Entry. */
/** Pointer to a const EPT Page Directory Pointer Entry. */
typedef const EPTPDPTE *PCEPTPDPTE;
/**
* EPT Page Directory Pointer Table.
*/
#pragma pack(1)
typedef struct EPTPDPT
{
} EPTPDPT;
#pragma pack()
/** Pointer to an EPT Page Directory Pointer Table. */
/** Pointer to a const EPT Page Directory Pointer Table. */
/**
* EPT Page Directory Table Entry. Bit view.
*/
#pragma pack(1)
typedef struct EPTPDEBITS
{
/** Present bit. */
/** Writable bit. */
/** Executable bit. */
/** Reserved (must be 0). */
/** Big page (must be 0 here). */
/** Available for software. */
/** Physical address of page table. Restricted by maximum physical address width of the cpu. */
/** Availabe for software. */
} EPTPDEBITS;
#pragma pack()
/** Bits 12-51 - - EPT - Physical Page number of the next level. */
#define EPT_PDE_PG_MASK X86_PDE_PAE_PG_MASK
/** The page shift to get the PD index. */
#define EPT_PD_SHIFT X86_PD_PAE_SHIFT
/** The PD index mask (apply to a shifted page address). */
#define EPT_PD_MASK X86_PD_PAE_MASK
/**
* EPT 2MB Page Directory Table Entry. Bit view.
*/
#pragma pack(1)
typedef struct EPTPDE2MBITS
{
/** Present bit. */
/** Writable bit. */
/** Executable bit. */
/** EPT Table Memory Type. MBZ for non-leaf nodes. */
/** Ignore PAT memory type */
/** Big page (must be 1 here). */
/** Available for software. */
/** Reserved (must be 0). */
/** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
/** Availabe for software. */
} EPTPDE2MBITS;
#pragma pack()
/** Bits 21-51 - - EPT - Physical Page number of the next level. */
/**
* EPT Page Directory Table Entry.
*/
#pragma pack(1)
typedef union EPTPDE
{
/** Normal view. */
EPTPDEBITS n;
/** 2MB view (big). */
EPTPDE2MBITS b;
/** Unsigned integer view. */
X86PGPAEUINT u;
/** 64 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} EPTPDE;
#pragma pack()
/** Pointer to an EPT Page Directory Table Entry. */
/** Pointer to a const EPT Page Directory Table Entry. */
/**
* EPT Page Directory Table.
*/
#pragma pack(1)
typedef struct EPTPD
{
EPTPDE a[EPT_PG_ENTRIES];
} EPTPD;
#pragma pack()
/** Pointer to an EPT Page Directory Table. */
/** Pointer to a const EPT Page Directory Table. */
/**
* EPT Page Table Entry. Bit view.
*/
#pragma pack(1)
typedef struct EPTPTEBITS
{
/** 0 - Present bit.
* @remark This is a convenience "misnomer". The bit actually indicates
* read access and the CPU will consider an entry with any of the
* first three bits set as present. Since all our valid entries
* will have this bit set, it can be used as a present indicator
* and allow some code sharing. */
/** 1 - Writable bit. */
/** 2 - Executable bit. */
/** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
/** 6 - Ignore PAT memory type */
/** 11:7 - Available for software. */
/** 51:12 - Physical address of page. Restricted by maximum physical
* address width of the cpu. */
/** 63:52 - Available for software. */
} EPTPTEBITS;
#pragma pack()
/** Bits 12-51 - - EPT - Physical Page number of the next level. */
#define EPT_PTE_PG_MASK X86_PTE_PAE_PG_MASK
/** The page shift to get the EPT PTE index. */
#define EPT_PT_SHIFT X86_PT_PAE_SHIFT
/** The EPT PT index mask (apply to a shifted page address). */
#define EPT_PT_MASK X86_PT_PAE_MASK
/**
* EPT Page Table Entry.
*/
#pragma pack(1)
typedef union EPTPTE
{
/** Normal view. */
EPTPTEBITS n;
/** Unsigned integer view. */
X86PGPAEUINT u;
/** 64 bit unsigned integer view. */
/** 32 bit unsigned integer view. */
} EPTPTE;
#pragma pack()
/** Pointer to an EPT Page Directory Table Entry. */
/** Pointer to a const EPT Page Directory Table Entry. */
/**
* EPT Page Table.
*/
#pragma pack(1)
typedef struct EPTPT
{
EPTPTE a[EPT_PG_ENTRIES];
} EPTPT;
#pragma pack()
/** Pointer to an extended page table. */
/** Pointer to a const extended table. */
/**
* VPID flush types.
*/
typedef enum
{
/** Invalidate a specific page. */
/** Invalidate one context (specific VPID). */
/** Invalidate all contexts (all VPIDs). */
/** Invalidate a single VPID context retaining global mappings. */
/** Unsupported by VirtualBox. */
VMX_FLUSH_VPID_NOT_SUPPORTED = 0xbad,
/** Unsupported by CPU. */
VMX_FLUSH_VPID_NONE = 0xb00,
/** 32bit hackishness. */
VMX_FLUSH_VPID_32BIT_HACK = 0x7fffffff
/**
* EPT flush types.
*/
typedef enum
{
/** Invalidate one context (specific EPT). */
/* Invalidate all contexts (all EPTs) */
/** Unsupported by VirtualBox. */
VMX_FLUSH_EPT_NOT_SUPPORTED = 0xbad,
/** Unsupported by CPU. */
VMX_FLUSH_EPT_NONE = 0xb00,
/** 32bit hackishness. */
VMX_FLUSH_EPT_32BIT_HACK = 0x7fffffff
/** @} */
* @{
*/
#pragma pack(1)
typedef struct
{
} VMXMSR;
#pragma pack()
/** @} */
/** @name VT-x capability qword
* @{
*/
#pragma pack(1)
typedef union
{
struct
{
/** Bits set here -must- be set in the correpsonding VM-execution controls. */
/** Bits cleared here -must- be cleared in the corresponding VM-execution
* controls. */
} n;
uint64_t u;
#pragma pack()
/** @} */
/** @name VMX Basic Exit Reasons.
* @{
*/
/** And-mask for setting reserved bits to zero */
#define VMX_EFLAGS_RESERVED_0 (~0xffc08028)
/** Or-mask for setting reserved bits to 1 */
#define VMX_EFLAGS_RESERVED_1 0x00000002
/** @} */
/** @name VMX Basic Exit Reasons.
* @{
*/
/** -1 Invalid exit code */
#define VMX_EXIT_INVALID -1
/** 0 Exception or non-maskable interrupt (NMI). */
#define VMX_EXIT_XCPT_NMI 0
/** 1 External interrupt. */
#define VMX_EXIT_EXT_INT 1
/** 2 Triple fault. */
#define VMX_EXIT_TRIPLE_FAULT 2
/** 3 INIT signal. */
#define VMX_EXIT_INIT_SIGNAL 3
/** 4 Start-up IPI (SIPI). */
#define VMX_EXIT_SIPI 4
/** 5 I/O system-management interrupt (SMI). */
#define VMX_EXIT_IO_SMI 5
/** 6 Other SMI. */
#define VMX_EXIT_SMI 6
/** 7 Interrupt window exiting. */
#define VMX_EXIT_INT_WINDOW 7
/** 9 Task switch. */
#define VMX_EXIT_TASK_SWITCH 9
/** 10 Guest software attempted to execute CPUID. */
#define VMX_EXIT_CPUID 10
/** 12 Guest software attempted to execute HLT. */
#define VMX_EXIT_HLT 12
/** 13 Guest software attempted to execute INVD. */
#define VMX_EXIT_INVD 13
/** 14 Guest software attempted to execute INVLPG. */
#define VMX_EXIT_INVLPG 14
/** 15 Guest software attempted to execute RDPMC. */
#define VMX_EXIT_RDPMC 15
/** 16 Guest software attempted to execute RDTSC. */
#define VMX_EXIT_RDTSC 16
/** 17 Guest software attempted to execute RSM in SMM. */
#define VMX_EXIT_RSM 17
/** 18 Guest software executed VMCALL. */
#define VMX_EXIT_VMCALL 18
/** 19 Guest software executed VMCLEAR. */
#define VMX_EXIT_VMCLEAR 19
/** 20 Guest software executed VMLAUNCH. */
#define VMX_EXIT_VMLAUNCH 20
/** 21 Guest software executed VMPTRLD. */
#define VMX_EXIT_VMPTRLD 21
/** 22 Guest software executed VMPTRST. */
#define VMX_EXIT_VMPTRST 22
/** 23 Guest software executed VMREAD. */
#define VMX_EXIT_VMREAD 23
/** 24 Guest software executed VMRESUME. */
#define VMX_EXIT_VMRESUME 24
/** 25 Guest software executed VMWRITE. */
#define VMX_EXIT_VMWRITE 25
/** 26 Guest software executed VMXOFF. */
#define VMX_EXIT_VMXOFF 26
/** 27 Guest software executed VMXON. */
#define VMX_EXIT_VMXON 27
/** 28 Control-register accesses. */
#define VMX_EXIT_MOV_CRX 28
/** 29 Debug-register accesses. */
#define VMX_EXIT_MOV_DRX 29
/** 30 I/O instruction. */
#define VMX_EXIT_IO_INSTR 30
/** 31 RDMSR. Guest software attempted to execute RDMSR. */
#define VMX_EXIT_RDMSR 31
/** 32 WRMSR. Guest software attempted to execute WRMSR. */
#define VMX_EXIT_WRMSR 32
/** 33 VM-entry failure due to invalid guest state. */
#define VMX_EXIT_ERR_INVALID_GUEST_STATE 33
/** 34 VM-entry failure due to MSR loading. */
#define VMX_EXIT_ERR_MSR_LOAD 34
/** 36 Guest software executed MWAIT. */
#define VMX_EXIT_MWAIT 36
/** 37 VM exit due to monitor trap flag. */
#define VMX_EXIT_MTF 37
/** 39 Guest software attempted to execute MONITOR. */
#define VMX_EXIT_MONITOR 39
/** 40 Guest software attempted to execute PAUSE. */
#define VMX_EXIT_PAUSE 40
/** 41 VM-entry failure due to machine-check. */
#define VMX_EXIT_ERR_MACHINE_CHECK 41
/** 43 TPR below threshold. Guest software executed MOV to CR8. */
#define VMX_EXIT_TPR_BELOW_THRESHOLD 43
/** 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
#define VMX_EXIT_APIC_ACCESS 44
/** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT. */
#define VMX_EXIT_XDTR_ACCESS 46
/** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR. */
#define VMX_EXIT_TR_ACCESS 47
/** 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
#define VMX_EXIT_EPT_VIOLATION 48
/** 49 EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry. */
#define VMX_EXIT_EPT_MISCONFIG 49
/** 50 INVEPT. Guest software attempted to execute INVEPT. */
#define VMX_EXIT_INVEPT 50
/** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
#define VMX_EXIT_RDTSCP 51
/** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
#define VMX_EXIT_PREEMPTION_TIMER 52
/** 53 INVVPID. Guest software attempted to execute INVVPID. */
#define VMX_EXIT_INVVPID 53
/** 54 WBINVD. Guest software attempted to execute WBINVD. */
#define VMX_EXIT_WBINVD 54
/** 55 XSETBV. Guest software attempted to execute XSETBV. */
#define VMX_EXIT_XSETBV 55
/** 57 RDRAND. Guest software attempted to execute RDRAND. */
#define VMX_EXIT_RDRAND 57
/** 58 INVPCID. Guest software attempted to execute INVPCID. */
#define VMX_EXIT_INVPCID 58
/** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
#define VMX_EXIT_VMFUNC 59
/** The maximum exit value (inclusive). */
#define VMX_EXIT_MAX (VMX_EXIT_VMFUNC)
/** @} */
/** @name VM Instruction Errors
* @{
*/
/** 1 VMCALL executed in VMX root operation. */
#define VMX_ERROR_VMCALL 1
/** 2 VMCLEAR with invalid physical address. */
#define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR 2
/** 3 VMCLEAR with VMXON pointer. */
#define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR 3
/** 4 VMLAUNCH with non-clear VMCS. */
#define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS 4
/** 5 VMRESUME with non-launched VMCS. */
#define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS 5
/** 6 VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
#define VMX_ERROR_VMRESUME_CORRUPTED_VMCS 6
/** 7 VM entry with invalid control field(s). */
#define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS 7
/** 8 VM entry with invalid host-state field(s). */
#define VMX_ERROR_VMENTRY_INVALID_HOST_STATE 8
/** 9 VMPTRLD with invalid physical address. */
#define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR 9
/** 10 VMPTRLD with VMXON pointer. */
#define VMX_ERROR_VMPTRLD_VMXON_PTR 10
/** 11 VMPTRLD with incorrect VMCS revision identifier. */
#define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION 11
#define VMX_ERROR_VMREAD_INVALID_COMPONENT 12
/** 13 VMWRITE to read-only VMCS component. */
#define VMX_ERROR_VMWRITE_READONLY_COMPONENT 13
/** 15 VMXON executed in VMX root operation. */
#define VMX_ERROR_VMXON_IN_VMX_ROOT_OP 15
/** 16 VM entry with invalid executive-VMCS pointer. */
#define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR 16
/** 17 VM entry with non-launched executive VMCS. */
#define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS 17
/** 18 VM entry with executive-VMCS pointer not VMXON pointer. */
#define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR 18
/** 19 VMCALL with non-clear VMCS. */
#define VMX_ERROR_VMCALL_NON_CLEAR_VMCS 19
/** 20 VMCALL with invalid VM-exit control fields. */
#define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS 20
/** 22 VMCALL with incorrect MSEG revision identifier. */
#define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION 22
/** 23 VMXOFF under dual-monitor treatment of SMIs and SMM. */
#define VMX_ERROR_VMXOFF_DUAL_MONITOR 23
/** 24 VMCALL with invalid SMM-monitor features. */
#define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR 24
/** 25 VM entry with invalid VM-execution control fields in executive VMCS. */
#define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL 25
/** 26 VM entry with events blocked by MOV SS. */
#define VMX_ERROR_VMENTRY_MOV_SS 26
#define VMX_ERROR_INVEPTVPID_INVALID_OPERAND 28
/** @} */
/** @name VMX MSRs - Basic VMX information.
* @{
*/
/** VMCS revision identifier used by the processor. */
#define MSR_IA32_VMX_BASIC_INFO_VMCS_ID(a) (a & 0x7FFFFFFF)
/** Size of the VMCS. */
/** Width of physical address used for the VMCS.
* 0 -> limited to the available amount of physical ram
* 1 -> within the first 4 GB
*/
/** Whether the processor supports the dual-monitor treatment of system-management interrupts and system-management code. (always 1) */
/** Memory type that must be used for the VMCS. */
/** @} */
/** @name VMX MSRs - Misc VMX info.
* @{
*/
/** Relationship between the preemption timer and tsc; count down every time bit x of the tsc changes. */
#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a) ((a) & 0x1f)
/** Activity states supported by the implementation. */
/** Number of CR3 target values supported by the processor. (0-256) */
/** Maximum nr of MSRs in the VMCS. (N+1)*512. */
/** MSEG revision identifier used by the processor. */
#define MSR_IA32_VMX_MISC_MSEG_ID(a) ((a) >> 32)
/** @} */
/** @name VMX MSRs - VMCS enumeration field info
* @{
*/
/** Highest field index. */
/** @} */
/** @name MSR_IA32_VMX_EPT_VPID_CAPS; EPT capabilities MSR
* @{
*/
#define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0)
/** @} */
/** @name Extended Page Table Pointer (EPTP)
* @{
*/
/** Uncachable EPT paging structure memory type. */
#define VMX_EPT_MEMTYPE_UC 0
/** Write-back EPT paging structure memory type. */
#define VMX_EPT_MEMTYPE_WB 6
/** Shift value to get the EPT page walk length (bits 5-3) */
#define VMX_EPT_PAGE_WALK_LENGTH_SHIFT 3
/** Mask value to get the EPT page walk length (bits 5-3) */
#define VMX_EPT_PAGE_WALK_LENGTH_MASK 7
/** Default EPT page-walk length (1 less than the actual EPT page-walk
* length) */
#define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT 3
/** @} */
/** @name VMCS field encoding - 16 bits guest fields
* @{
*/
#define VMX_VMCS16_GUEST_FIELD_VPID 0x0
#define VMX_VMCS16_GUEST_FIELD_ES 0x800
#define VMX_VMCS16_GUEST_FIELD_CS 0x802
#define VMX_VMCS16_GUEST_FIELD_SS 0x804
#define VMX_VMCS16_GUEST_FIELD_DS 0x806
#define VMX_VMCS16_GUEST_FIELD_FS 0x808
#define VMX_VMCS16_GUEST_FIELD_GS 0x80A
#define VMX_VMCS16_GUEST_FIELD_LDTR 0x80C
#define VMX_VMCS16_GUEST_FIELD_TR 0x80E
/** @} */
/** @name VMCS field encoding - 16 bits host fields
* @{
*/
#define VMX_VMCS16_HOST_FIELD_ES 0xC00
#define VMX_VMCS16_HOST_FIELD_CS 0xC02
#define VMX_VMCS16_HOST_FIELD_SS 0xC04
#define VMX_VMCS16_HOST_FIELD_DS 0xC06
#define VMX_VMCS16_HOST_FIELD_FS 0xC08
#define VMX_VMCS16_HOST_FIELD_GS 0xC0A
#define VMX_VMCS16_HOST_FIELD_TR 0xC0C
/** @} */
/** @name VMCS field encoding - 64 bits host fields
* @{
*/
#define VMX_VMCS64_HOST_FIELD_PAT_FULL 0x2C00
#define VMX_VMCS64_HOST_FIELD_PAT_HIGH 0x2C01
#define VMX_VMCS64_HOST_FIELD_EFER_FULL 0x2C02
#define VMX_VMCS64_HOST_FIELD_EFER_HIGH 0x2C03
/** @} */
/** @name VMCS field encoding - 64 Bits control fields
* @{
*/
#define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL 0x2000
#define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH 0x2001
#define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL 0x2002
#define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH 0x2003
/* Optional */
#define VMX_VMCS64_CTRL_MSR_BITMAP_FULL 0x2004
#define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH 0x2005
#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL 0x2006
#define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH 0x2007
#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL 0x2008
#define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH 0x2009
#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL 0x200A
#define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH 0x200B
#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL 0x200C
#define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH 0x200D
#define VMX_VMCS64_CTRL_TSC_OFFSET_FULL 0x2010
#define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH 0x2011
/** Optional (VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW) */
#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL 0x2012
#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH 0x2013
/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) */
#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL 0x2014
#define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH 0x2015
/** Optional (VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC) */
#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL 0x2018
#define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH 0x2019
/** Extended page table pointer. */
#define VMX_VMCS64_CTRL_EPTP_FULL 0x201a
#define VMX_VMCS64_CTRL_EPTP_HIGH 0x201b
/** Extended page table pointer lists. */
#define VMX_VMCS64_CTRL_EPTP_LIST_FULL 0x2024
#define VMX_VMCS64_CTRL_EPTP_LIST_HIGH 0x2025
/** VM-exit guest phyiscal address. */
#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400
#define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401
/** @} */
/** @name VMCS field encoding - 64 Bits guest fields
* @{
*/
#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL 0x2800
#define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH 0x2801
#define VMX_VMCS64_GUEST_PAT_FULL 0x2804
#define VMX_VMCS64_GUEST_PAT_HIGH 0x2805
#define VMX_VMCS64_GUEST_EFER_FULL 0x2806
#define VMX_VMCS64_GUEST_EFER_HIGH 0x2807
#define VMX_VMCS64_GUEST_PDPTE0_FULL 0x280A
#define VMX_VMCS64_GUEST_PDPTE0_HIGH 0x280B
#define VMX_VMCS64_GUEST_PDPTE1_FULL 0x280C
#define VMX_VMCS64_GUEST_PDPTE1_HIGH 0x280D
#define VMX_VMCS64_GUEST_PDPTE2_FULL 0x280E
#define VMX_VMCS64_GUEST_PDPTE2_HIGH 0x280F
#define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810
#define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811
/** @} */
/** @name VMCS field encoding - 32 Bits control fields
* @{
*/
#define VMX_VMCS32_CTRL_PIN_EXEC_CONTROLS 0x4000
#define VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS 0x4002
#define VMX_VMCS32_CTRL_EXCEPTION_BITMAP 0x4004
#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK 0x4006
#define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH 0x4008
#define VMX_VMCS32_CTRL_CR3_TARGET_COUNT 0x400A
#define VMX_VMCS32_CTRL_EXIT_CONTROLS 0x400C
#define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT 0x400E
#define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT 0x4010
#define VMX_VMCS32_CTRL_ENTRY_CONTROLS 0x4012
#define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT 0x4014
#define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO 0x4016
#define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE 0x4018
#define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH 0x401A
#define VMX_VMCS32_CTRL_TPR_THRESHOLD 0x401C
#define VMX_VMCS32_CTRL_PROC_EXEC_CONTROLS2 0x401E
/** @} */
/** @name VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
* @{
*/
/** External interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
/** Non-maskable interrupts cause VM exits if set; otherwise dispatched through the guest's IDT. */
/** Virtual NMIs. */
/** Activate VMX preemption timer. */
/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
/** @} */
/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
* @{
*/
/** VM Exit as soon as RFLAGS.IF=1 and no blocking is active. */
/** Use timestamp counter offset. */
/** VM Exit when executing the HLT instruction. */
/** VM Exit when executing the INVLPG instruction. */
/** VM Exit when executing the MWAIT instruction. */
/** VM Exit when executing the RDPMC instruction. */
/** VM Exit when executing the MOV to CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
/** VM Exit when executing the MOV from CR3 instruction. (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
/** VM Exit on CR8 loads. */
/** VM Exit on CR8 stores. */
/** Use TPR shadow. */
/** VM Exit when virtual nmi blocking is disabled. */
/** VM Exit when executing a MOV DRx instruction. */
/** VM Exit when executing IO instructions. */
/** Use IO bitmaps. */
/** Monitor trap flag. */
/** Use MSR bitmaps. */
/** VM Exit when executing the MONITOR instruction. */
/** VM Exit when executing the PAUSE instruction. */
/** Determines whether the secondary processor based VM-execution controls are used. */
/** @} */
/** @name VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
* @{
*/
/** Virtualize APIC access. */
#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC RT_BIT(0)
/** Descriptor table instructions cause VM-exits. */
/** Virtualize x2APIC mode. */
/** VM Exit when executing the WBINVD instruction. */
/** Unrestricted guest execution. */
/** A specified nr of pause loops cause a VM-exit. */
/** VM Exit when executing RDRAND instructions. */
/** Enables INVPCID instructions. */
/** Enables VMFUNC instructions. */
/** @} */
/** @name VMX_VMCS_CTRL_ENTRY_CONTROLS
* @{
*/
/** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
/** In SMM mode after VM-entry. */
/** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
/** This control determines whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM entry. */
/** This control determines whether the guest IA32_PAT MSR is loaded on VM entry. */
/** This control determines whether the guest IA32_EFER MSR is loaded on VM entry. */
/** @} */
/** @name VMX_VMCS_CTRL_EXIT_CONTROLS
* @{
*/
/** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
/** Return to long mode after a VM-exit. */
/** This control determines whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM exit. */
/** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
/** This control determines whether the guest IA32_PAT MSR is saved on VM exit. */
/** This control determines whether the host IA32_PAT MSR is loaded on VM exit. */
/** This control determines whether the guest IA32_EFER MSR is saved on VM exit. */
/** This control determines whether the host IA32_EFER MSR is loaded on VM exit. */
/** This control determines whether the value of the VMX preemption timer is saved on VM exit. */
/** @} */
/** @name VMCS field encoding - 32 Bits read-only fields
* @{
*/
#define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400
#define VMX_VMCS32_RO_EXIT_REASON 0x4402
#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404
#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406
#define VMX_VMCS32_RO_IDT_INFO 0x4408
#define VMX_VMCS32_RO_IDT_ERROR_CODE 0x440A
#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440C
#define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440E
/** @} */
/** @name VMX_VMCS32_RO_EXIT_REASON
* @{
*/
#define VMX_EXIT_REASON_BASIC(a) (a & 0xffff)
/** @} */
/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
* @{
*/
/** @} */
/** @name VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO
* @{
*/
#define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) (a & 0xff)
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8
#define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(a) (a & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID)
#define VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT 31
/** Construct an irq event injection value from the exit interruption info value (same except that bit 12 is reserved). */
/** @} */
/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
* @{
*/
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT 0
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI 2
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT 3
#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT 6
/** @} */
/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
* @{
*/
#define VMX_IDT_VECTORING_INFO_VECTOR(a) (a & 0xff)
#define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8
/** @} */
/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
* @{
*/
#define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT 0
#define VMX_IDT_VECTORING_INFO_TYPE_NMI 2
#define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT 3
#define VMX_IDT_VECTORING_INFO_TYPE_SW_INT 4
#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5
#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6
/** @} */
/** @name VMCS field encoding - 32 Bits guest state fields
* @{
*/
#define VMX_VMCS32_GUEST_ES_LIMIT 0x4800
#define VMX_VMCS32_GUEST_CS_LIMIT 0x4802
#define VMX_VMCS32_GUEST_SS_LIMIT 0x4804
#define VMX_VMCS32_GUEST_DS_LIMIT 0x4806
#define VMX_VMCS32_GUEST_FS_LIMIT 0x4808
#define VMX_VMCS32_GUEST_GS_LIMIT 0x480A
#define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480C
#define VMX_VMCS32_GUEST_TR_LIMIT 0x480E
#define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810
#define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812
#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814
#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816
#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818
#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481A
#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481C
#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481E
#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820
#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822
#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x4824
#define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826
#define VMX_VMCS32_GUEST_PREEMPTION_TIMER_VALUE 0x482E
/** @} */
/** @name VMX_VMCS_GUEST_ACTIVITY_STATE
* @{
*/
/** The logical processor is active. */
#define VMX_VMCS_GUEST_ACTIVITY_ACTIVE 0x0
/** The logiVMCS processor is inactive, because executed a HLT instruction. */
#define VMX_VMCS_GUEST_ACTIVITY_HLT 0x1
/** The logiVMCS processor is inactive, because of a triple fault or other serious error. */
#define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN 0x2
/** The logiVMCS processor is inactive, because it's waiting for a startup-IPI */
#define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT 0x3
/** @} */
/** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE
* @{
*/
/** @} */
/** @name VMCS field encoding - 32 Bits host state fields
* @{
*/
#define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00
/** @} */
/** @name Natural width control fields
* @{
*/
#define VMX_VMCS_CTRL_CR0_MASK 0x6000
#define VMX_VMCS_CTRL_CR4_MASK 0x6002
#define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004
#define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006
#define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008
#define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600A
#define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600C
#define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600E
/** @} */
/** @name Natural width read-only data fields
* @{
*/
#define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400
#define VMX_VMCS_RO_IO_RCX 0x6402
#define VMX_VMCS_RO_IO_RSX 0x6404
#define VMX_VMCS_RO_IO_RDI 0x6406
#define VMX_VMCS_RO_IO_RIP 0x6408
#define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640A
/** @} */
/** @name VMX_VMCS_RO_EXIT_QUALIFICATION
* @{
*/
/** 0-2: Debug register number */
#define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a) (a & 7)
/** 3: Reserved; cleared to 0. */
/** 4: Direction of move (0 = write, 1 = read) */
/** 5-7: Reserved; cleared to 0. */
/** 8-11: General purpose register number. */
/** Rest: reserved. */
/** @} */
/** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
* @{
*/
/** @} */
/** @name CRx accesses
* @{
*/
/** 0-3: Control register number (0 for CLTS & LMSW) */
#define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a) (a & 0xF)
/** 4-5: Access type. */
/** 6: LMSW operand type */
/** 7: Reserved; cleared to 0. */
/** 8-11: General purpose register number (0 for CLTS & LMSW). */
/** 12-15: Reserved; cleared to 0. */
/** 16-31: LMSW source data (else 0). */
/** Rest: reserved. */
/** @} */
/** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
* @{
*/
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE 0
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ 1
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS 2
#define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW 3
/** @} */
/** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
* @{
*/
#define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a) (a & 0xffff)
/** Task switch caused by a call instruction. */
/** Task switch caused by an iret instruction. */
/** Task switch caused by a jmp instruction. */
/** Task switch caused by an interrupt gate. */
/** @} */
/** @name VMX_EXIT_EPT_VIOLATION
* @{
*/
/** Set if the violation was caused by a data read. */
#define VMX_EXIT_QUALIFICATION_EPT_DATA_READ RT_BIT(0)
/** Set if the violation was caused by a data write. */
/** Set if the violation was caused by an insruction fetch. */
/** AND of the present bit of all EPT structures. */
/** AND of the write bit of all EPT structures. */
/** AND of the execute bit of all EPT structures. */
/** Set if the guest linear address field contains the faulting address. */
/** If bit 7 is one: (reserved otherwise)
* 1 - violation due to physical address access.
*/
/** @} */
/** @name VMX_EXIT_PORT_IO
* @{
*/
/** 0-2: IO operation width. */
#define VMX_EXIT_QUALIFICATION_IO_WIDTH(a) (a & 7)
/** 3: IO operation direction. */
/** 4: String IO operation. */
/** 5: Repeated IO operation. */
/** 6: Operand encoding. */
/** 16-31: IO Port (0-0xffff). */
/* Rest reserved. */
/** @} */
/** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
* @{
*/
#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT 0
#define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN 1
/** @} */
/** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
* @{
*/
#define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX 0
#define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM 1
/** @} */
/** @name VMX_EXIT_APIC_ACCESS
* @{
*/
/** 0-11: If the APIC-access VM exit is due to a linear access, the offset of access within the APIC page. */
#define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a) (a & 0xfff)
/** 12-15: Access type. */
/* Rest reserved. */
/** @} */
/** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE; access types
* @{
*/
/** Linear read access. */
#define VMX_APIC_ACCESS_TYPE_LINEAR_READ 0
/** Linear write access. */
#define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE 1
/** Linear instruction fetch access. */
#define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH 2
#define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY 10
/** Physical access for an instruction fetch or during instruction execution. */
#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR 15
/** @} */
/** @} */
/** @name VMCS field encoding - Natural width guest state fields
* @{
*/
#define VMX_VMCS_GUEST_CR0 0x6800
#define VMX_VMCS_GUEST_CR3 0x6802
#define VMX_VMCS_GUEST_CR4 0x6804
#define VMX_VMCS_GUEST_ES_BASE 0x6806
#define VMX_VMCS_GUEST_CS_BASE 0x6808
#define VMX_VMCS_GUEST_SS_BASE 0x680A
#define VMX_VMCS_GUEST_DS_BASE 0x680C
#define VMX_VMCS_GUEST_FS_BASE 0x680E
#define VMX_VMCS_GUEST_GS_BASE 0x6810
#define VMX_VMCS_GUEST_LDTR_BASE 0x6812
#define VMX_VMCS_GUEST_TR_BASE 0x6814
#define VMX_VMCS_GUEST_GDTR_BASE 0x6816
#define VMX_VMCS_GUEST_IDTR_BASE 0x6818
#define VMX_VMCS_GUEST_DR7 0x681A
#define VMX_VMCS_GUEST_RSP 0x681C
#define VMX_VMCS_GUEST_RIP 0x681E
#define VMX_VMCS_GUEST_RFLAGS 0x6820
#define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x6822
/** @} */
/** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS
* @{
*/
/** Hardware breakpoint 0 was met. */
#define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_B0 RT_BIT(0)
/** Hardware breakpoint 1 was met. */
/** Hardware breakpoint 2 was met. */
/** Hardware breakpoint 3 was met. */
/** At least one data or IO breakpoint was hit. */
/** A debug exception would have been triggered by single-step execution mode. */
/** Bits 4-11, 13 and 15-63 are reserved. */
/** @} */
/** @name VMCS field encoding - Natural width host state fields
* @{
*/
#define VMX_VMCS_HOST_CR0 0x6C00
#define VMX_VMCS_HOST_CR3 0x6C02
#define VMX_VMCS_HOST_CR4 0x6C04
#define VMX_VMCS_HOST_FS_BASE 0x6C06
#define VMX_VMCS_HOST_GS_BASE 0x6C08
#define VMX_VMCS_HOST_TR_BASE 0x6C0A
#define VMX_VMCS_HOST_GDTR_BASE 0x6C0C
#define VMX_VMCS_HOST_IDTR_BASE 0x6C0E
#define VMX_VMCS_HOST_SYSENTER_ESP 0x6C10
#define VMX_VMCS_HOST_SYSENTER_EIP 0x6C12
#define VMX_VMCS_HOST_RSP 0x6C14
#define VMX_VMCS_HOST_RIP 0x6C16
/** @} */
/** @} */
# define __STR(x) #x
#endif
/** @defgroup grp_vmx_asm vmx assembly helpers
* @ingroup grp_vmx
* @{
*/
/**
* Executes VMXON
*
* @returns VBox status code
* @param pVMXOn Physical address of VMXON structure
*/
#else
{
int rc = VINF_SUCCESS;
"push %3 \n\t"
"push %2 \n\t"
".byte 0xF3, 0x0F, 0xC7, 0x34, 0x24 # VMXON [esp] \n\t"
"ja 2f \n\t"
"je 1f \n\t"
"jmp 2f \n\t"
"1: \n\t"
"2: \n\t"
"add $8, %%esp \n\t"
:"=rm"(rc)
:"0"(VINF_SUCCESS),
:"memory"
);
# else
{
_emit 0xF3
_emit 0x0F
_emit 0xC7
_emit 0x34
}
# endif
return rc;
}
#endif
/**
* Executes VMXOFF
*/
DECLASM(void) VMXDisable(void);
#else
DECLINLINE(void) VMXDisable(void)
{
".byte 0x0F, 0x01, 0xC4 # VMXOFF \n\t"
);
# else
{
_emit 0x0F
_emit 0x01
}
# endif
}
#endif
/**
* Executes VMCLEAR
*
* @returns VBox status code
* @param pVMCS Physical address of VM control structure
*/
#else
{
int rc = VINF_SUCCESS;
"push %3 \n\t"
"push %2 \n\t"
".byte 0x66, 0x0F, 0xC7, 0x34, 0x24 # VMCLEAR [esp] \n\t"
"jnc 1f \n\t"
"1: \n\t"
"add $8, %%esp \n\t"
:"=rm"(rc)
:"0"(VINF_SUCCESS),
:"memory"
);
# else
{
_emit 0x66
_emit 0x0F
_emit 0xC7
_emit 0x34
}
# endif
return rc;
}
#endif
/**
* Executes VMPTRLD
*
* @returns VBox status code
* @param pVMCS Physical address of VMCS structure
*/
#else
{
int rc = VINF_SUCCESS;
"push %3 \n\t"
"push %2 \n\t"
".byte 0x0F, 0xC7, 0x34, 0x24 # VMPTRLD [esp] \n\t"
"jnc 1f \n\t"
"1: \n\t"
"add $8, %%esp \n\t"
:"=rm"(rc)
:"0"(VINF_SUCCESS),
);
# else
{
_emit 0x0F
_emit 0xC7
_emit 0x34
}
# endif
return rc;
}
#endif
/**
* Executes VMPTRST
*
* @returns VBox status code
* @param pVMCS Address that will receive the current pointer
*/
/**
* Executes VMWRITE
*
* @returns VBox status code
* @param idxField VMCS index
* @param u32Val 32 bits value
*/
#else
{
int rc = VINF_SUCCESS;
".byte 0x0F, 0x79, 0xC2 # VMWRITE eax, edx \n\t"
"ja 2f \n\t"
"je 1f \n\t"
"jmp 2f \n\t"
"1: \n\t"
"2: \n\t"
:"=rm"(rc)
:"0"(VINF_SUCCESS),
"a"(idxField),
"d"(u32Val)
);
# else
{
_emit 0x0F
_emit 0x79
_emit 0x04
}
# endif
return rc;
}
#endif
/**
* Executes VMWRITE
*
* @returns VBox status code
* @param idxField VMCS index
* @param u64Val 16, 32 or 64 bits value
*/
#else
#endif
#if HC_ARCH_BITS == 64
#define VMXWriteVmcs VMXWriteVmcs64
#else
#define VMXWriteVmcs VMXWriteVmcs32
#endif /* HC_ARCH_BITS == 64 */
/**
* Invalidate a page using invept
* @returns VBox status code
* @param enmFlush Type of flush
* @param pDescriptor Descriptor
*/
/**
* Invalidate a page using invvpid
* @returns VBox status code
* @param enmFlush Type of flush
* @param pDescriptor Descriptor
*/
/**
* Executes VMREAD
*
* @returns VBox status code
* @param idxField VMCS index
* @param pData Ptr to store VM field value
*/
#else
{
int rc = VINF_SUCCESS;
".byte 0x0F, 0x78, 0xc2 # VMREAD eax, edx \n\t"
"ja 2f \n\t"
"je 1f \n\t"
"jmp 2f \n\t"
"1: \n\t"
"2: \n\t"
:"=&r"(rc),
"=d"(*pData)
:"a"(idxField),
"d"(0)
);
# else
{
_emit 0x0F
_emit 0x78
_emit 0x04
}
# endif
return rc;
}
#endif
/**
* Executes VMREAD
*
* @returns VBox status code
* @param idxField VMCS index
* @param pData Ptr to store VM field value
*/
#else
{
int rc;
return rc;
}
#endif
# if HC_ARCH_BITS == 64
# define VMXReadVmcs VMXReadVmcs64
# else
# define VMXReadVmcs VMXReadVmcs32
# endif
/**
* Gets the last instruction error value from the current VMCS
*
* @returns error value
*/
{
#if HC_ARCH_BITS == 64
uint64_t uLastError = 0;
return (uint32_t)uLastError;
#else /* 32-bit host: */
uint32_t uLastError = 0;
return uLastError;
#endif
}
#ifdef IN_RING0
#endif /* IN_RING0 */
/** @} */
#endif