cpum.h revision ecb98c0e709a5cebd8877fb39f61a821804024bc
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * CPUM - CPU Monitor(/ Manager).
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Copyright (C) 2006-2013 Oracle Corporation
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * available from http://www.virtualbox.org. This file is free software;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * you can redistribute it and/or modify it under the terms of the GNU
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * General Public License (GPL) as published by the Free Software
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * The contents of this file may alternatively be used under the terms
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * of the Common Development and Distribution License Version 1.0
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * VirtualBox OSE distribution, in which case the provisions of the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * CDDL are applicable instead of those of the GPL.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * You may elect to license modified versions of this file under the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * terms and conditions of either the GPL or the CDDL or both.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @defgroup grp_cpum The CPU Monitor / Manager API
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * CPUID feature to set or clear.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The APIC feature bit. (Std+Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The sysenter/sysexit feature bit. (Std) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The PAE feature bit. (Std+Ext) */
24986763e9e9e6633a4a54479be945d577fdfd34vboxsync /** The NX feature bit. (Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The LONG MODE feature bit. (Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The PAT feature bit. (Std+Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The x2APIC feature bit. (Std) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The RDTSCP feature bit. (Ext) */
99fc25fde31ac60ee18ac48eab7027dea4272a0bvboxsync /** The Hypervisor Present bit. (Std) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** 32bit hackishness. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * CPU Vendor.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** 32bit hackishness. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * X86 and AMD64 CPU microarchitectures and in processor generations.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * @remarks The separation here is sometimes a little bit too finely grained,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * and the differences is more like processor generation than micro
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * arch. This can be useful, so we'll provide functions for getting at
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * more coarse grained info.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
dbca5bd5e2f9d025c280c2f040518de4e93ff58dvboxsync kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Predicate macro for catching netburst CPUs. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Predicate macro for catching Core7 CPUs. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
83d61602c6968041692aa7203ee51c4085c7e460vboxsync/** Predicate macro for catching AMD Family OFh CPUs (aka K8). */
83d61602c6968041692aa7203ee51c4085c7e460vboxsync#define CPUMMICROARCH_IS_AMD_FAM_0FH(a_enmMicroarch) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * decendants). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Predicate macro for catching AMD Family 16H CPUs. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * CPUID leaf.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The leaf number. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The sub-leaf number. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The EAX value. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The EBX value. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The ECX value. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The EDX value. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** Flags. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Pointer to a CPUID leaf. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Pointer to a const CPUID leaf. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** @name CPUMCPUIDLEAF::fFlags
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Indicates that ECX (the sub-leaf indicator) doesn't change when
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * requesting the final leaf and all undefined leaves that follows it.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Observed for 0x0000000b on Intel. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync#define CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED RT_BIT_32(0)
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Method used to deal with unknown CPUID leafs.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** Invalid zero value. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** Use given default values (DefCpuId). */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** Return the last standard leaf.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Intel Sandy Bridge has been observed doing this. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** Return the last standard leaf, with ecx observed.
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync * Intel Sandy Bridge has been observed doing this. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** The register values are passed thru unmodified. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** End of valid value. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync /** Ensure 32-bit type. */
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsync/** Pointer to unknown CPUID leaf method. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @name Guest Register Getters.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
d9e8985b936caa8e72f58c48045478fc2776dc5evboxsyncVMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @name Guest Register Setters.
eb30b3bfcb8b0e55f5498ba7a84e55a536debcd7vboxsyncVMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
eb30b3bfcb8b0e55f5498ba7a84e55a536debcd7vboxsyncVMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
559419830ee63b8481ade36d8994f235932aae49vboxsyncVMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
559419830ee63b8481ade36d8994f235932aae49vboxsyncVMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @name Misc Guest Predicate Functions.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
e69378448f919940b0b999796d40a23df2a7aa39vboxsyncVMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
26f38400c03761b1934b05fa93a64188e88e9904vboxsyncVMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tests if the guest is running in real mode or not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns true if in real mode, otherwise false.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Current CPU context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
e69378448f919940b0b999796d40a23df2a7aa39vboxsync * Tests if the guest is running in real or virtual 8086 mode.
e69378448f919940b0b999796d40a23df2a7aa39vboxsync * @returns @c true if it is, @c false if not.
e69378448f919940b0b999796d40a23df2a7aa39vboxsync * @param pCtx Current CPU context
56fa1b550cbdeec7ef620d566155a388c04ca796vboxsyncDECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
acf97addaaed7b946d412cfcff46547ba7cb33bfvboxsync || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
b40ca073ac6b445a7a49aa6b15fca3c2a26f97a9vboxsync * Tests if the guest is running in virtual 8086 mode.
b40ca073ac6b445a7a49aa6b15fca3c2a26f97a9vboxsync * @returns @c true if it is, @c false if not.
b40ca073ac6b445a7a49aa6b15fca3c2a26f97a9vboxsync * @param pCtx Current CPU context
b40ca073ac6b445a7a49aa6b15fca3c2a26f97a9vboxsyncDECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tests if the guest is running in paged protected or not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns true if in paged protected mode, otherwise false.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM handle.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tests if the guest is running in long mode or not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns true if in long mode, otherwise false.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Current CPU context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLINLINE(bool) CPUMIsGuestInLongModeEx(PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
559419830ee63b8481ade36d8994f235932aae49vboxsyncVMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tests if the guest is running in 64 bits mode or not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns true if in 64 bits protected mode, otherwise false.
559419830ee63b8481ade36d8994f235932aae49vboxsync * @param pVCpu The current virtual CPU.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Current CPU context
559419830ee63b8481ade36d8994f235932aae49vboxsyncDECLINLINE(bool) CPUMIsGuestIn64BitCodeEx(PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return false;
26f38400c03761b1934b05fa93a64188e88e9904vboxsync if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(NULL, &pCtx->cs))
886d0ed1f0aa2e75c92140ca240345679d617e4cvboxsync * Tests if the guest has paging enabled or not.
886d0ed1f0aa2e75c92140ca240345679d617e4cvboxsync * @returns true if paging is enabled, otherwise false.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Current CPU context
886d0ed1f0aa2e75c92140ca240345679d617e4cvboxsyncDECLINLINE(bool) CPUMIsGuestPagingEnabledEx(PCPUMCTX pCtx)
886d0ed1f0aa2e75c92140ca240345679d617e4cvboxsync * Tests if the guest is running in PAE mode or not.
886d0ed1f0aa2e75c92140ca240345679d617e4cvboxsync * @returns true if in PAE mode, otherwise false.
f3fd5f0cfee6865de86bef793a549083d37edd4fvboxsync * @param pCtx Current CPU context
886d0ed1f0aa2e75c92140ca240345679d617e4cvboxsyncDECLINLINE(bool) CPUMIsGuestInPAEModeEx(PCPUMCTX pCtx)
873db999b6c8aa54ad92544e8a82d7cee26f87bfvboxsync /* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
873db999b6c8aa54ad92544e8a82d7cee26f87bfvboxsync than EFER.LME as it reflects if the CPU has entered paging with EFER.LME set. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* VBOX_WITHOUT_UNNAMED_UNIONS */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @name Hypervisor Register Getters.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#if 0 /* these are not correct. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** This register is only saved on fatal traps. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** This register is only saved on fatal traps. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** This register is only saved on fatal traps. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMGetHyperCtx(PVMCPU pVCpu, PCPUMCTX pCtx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @name Hypervisor Register Setters.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelDS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelDS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelDS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP);
3942acfaf590eaef4740d7b8a5311bb91e2bed0dvboxsyncVMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetHyperCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
45b7b06f3c4ef53f499c355505010a2b050802f4vboxsyncVMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu, uint8_t iGstReg, bool fForceHyper);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMPushHyper(PVMCPU pVCpu, uint32_t u32);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMQueryHyperCtxPtr(PVMCPU pVCpu, PCPUMCTX *ppCtx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu);
682342827b0e80c493c820603508e79e76c42658vboxsyncVMM_INT_DECL(int) CPUMRawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
682342827b0e80c493c820603508e79e76c42658vboxsyncVMM_INT_DECL(int) CPUMRawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc);
8cb8cf7eeafbf2ad5b23866ca19f257bd3aaf9e7vboxsyncVMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl);
53799e1f1f6601cd3d6be95ff1aa8d3648712618vboxsync/** @name Changed flags.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * These flags are used to keep track of which important register that
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * have been changed since last they were reset. The only one allowed
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * to clear them is REM!
53799e1f1f6601cd3d6be95ff1aa8d3648712618vboxsync#define CPUM_CHANGED_TR RT_BIT(8) /**@< Currently unused. */
53799e1f1f6601cd3d6be95ff1aa8d3648712618vboxsync#define CPUM_CHANGED_HIDDEN_SEL_REGS RT_BIT(10) /**@< Currently unused. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels);
79883babb0e5b9c7397c304d576bfc29282542afvboxsyncVMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu);
22646c9d8a83d8fd3f164563f0141636fcc5a71bvboxsyncVMMDECL(bool) CPUMIsGuestDebugStateActivePending(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
22646c9d8a83d8fd3f164563f0141636fcc5a71bvboxsyncVMMDECL(bool) CPUMIsHyperDebugStateActivePending(PVMCPU pVCpu);
681380880d4131019871e8f22cb3349b757168cavboxsyncVMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu);
681380880d4131019871e8f22cb3349b757168cavboxsyncVMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu);
ecb98c0e709a5cebd8877fb39f61a821804024bcvboxsyncVMMDECL(uint64_t) CPUMGetGuestScalableBusFrequency(PVM pVM);
ecb98c0e709a5cebd8877fb39f61a821804024bcvboxsync/** @name Typical scalable bus frequency values.
ecb98c0e709a5cebd8877fb39f61a821804024bcvboxsync/** Special internal value indicating that we don't know the frequency.
ecb98c0e709a5cebd8877fb39f61a821804024bcvboxsync * @internal */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @defgroup grp_cpum_r3 The CPU Monitor(/Manager) API
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @ingroup grp_cpum
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUKNOWNCPUID enmUnknownMethod);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
41d680dd6eb0287afc200adc5b0d61b07a32b72dvboxsyncVMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* IN_RING3 */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @defgroup grp_cpum_gc The CPU Monitor(/Manager) API
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @ingroup grp_cpum
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Calls a guest trap/interrupt handler directly
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Assumes a trap stack frame has already been setup on the guest's stack!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This function does not return!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pRegFrame Original trap/interrupt context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param selCS Code selector of handler
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pHandler GC virtual address of handler
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param eflags Callee's EFLAGS
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param selSS Stack selector for handler
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pEsp Stack address for handler
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Call guest V86 code directly.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This function does not return!
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pRegFrame Original trap/interrupt context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLASM(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
7ce6e7e8fb0eddb176361a49f53fa1bd15eaab4evboxsyncVMMDECL(uint32_t) CPUMRCGetGuestCPL(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
7847c123aebebc6d3d5c1406619cfba1ab6457c1vboxsyncVMMDECL(void) CPUMRCRecheckRawState(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* IN_RC */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @defgroup grp_cpum_r0 The CPU Monitor(/Manager) API
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @ingroup grp_cpum
c3ad07071523338d76960d8da7678860aea8b03dvboxsyncVMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
47e2ddf908aebbc4adbc758d46a6266a4c9c5051vboxsyncVMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
47e2ddf908aebbc4adbc758d46a6266a4c9c5051vboxsyncVMMR0_INT_DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
47e2ddf908aebbc4adbc758d46a6266a4c9c5051vboxsyncVMMR0_INT_DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu);
47e2ddf908aebbc4adbc758d46a6266a4c9c5051vboxsyncVMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6);
47e2ddf908aebbc4adbc758d46a6266a4c9c5051vboxsyncVMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6);
47e2ddf908aebbc4adbc758d46a6266a4c9c5051vboxsyncVMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6);
47e2ddf908aebbc4adbc758d46a6266a4c9c5051vboxsyncVMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6);
6cac05f856d982151579a9d445a109960c2c07d2vboxsyncVMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, RTCPUID idHostCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#endif /* IN_RING0 */