cpum.h revision dbca5bd5e2f9d025c280c2f040518de4e93ff58d
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * CPUM - CPU Monitor(/ Manager).
a5f17f2682f4e8ed08ffca84a036028533ea8f16vboxsync * Copyright (C) 2006-2013 Oracle Corporation
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * available from http://www.virtualbox.org. This file is free software;
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * you can redistribute it and/or modify it under the terms of the GNU
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * General Public License (GPL) as published by the Free Software
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * The contents of this file may alternatively be used under the terms
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * of the Common Development and Distribution License Version 1.0
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * VirtualBox OSE distribution, in which case the provisions of the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * CDDL are applicable instead of those of the GPL.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * You may elect to license modified versions of this file under the
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * terms and conditions of either the GPL or the CDDL or both.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @defgroup grp_cpum The CPU Monitor / Manager API
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * CPUID feature to set or clear.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The APIC feature bit. (Std+Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The sysenter/sysexit feature bit. (Std) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The SYSCALL/SYSEXIT feature bit (64 bits mode only for Intel CPUs). (Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The PAE feature bit. (Std+Ext) */
24986763e9e9e6633a4a54479be945d577fdfd34vboxsync /** The NX feature bit. (Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The LAHF/SAHF feature bit (64 bits mode only). (Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The LONG MODE feature bit. (Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The PAT feature bit. (Std+Ext) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The x2APIC feature bit. (Std) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The RDTSCP feature bit. (Ext) */
99fc25fde31ac60ee18ac48eab7027dea4272a0bvboxsync /** The Hypervisor Present bit. (Std) */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** 32bit hackishness. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * CPU Vendor.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** 32bit hackishness. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * X86 and AMD64 CPU microarchitectures and in processor generations.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @remarks The separation here is sometimes a little bit too finely grained,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * and the differences is more like processor generation than micro
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * arch. This can be useful, so we'll provide functions for getting at
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * more coarse grained info.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_8086 = kCpumMicroarch_Intel_First,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_P6 = kCpumMicroarch_Intel_P6_Core_Atom_First,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_Core_Yonah, /**< Core, also known as Enhanced Pentium M. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_Core2_Merom = kCpumMicroarch_Intel_Core2_First,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_Core7_Nehalem = kCpumMicroarch_Intel_Core7_First,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_Atom_Bonnell = kCpumMicroarch_Intel_Atom_First,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_Atom_Lincroft, /**< Second generation bonnell (44nm). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_Atom_Saltwell, /**< 32nm shrink of Bonnell. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_NB_Willamette = kCpumMicroarch_Intel_NB_First, /**< 180nm */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Intel_NB_Gallatin, /**< 90nm Xeon, Pentium 4 Extreme Edition ("Emergency Edition"). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_AMD_Am286 = kCpumMicroarch_AMD_First,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_AMD_Am486Enh, /**< Covers Am5x86 as well. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_AMD_K7_Palomino = kCpumMicroarch_AMD_K7_First,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_AMD_K8_130nm = kCpumMicroarch_AMD_K8_First, /**< 130nm Clawhammer, Sledgehammer, Newcastle, Paris, Odessa, Dublin */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_AMD_K8_90nm_DualCore, /**< 90nm with two cores. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_AMD_K8_90nm_AMDV, /**< 90nm with AMD-V (usually) and two cores (usually). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_AMD_15h_Bulldozer = kCpumMicroarch_AMD_15h_First,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_AMD_15h_Steamroller, /**< Yet to be released, might have different family. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_AMD_15h_Excavator, /**< Yet to be released, might have different family. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Centaur_C6 = kCpumMicroarch_VIA_First,
e69378448f919940b0b999796d40a23df2a7aa39vboxsync kCpumMicroarch_VIA_C3_C5A, /**< 180nm Samuel - Cyrix III, C3, 1GigaPro. */
e69378448f919940b0b999796d40a23df2a7aa39vboxsync kCpumMicroarch_VIA_C3_C5B, /**< 150nm Samuel 2 - Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+. */
e69378448f919940b0b999796d40a23df2a7aa39vboxsync kCpumMicroarch_VIA_C3_C5C, /**< 130nm Ezra - C3, Eden ESP. */
e69378448f919940b0b999796d40a23df2a7aa39vboxsync kCpumMicroarch_VIA_C3_C5N, /**< 130nm Ezra-T - C3. */
e69378448f919940b0b999796d40a23df2a7aa39vboxsync kCpumMicroarch_VIA_C3_C5XL, /**< 130nm Nehemiah - C3, Eden ESP, Eden-N. */
56fa1b550cbdeec7ef620d566155a388c04ca796vboxsync kCpumMicroarch_VIA_C3_C5P, /**< 130nm Nehemiah+ - C3. */
e69378448f919940b0b999796d40a23df2a7aa39vboxsync kCpumMicroarch_VIA_C7_C5J, /**< 90nm Esther - C7, C7-D, C7-M, Eden, Eden ULV. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync kCpumMicroarch_Cyrix_5x86 = kCpumMicroarch_Cyrix_First,
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Predicate macro for catching netburst CPUs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#define CPUMMICROARCH_IS_INTEL_NETBURST(a_enmMicroarch) \
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ((a_enmMicroarch) >= kCpumMicroarch_Intel_NB_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_NB_End)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Predicate macro for catching Core7 CPUs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#define CPUMMICROARCH_IS_INTEL_CORE7(a_enmMicroarch) \
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ((a_enmMicroarch) >= kCpumMicroarch_Intel_Core7_First && (a_enmMicroarch) <= kCpumMicroarch_Intel_Core7_End)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Predicate macro for catching AMD Family 8H CPUs (aka K8). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#define CPUMMICROARCH_IS_AMD_FAM_8H(a_enmMicroarch) \
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ((a_enmMicroarch) >= kCpumMicroarch_AMD_K8_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_K8_End)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Predicate macro for catching AMD Family 10H CPUs (aka K10). */
559419830ee63b8481ade36d8994f235932aae49vboxsync#define CPUMMICROARCH_IS_AMD_FAM_10H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Predicate macro for catching AMD Family 11H CPUs (aka Lion). */
559419830ee63b8481ade36d8994f235932aae49vboxsync#define CPUMMICROARCH_IS_AMD_FAM_11H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Lion)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Predicate macro for catching AMD Family 12H CPUs (aka Llano). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#define CPUMMICROARCH_IS_AMD_FAM_12H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_K10_Llano)
559419830ee63b8481ade36d8994f235932aae49vboxsync/** Predicate macro for catching AMD Family 14H CPUs (aka Bobcat). */
37fb67be7d1d328213aeda3f56ab5aacd37416d1vboxsync#define CPUMMICROARCH_IS_AMD_FAM_14H(a_enmMicroarch) ((a_enmMicroarch) == kCpumMicroarch_AMD_Bobcat)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Predicate macro for catching AMD Family 15H CPUs (bulldozer and it's
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * decendants). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#define CPUMMICROARCH_IS_AMD_FAM_15H(a_enmMicroarch) \
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ((a_enmMicroarch) >= kCpumMicroarch_AMD_15h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_15h_End)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Predicate macro for catching AMD Family 16H CPUs. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#define CPUMMICROARCH_IS_AMD_FAM_16H(a_enmMicroarch) \
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync ((a_enmMicroarch) >= kCpumMicroarch_AMD_16h_First && (a_enmMicroarch) <= kCpumMicroarch_AMD_16h_End)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * CPUID leaf.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The leaf number. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The sub-leaf number. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Sub-leaf mask. This is 0 when sub-leaves aren't used. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The EAX value. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The EBX value. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The ECX value. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The EDX value. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Flags. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Pointer to a CPUID leaf. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Pointer to a const CPUID leaf. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @name CPUMCPUIDLEAF::fFlags
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Indicates that ECX (the sub-leaf indicator) doesn't change when
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * requesting the final leaf and all undefined leaves that follows it.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Observed for 0x0000000b on Intel. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync#define CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED RT_BIT_32(0)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Method used to deal with unknown CPUID leafs.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Invalid zero value. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Use given default values (DefCpuId). */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Return the last standard leaf.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Intel Sandy Bridge has been observed doing this. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Return the last standard leaf, with ecx observed.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Intel Sandy Bridge has been observed doing this. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** The register values are passed thru unmodified. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** End of valid value. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync /** Ensure 32-bit type. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** Pointer to unknown CPUID leaf method. */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @name Guest Register Getters.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM);
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsyncVMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsyncVMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsyncVMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM);
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsyncVMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM);
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsync/** @name Guest Register Setters.
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsyncVMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsyncVMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit);
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsyncVMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr);
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsyncVMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr);
db946a685afcb5cfb59b1342a2fc637fc0c04c50vboxsyncVMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp);
7a896688c49bde3fa1490e7ebb321ac51b6ad29dvboxsyncVMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(void) CPUMSetGuestCtx(PVMCPU pVCpu, const PCPUMCTX pCtx);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0_INT_DECL(void) CPUMR0SetGuestTscAux(PVMCPU pVCpu, uint64_t uValue);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMR0_INT_DECL(uint64_t) CPUMR0GetGuestTscAux(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync/** @name Misc Guest Predicate Functions.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncVMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tests if the guest is running in real mode or not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns true if in real mode, otherwise false.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Current CPU context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLINLINE(bool) CPUMIsGuestInRealModeEx(PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tests if the guest is running in real or virtual 8086 mode.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns @c true if it is, @c false if not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Current CPU context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLINLINE(bool) CPUMIsGuestInRealOrV86ModeEx(PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync || pCtx->eflags.Bits.u1VM; /* Cannot be set in long mode. Intel spec 2.3.1 "System Flags and Fields in IA-32e Mode". */
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tests if the guest is running in virtual 8086 mode.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns @c true if it is, @c false if not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Current CPU context
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLINLINE(bool) CPUMIsGuestInV86ModeEx(PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tests if the guest is running in paged protected or not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns true if in paged protected mode, otherwise false.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pVM The VM handle.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsyncDECLINLINE(bool) CPUMIsGuestInPagedProtectedModeEx(PCPUMCTX pCtx)
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync return (pCtx->cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * Tests if the guest is running in long mode or not.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @returns true if in long mode, otherwise false.
0b74a2f80aba476dc8be8bc1c63891fc53945986vboxsync * @param pCtx Current CPU context
/* Intel mentions EFER.LMA and EFER.LME in different parts of their spec. We shall use EFER.LMA rather
VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX);
| CPUM_CHANGED_CR0 \
| CPUM_CHANGED_CR4 \
| CPUM_CHANGED_CR3 \
| CPUM_CHANGED_TR \
#ifdef IN_RING3
VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown);
VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
#ifdef IN_RC
#ifdef VBOX_WITH_RAW_RING1
#ifdef IN_RING0