1450N/A/*
1450N/A * Copyright (c) 2008, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A#ifndef __RADEON_IO32_H__
1450N/A#define __RADEON_IO32_H__
1450N/A
1450N/A
1450N/A#ifdef _MULTI_DATAMODEL
1450N/A/*
1450N/A * For radeon_cp_init()
1450N/A */
1450N/Atypedef struct drm_radeon_init_32 {
1450N/A int func;
1450N/A unsigned int sarea_priv_offset;
1450N/A int is_pci; /* for overriding only */
1450N/A int cp_mode;
1450N/A int gart_size;
1450N/A int ring_size;
1450N/A int usec_timeout;
1450N/A
1450N/A unsigned int fb_bpp;
1450N/A unsigned int front_offset, front_pitch;
1450N/A unsigned int back_offset, back_pitch;
1450N/A unsigned int depth_bpp;
1450N/A unsigned int depth_offset, depth_pitch;
1450N/A
1450N/A unsigned int fb_offset DEPRECATED;
1450N/A unsigned int mmio_offset DEPRECATED;
1450N/A unsigned int ring_offset;
1450N/A unsigned int ring_rptr_offset;
1450N/A unsigned int buffers_offset;
1450N/A unsigned int gart_textures_offset;
1450N/A} drm_radeon_init_32_t;
1450N/A
1450N/A/*
1450N/A * radeon_cp_buffers()
1450N/A */
1450N/Atypedef struct drm_dma_32 {
1450N/A int context;
1450N/A int send_count;
1450N/A uint32_t send_indices;
1450N/A uint32_t send_sizes;
1450N/A drm_dma_flags_t flags;
1450N/A int request_count;
1450N/A int request_size;
1450N/A uint32_t request_indices;
1450N/A uint32_t request_sizes;
1450N/A int granted_count;
1450N/A} drm_dma_32_t;
1450N/A
1450N/A/*
1450N/A * drm_radeon_clear()
1450N/A */
1450N/Atypedef struct drm_radeon_clear_32 {
1450N/A unsigned int flags;
1450N/A unsigned int clear_color;
1450N/A unsigned int clear_depth;
1450N/A unsigned int color_mask;
1450N/A unsigned int depth_mask;
1450N/A uint32_t depth_boxes;
1450N/A} drm_radeon_clear_32_t;
1450N/A
1450N/A/*
1450N/A * For radeon_cp_texture()
1450N/A */
1450N/Atypedef struct drm_radeon_tex_image_32 {
1450N/A unsigned int x, y;
1450N/A unsigned int width, height;
1450N/A uint32_t data;
1450N/A} drm_radeon_tex_image_32_t;
1450N/A
1450N/Atypedef struct drm_radeon_texture_32 {
1450N/A unsigned int offset;
1450N/A int pitch;
1450N/A int format;
1450N/A int width;
1450N/A int height;
1450N/A uint32_t image;
1450N/A} drm_radeon_texture_32_t;
1450N/A
1450N/A/*
1450N/A * for radeon_cp_stipple()
1450N/A */
1450N/Atypedef struct drm_radeon_stipple_32 {
1450N/A uint32_t mask;
1450N/A} drm_radeon_stipple_32_t;
1450N/A
1450N/A/*
1450N/A * radeon_cp_vertex2()
1450N/A */
1450N/Atypedef struct drm_radeon_vertex2_32 {
1450N/A int idx;
1450N/A int discard;
1450N/A int nr_states;
1450N/A uint32_t state;
1450N/A int nr_prims;
1450N/A uint32_t prim;
1450N/A} drm_radeon_vertex2_32_t;
1450N/A
1450N/A/*
1450N/A * radeon_cp_cmdbuf()
1450N/A */
1450N/Atypedef struct drm_radeon_kcmd_buffer_32 {
1450N/A int bufsz;
1450N/A uint32_t buf;
1450N/A int nbox;
1450N/A uint32_t boxes;
1450N/A} drm_radeon_kcmd_buffer_32_t;
1450N/A
1450N/A/*
1450N/A * radeon_cp_getparam()
1450N/A */
1450N/Atypedef struct drm_radeon_getparam_32 {
1450N/A int param;
1450N/A uint32_t value;
1450N/A} drm_radeon_getparam_32_t;
1450N/A
1450N/A
1450N/A/*
1450N/A * radeon_mem_alloc()
1450N/A */
1450N/Atypedef struct drm_radeon_mem_alloc_32 {
1450N/A int region;
1450N/A int alignment;
1450N/A int size;
1450N/A uint32_t region_offset; /* offset from start of fb or GART */
1450N/A} drm_radeon_mem_alloc_32_t;
1450N/A
1450N/A
1450N/A/*
1450N/A * radeon_irq_emit()
1450N/A */
1450N/Atypedef struct drm_radeon_irq_emit_32 {
1450N/A uint32_t irq_seq;
1450N/A} drm_radeon_irq_emit_32_t;
1450N/A
1450N/A
1450N/A/*
1450N/A * radeon_cp_setparam()
1450N/A */
1450N/A#pragma pack(1)
1450N/Atypedef struct drm_radeon_setparam_32 {
1450N/A unsigned int param;
1450N/A uint64_t value;
1450N/A} drm_radeon_setparam_32_t;
1450N/A#pragma pack()
1450N/A
1450N/A#endif /* _MULTI_DATAMODEL */
1450N/A#endif /* __RADEON_IO32_H__ */