radeon_drv.h revision 1450
1450N/A * radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
1450N/A#ifndef __RADEON_DRV_H__
1450N/A#define __RADEON_DRV_H__
1450N/A#define DRIVER_PATCHLEVEL 0
1450N/Aenum radeon_family {
1450N/Atypedef struct drm_radeon_freelist {
1450N/Atypedef struct drm_radeon_ring_buffer {
1450N/Atypedef struct drm_radeon_depth_clear_t {
1450N/Astruct drm_radeon_driver_file_fields {
1450N/A void *private_data;
1450N/Astruct radeon_surface {
1450N/Astruct radeon_virt_surface {
1450N/A int surface_index;
1450N/Atypedef struct drm_radeon_private {
1450N/A int new_memmap;
1450N/A unsigned long gart_buffers_offset;
1450N/A int cp_running;
1450N/A int writeback_works;
1450N/A int usec_timeout;
1450N/A int microcode_version;
1450N/A int freelist_timeouts;
1450N/A int freelist_loops;
1450N/A int requested_bufs;
1450N/A int last_frame_reads;
1450N/A int last_clear_reads;
1450N/A int texture_uploads;
1450N/A int page_flipping;
1450N/A int current_page;
1450N/A unsigned int front_offset;
1450N/A unsigned int front_pitch;
1450N/A unsigned int back_offset;
1450N/A unsigned int back_pitch;
1450N/A unsigned int depth_offset;
1450N/A unsigned int depth_pitch;
1450N/A unsigned long ring_offset;
1450N/A unsigned long ring_rptr_offset;
1450N/A unsigned long buffers_offset;
1450N/A unsigned long gart_textures_offset;
1450N/A int vblank_crtc;
1450N/A int irq_enabled;
1450N/A unsigned long pcigart_offset;
1450N/A void *private_data;
1450N/Atypedef struct drm_radeon_buf_priv {
1450N/Atypedef struct drm_radeon_kcmd_buffer {
1450N/Aextern int radeon_no_wb;
1450N/Aextern int radeon_max_ioctl;
1450N/A /* radeon_cp.c */
1450N/A /* radeon_irq.c */
1450N/A/* r300_cmdbuf.c */
1450N/Aextern void r300_init_reg_flags(void);
1450N/A#define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
1450N/A#define RADEON_FFACE_CULL_CW (0 << 0)
1450N/A#define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
1450N/A#define RADEON_PRE_WRITE_TIMER_SHIFT 0
1450N/A#define RADEON_PRIM_TYPE_NONE (0 << 0)
1450N/A#define RADEON_TXFORMAT_I8 0
1450N/A} while (__lintzero)
1450N/A} while (__lintzero)
1450N/A#define CP_PACKET2() \
1450N/A#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1450N/A} while (__lintzero)
1450N/A#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1450N/A} while (__lintzero)
1450N/A#define RADEON_WAIT_UNTIL_IDLE() do { \
1450N/A} while (__lintzero)
1450N/A#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1450N/A} while (__lintzero)
1450N/A#define RADEON_FLUSH_CACHE() do { \
1450N/A} while (__lintzero)
1450N/A#define RADEON_PURGE_CACHE() do { \
1450N/A} while (__lintzero)
1450N/A#define RADEON_FLUSH_ZCACHE() do { \
1450N/A} while (__lintzero)
1450N/A#define RADEON_PURGE_ZCACHE() do { \
1450N/A} while (__lintzero)
1450N/A} while (__lintzero)
1450N/A} while (__lintzero)
1450N/A} while (__lintzero)
1450N/A} while (__lintzero)
1450N/A} while (__lintzero)
1450N/A#define BEGIN_RING(n) do { \
1450N/A COMMIT_RING(); \
1450N/A} while (__lintzero)
1450N/A#define ADVANCE_RING() do { \
1450N/A} while (__lintzero)
1450N/A#define COMMIT_RING() do { \
1450N/A DRM_MEMORYBARRIER(); \
1450N/A} while (__lintzero)
1450N/A} while (__lintzero)
1450N/A} while (__lintzero)
1450N/A} while (__lintzero)