radeon_drm.h revision 1450
1450N/A/*
1450N/A * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A/*
1450N/A * radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
1450N/A *
1450N/A * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
1450N/A * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
1450N/A * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
1450N/A * All rights reserved.
1450N/A *
1450N/A * Permission is hereby granted, free of charge, to any person obtaining a
1450N/A * copy of this software and associated documentation files (the "Software"),
1450N/A * to deal in the Software without restriction, including without limitation
1450N/A * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1450N/A * and/or sell copies of the Software, and to permit persons to whom the
1450N/A * Software is furnished to do so, subject to the following conditions:
1450N/A *
1450N/A * The above copyright notice and this permission notice (including the next
1450N/A * paragraph) shall be included in all copies or substantial portions of the
1450N/A * Software.
1450N/A *
1450N/A * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1450N/A * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1450N/A * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1450N/A * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
1450N/A * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1450N/A * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
1450N/A * DEALINGS IN THE SOFTWARE.
1450N/A *
1450N/A * Authors:
1450N/A * Kevin E. Martin <martin@valinux.com>
1450N/A * Gareth Hughes <gareth@valinux.com>
1450N/A * Keith Whitwell <keith@tungstengraphics.com>
1450N/A */
1450N/A
1450N/A#ifndef __RADEON_DRM_H__
1450N/A#define __RADEON_DRM_H__
1450N/A
1450N/A/*
1450N/A * WARNING: If you change any of these defines, make sure to change the
1450N/A * defines in the X server file (radeon_sarea.h)
1450N/A */
1450N/A#ifndef __RADEON_SAREA_DEFINES__
1450N/A#define __RADEON_SAREA_DEFINES__
1450N/A
1450N/A/*
1450N/A * Old style state flags, required for sarea interface (1.1 and 1.2
1450N/A * clears) and 1.2 drm_vertex2 ioctl.
1450N/A */
1450N/A#define RADEON_UPLOAD_CONTEXT 0x00000001
1450N/A#define RADEON_UPLOAD_VERTFMT 0x00000002
1450N/A#define RADEON_UPLOAD_LINE 0x00000004
1450N/A#define RADEON_UPLOAD_BUMPMAP 0x00000008
1450N/A#define RADEON_UPLOAD_MASKS 0x00000010
1450N/A#define RADEON_UPLOAD_VIEWPORT 0x00000020
1450N/A#define RADEON_UPLOAD_SETUP 0x00000040
1450N/A#define RADEON_UPLOAD_TCL 0x00000080
1450N/A#define RADEON_UPLOAD_MISC 0x00000100
1450N/A#define RADEON_UPLOAD_TEX0 0x00000200
1450N/A#define RADEON_UPLOAD_TEX1 0x00000400
1450N/A#define RADEON_UPLOAD_TEX2 0x00000800
1450N/A#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
1450N/A#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
1450N/A#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
1450N/A#define RADEON_UPLOAD_CLIPRECTS 0x00008000
1450N/A /* handled client-side */
1450N/A#define RADEON_REQUIRE_QUIESCENCE 0x00010000
1450N/A#define RADEON_UPLOAD_ZBIAS 0x00020000
1450N/A /* version 1.2 and newer */
1450N/A#define RADEON_UPLOAD_ALL 0x003effff
1450N/A#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
1450N/A
1450N/A/*
1450N/A * New style per-packet identifiers for use in cmd_buffer ioctl with
1450N/A * the RADEON_EMIT_PACKET command. Comments relate new packets to old
1450N/A * state bits and the packet size:
1450N/A */
1450N/A#define RADEON_EMIT_PP_MISC 0 /* context/7 */
1450N/A#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
1450N/A#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
1450N/A#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
1450N/A#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
1450N/A#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
1450N/A#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
1450N/A#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
1450N/A#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
1450N/A#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
1450N/A#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
1450N/A#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
1450N/A#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
1450N/A#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
1450N/A#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
1450N/A#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
1450N/A#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
1450N/A#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
1450N/A#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
1450N/A#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
1450N/A#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
1450N/A#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
1450N/A#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
1450N/A#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
1450N/A#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
1450N/A#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
1450N/A#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
1450N/A#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
1450N/A#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
1450N/A#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
1450N/A#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
1450N/A#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
1450N/A#define R200_EMIT_VAP_CTL 32 /* vap/1 */
1450N/A#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
1450N/A#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
1450N/A#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
1450N/A#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
1450N/A#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
1450N/A#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
1450N/A#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
1450N/A#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
1450N/A#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
1450N/A#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
1450N/A#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
1450N/A#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
1450N/A#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
1450N/A#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
1450N/A#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
1450N/A#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
1450N/A#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
1450N/A#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
1450N/A#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
1450N/A#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
1450N/A#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
1450N/A#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
1450N/A#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
1450N/A#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
1450N/A#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
1450N/A#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
1450N/A#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
1450N/A#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
1450N/A#define R200_EMIT_PP_CUBIC_FACES_0 61
1450N/A#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
1450N/A#define R200_EMIT_PP_CUBIC_FACES_1 63
1450N/A#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
1450N/A#define R200_EMIT_PP_CUBIC_FACES_2 65
1450N/A#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
1450N/A#define R200_EMIT_PP_CUBIC_FACES_3 67
1450N/A#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
1450N/A#define R200_EMIT_PP_CUBIC_FACES_4 69
1450N/A#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
1450N/A#define R200_EMIT_PP_CUBIC_FACES_5 71
1450N/A#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
1450N/A#define RADEON_EMIT_PP_TEX_SIZE_0 73
1450N/A#define RADEON_EMIT_PP_TEX_SIZE_1 74
1450N/A#define RADEON_EMIT_PP_TEX_SIZE_2 75
1450N/A#define R200_EMIT_RB3D_BLENDCOLOR 76
1450N/A#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
1450N/A#define RADEON_EMIT_PP_CUBIC_FACES_0 78
1450N/A#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
1450N/A#define RADEON_EMIT_PP_CUBIC_FACES_1 80
1450N/A#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
1450N/A#define RADEON_EMIT_PP_CUBIC_FACES_2 82
1450N/A#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
1450N/A#define R200_EMIT_PP_TRI_PERF_CNTL 84
1450N/A#define R200_EMIT_PP_AFS_0 85
1450N/A#define R200_EMIT_PP_AFS_1 86
1450N/A#define R200_EMIT_ATF_TFACTOR 87
1450N/A#define R200_EMIT_PP_TXCTLALL_0 88
1450N/A#define R200_EMIT_PP_TXCTLALL_1 89
1450N/A#define R200_EMIT_PP_TXCTLALL_2 90
1450N/A#define R200_EMIT_PP_TXCTLALL_3 91
1450N/A#define R200_EMIT_PP_TXCTLALL_4 92
1450N/A#define R200_EMIT_PP_TXCTLALL_5 93
1450N/A#define R200_EMIT_VAP_PVS_CNTL 94
1450N/A#define RADEON_MAX_STATE_PACKETS 95
1450N/A
1450N/A/*
1450N/A * Commands understood by cmd_buffer ioctl. More can be added but
1450N/A * obviously these can't be removed or changed:
1450N/A */
1450N/A#define RADEON_CMD_PACKET 1
1450N/A /* emit one of the register packets above */
1450N/A#define RADEON_CMD_SCALARS 2 /* emit scalar data */
1450N/A#define RADEON_CMD_VECTORS 3 /* emit vector data */
1450N/A#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
1450N/A#define RADEON_CMD_PACKET3 5 /* emit hw packet */
1450N/A#define RADEON_CMD_PACKET3_CLIP 6
1450N/A /* emit hw packet wrapped in cliprects */
1450N/A#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
1450N/A
1450N/A/*
1450N/A * emit hw wait commands -- note:
1450N/A * doesn't make the cpu wait, just
1450N/A * the graphics hardware
1450N/A */
1450N/A#define RADEON_CMD_WAIT 8
1450N/A
1450N/A#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
1450N/Atypedef union {
1450N/A int i;
1450N/A struct {
1450N/A unsigned char cmd_type, pad0, pad1, pad2;
1450N/A } header;
1450N/A struct {
1450N/A unsigned char cmd_type, packet_id, pad0, pad1;
1450N/A } packet;
1450N/A struct {
1450N/A unsigned char cmd_type, offset, stride, count;
1450N/A } scalars;
1450N/A struct {
1450N/A unsigned char cmd_type, offset, stride, count;
1450N/A } vectors;
1450N/A struct {
1450N/A unsigned char cmd_type, addr_lo, addr_hi, count;
1450N/A } veclinear;
1450N/A struct {
1450N/A unsigned char cmd_type, buf_idx, pad0, pad1;
1450N/A } dma;
1450N/A struct {
1450N/A unsigned char cmd_type, flags, pad0, pad1;
1450N/A } wait;
1450N/A} drm_radeon_cmd_header_t;
1450N/A
1450N/A#define RADEON_WAIT_2D 0x1
1450N/A#define RADEON_WAIT_3D 0x2
1450N/A
1450N/A/* Allowed parameters for R300_CMD_PACKET3 */
1450N/A#define R300_CMD_PACKET3_CLEAR 0
1450N/A#define R300_CMD_PACKET3_RAW 1
1450N/A
1450N/A/*
1450N/A * Commands understood by cmd_buffer ioctl for R300.
1450N/A * The interface has not been stabilized, so some of these may be removed
1450N/A * and eventually reordered before stabilization.
1450N/A */
1450N/A#define R300_CMD_PACKET0 1
1450N/A#define R300_CMD_VPU 2 /* emit vertex program upload */
1450N/A#define R300_CMD_PACKET3 3 /* emit a packet3 */
1450N/A
1450N/A/* emit sequence ending 3d rendering */
1450N/A#define R300_CMD_END3D 4
1450N/A
1450N/A#define R300_CMD_CP_DELAY 5
1450N/A#define R300_CMD_DMA_DISCARD 6
1450N/A#define R300_CMD_WAIT 7
1450N/A#define R300_WAIT_2D 0x1
1450N/A#define R300_WAIT_3D 0x2
1450N/A#define R300_WAIT_2D_CLEAN 0x3
1450N/A#define R300_WAIT_3D_CLEAN 0x4
1450N/A#define R300_CMD_SCRATCH 8
1450N/A/*
1450N/A * sys/user.h defines u
1450N/A */
1450N/A
1450N/A#ifdef u
1450N/A#undef u
1450N/A#endif /* u */
1450N/A
1450N/A
1450N/Atypedef union {
1450N/A unsigned int u;
1450N/A struct {
1450N/A unsigned char cmd_type, pad0, pad1, pad2;
1450N/A } header;
1450N/A struct {
1450N/A unsigned char cmd_type, count, reglo, reghi;
1450N/A } packet0;
1450N/A struct {
1450N/A unsigned char cmd_type, count, adrlo, adrhi;
1450N/A } vpu;
1450N/A struct {
1450N/A unsigned char cmd_type, packet, pad0, pad1;
1450N/A } packet3;
1450N/A struct {
1450N/A unsigned char cmd_type, packet;
1450N/A unsigned short count; /* amount of packet2 to emit */
1450N/A } delay;
1450N/A struct {
1450N/A unsigned char cmd_type, buf_idx, pad0, pad1;
1450N/A } dma;
1450N/A struct {
1450N/A unsigned char cmd_type, flags, pad0, pad1;
1450N/A } wait;
1450N/A struct {
1450N/A unsigned char cmd_type, reg, n_bufs, flags;
1450N/A } scratch;
1450N/A} drm_r300_cmd_header_t;
1450N/A
1450N/A#define RADEON_FRONT 0x1
1450N/A#define RADEON_BACK 0x2
1450N/A#define RADEON_DEPTH 0x4
1450N/A#define RADEON_STENCIL 0x8
1450N/A#define RADEON_CLEAR_FASTZ 0x80000000
1450N/A#define RADEON_USE_HIERZ 0x40000000
1450N/A#define RADEON_USE_COMP_ZBUF 0x20000000
1450N/A
1450N/A/* Primitive types */
1450N/A#define RADEON_POINTS 0x1
1450N/A#define RADEON_LINES 0x2
1450N/A#define RADEON_LINE_STRIP 0x3
1450N/A#define RADEON_TRIANGLES 0x4
1450N/A#define RADEON_TRIANGLE_FAN 0x5
1450N/A#define RADEON_TRIANGLE_STRIP 0x6
1450N/A
1450N/A/* Vertex/indirect buffer size */
1450N/A#define RADEON_BUFFER_SIZE 65536
1450N/A
1450N/A/* Byte offsets for indirect buffer data */
1450N/A#define RADEON_INDEX_PRIM_OFFSET 20
1450N/A
1450N/A#define RADEON_SCRATCH_REG_OFFSET 32
1450N/A
1450N/A#define RADEON_NR_SAREA_CLIPRECTS 12
1450N/A
1450N/A/*
1450N/A * There are 2 heaps (local/GART). Each region within a heap is a
1450N/A * minimum of 64k, and there are at most 64 of them per heap.
1450N/A */
1450N/A#define RADEON_LOCAL_TEX_HEAP 0
1450N/A#define RADEON_GART_TEX_HEAP 1
1450N/A#define RADEON_NR_TEX_HEAPS 2
1450N/A#define RADEON_NR_TEX_REGIONS 64
1450N/A#define RADEON_LOG_TEX_GRANULARITY 16
1450N/A
1450N/A#define RADEON_MAX_TEXTURE_LEVELS 12
1450N/A#define RADEON_MAX_TEXTURE_UNITS 3
1450N/A
1450N/A#define RADEON_MAX_SURFACES 8
1450N/A
1450N/A/*
1450N/A * Blits have strict offset rules. All blit offset must be aligned on
1450N/A * a 1K-byte boundary.
1450N/A */
1450N/A#define RADEON_OFFSET_SHIFT 10
1450N/A#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
1450N/A#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
1450N/A
1450N/A#endif /* __RADEON_SAREA_DEFINES__ */
1450N/A
1450N/Atypedef struct {
1450N/A unsigned int red;
1450N/A unsigned int green;
1450N/A unsigned int blue;
1450N/A unsigned int alpha;
1450N/A} radeon_color_regs_t;
1450N/A
1450N/Atypedef struct {
1450N/A /* Context state */
1450N/A unsigned int pp_misc; /* 0x1c14 */
1450N/A unsigned int pp_fog_color;
1450N/A unsigned int re_solid_color;
1450N/A unsigned int rb3d_blendcntl;
1450N/A unsigned int rb3d_depthoffset;
1450N/A unsigned int rb3d_depthpitch;
1450N/A unsigned int rb3d_zstencilcntl;
1450N/A
1450N/A unsigned int pp_cntl; /* 0x1c38 */
1450N/A unsigned int rb3d_cntl;
1450N/A unsigned int rb3d_coloroffset;
1450N/A unsigned int re_width_height;
1450N/A unsigned int rb3d_colorpitch;
1450N/A unsigned int se_cntl;
1450N/A
1450N/A /* Vertex format state */
1450N/A unsigned int se_coord_fmt; /* 0x1c50 */
1450N/A
1450N/A /* Line state */
1450N/A unsigned int re_line_pattern; /* 0x1cd0 */
1450N/A unsigned int re_line_state;
1450N/A
1450N/A unsigned int se_line_width; /* 0x1db8 */
1450N/A
1450N/A /* Bumpmap state */
1450N/A unsigned int pp_lum_matrix; /* 0x1d00 */
1450N/A
1450N/A unsigned int pp_rot_matrix_0; /* 0x1d58 */
1450N/A unsigned int pp_rot_matrix_1;
1450N/A
1450N/A /* Mask state */
1450N/A unsigned int rb3d_stencilrefmask; /* 0x1d7c */
1450N/A unsigned int rb3d_ropcntl;
1450N/A unsigned int rb3d_planemask;
1450N/A
1450N/A /* Viewport state */
1450N/A unsigned int se_vport_xscale; /* 0x1d98 */
1450N/A unsigned int se_vport_xoffset;
1450N/A unsigned int se_vport_yscale;
1450N/A unsigned int se_vport_yoffset;
1450N/A unsigned int se_vport_zscale;
1450N/A unsigned int se_vport_zoffset;
1450N/A
1450N/A /* Setup state */
1450N/A unsigned int se_cntl_status; /* 0x2140 */
1450N/A
1450N/A /* Misc state */
1450N/A unsigned int re_top_left; /* 0x26c0 */
1450N/A unsigned int re_misc;
1450N/A} drm_radeon_context_regs_t;
1450N/A
1450N/Atypedef struct {
1450N/A /* Zbias state */
1450N/A unsigned int se_zbias_factor; /* 0x1dac */
1450N/A unsigned int se_zbias_constant;
1450N/A} drm_radeon_context2_regs_t;
1450N/A
1450N/A/* Setup registers for each texture unit */
1450N/Atypedef struct {
1450N/A unsigned int pp_txfilter;
1450N/A unsigned int pp_txformat;
1450N/A unsigned int pp_txoffset;
1450N/A unsigned int pp_txcblend;
1450N/A unsigned int pp_txablend;
1450N/A unsigned int pp_tfactor;
1450N/A unsigned int pp_border_color;
1450N/A} drm_radeon_texture_regs_t;
1450N/A
1450N/Atypedef struct {
1450N/A unsigned int start;
1450N/A unsigned int finish;
1450N/A unsigned int prim:8;
1450N/A unsigned int stateidx:8;
1450N/A unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
1450N/A unsigned int vc_format; /* vertex format */
1450N/A} drm_radeon_prim_t;
1450N/A
1450N/Atypedef struct {
1450N/A drm_radeon_context_regs_t context;
1450N/A drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
1450N/A drm_radeon_context2_regs_t context2;
1450N/A unsigned int dirty;
1450N/A} drm_radeon_state_t;
1450N/A
1450N/Atypedef struct {
1450N/A /*
1450N/A * The channel for communication of state information to the
1450N/A * kernel on firing a vertex buffer with either of the
1450N/A * obsoleted vertex/index ioctls.
1450N/A */
1450N/A drm_radeon_context_regs_t context_state;
1450N/A drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
1450N/A unsigned int dirty;
1450N/A unsigned int vertsize;
1450N/A unsigned int vc_format;
1450N/A
1450N/A /* The current cliprects, or a subset thereof. */
1450N/A drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
1450N/A unsigned int nbox;
1450N/A
1450N/A /* Counters for client-side throttling of rendering clients. */
1450N/A unsigned int last_frame;
1450N/A unsigned int last_dispatch;
1450N/A unsigned int last_clear;
1450N/A
1450N/A drm_tex_region_t
1450N/A tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1];
1450N/A unsigned int tex_age[RADEON_NR_TEX_HEAPS];
1450N/A int ctx_owner;
1450N/A int pfState; /* number of 3d windows (0,1,2ormore) */
1450N/A int pfCurrentPage; /* which buffer is being displayed? */
1450N/A int crtc2_base; /* CRTC2 frame offset */
1450N/A int tiling_enabled; /* set by drm, read by 2d + 3d clients */
1450N/A} drm_radeon_sarea_t;
1450N/A
1450N/A/*
1450N/A * WARNING: If you change any of these defines, make sure to change the
1450N/A * defines in the Xserver file (xf86drmRadeon.h)
1450N/A *
1450N/A * KW: actually it's illegal to change any of this (backwards compatibility).
1450N/A */
1450N/A
1450N/A/*
1450N/A * Radeon specific ioctls
1450N/A * The device specific ioctl range is 0x40 to 0x79.
1450N/A */
1450N/A#define DRM_RADEON_CP_INIT 0x00
1450N/A#define DRM_RADEON_CP_START 0x01
1450N/A#define DRM_RADEON_CP_STOP 0x02
1450N/A#define DRM_RADEON_CP_RESET 0x03
1450N/A#define DRM_RADEON_CP_IDLE 0x04
1450N/A#define DRM_RADEON_RESET 0x05
1450N/A#define DRM_RADEON_FULLSCREEN 0x06
1450N/A#define DRM_RADEON_SWAP 0x07
1450N/A#define DRM_RADEON_CLEAR 0x08
1450N/A#define DRM_RADEON_VERTEX 0x09
1450N/A#define DRM_RADEON_INDICES 0x0A
1450N/A#define DRM_RADEON_NOT_USED
1450N/A#define DRM_RADEON_STIPPLE 0x0C
1450N/A#define DRM_RADEON_INDIRECT 0x0D
1450N/A#define DRM_RADEON_TEXTURE 0x0E
1450N/A#define DRM_RADEON_VERTEX2 0x0F
1450N/A#define DRM_RADEON_CMDBUF 0x10
1450N/A#define DRM_RADEON_GETPARAM 0x11
1450N/A#define DRM_RADEON_FLIP 0x12
1450N/A#define DRM_RADEON_ALLOC 0x13
1450N/A#define DRM_RADEON_FREE 0x14
1450N/A#define DRM_RADEON_INIT_HEAP 0x15
1450N/A#define DRM_RADEON_IRQ_EMIT 0x16
1450N/A#define DRM_RADEON_IRQ_WAIT 0x17
1450N/A#define DRM_RADEON_CP_RESUME 0x18
1450N/A#define DRM_RADEON_SETPARAM 0x19
1450N/A#define DRM_RADEON_SURF_ALLOC 0x1a
1450N/A#define DRM_RADEON_SURF_FREE 0x1b
1450N/A
1450N/A#define DRM_IOCTL_RADEON_CP_INIT \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
1450N/A#define DRM_IOCTL_RADEON_CP_START \
1450N/A DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START)
1450N/A#define DRM_IOCTL_RADEON_CP_STOP \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
1450N/A#define DRM_IOCTL_RADEON_CP_RESET \
1450N/A DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
1450N/A#define DRM_IOCTL_RADEON_CP_IDLE \
1450N/A DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
1450N/A#define DRM_IOCTL_RADEON_RESET \
1450N/A DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET)
1450N/A#define DRM_IOCTL_RADEON_FULLSCREEN \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, \
1450N/A drm_radeon_fullscreen_t)
1450N/A#define DRM_IOCTL_RADEON_SWAP \
1450N/A DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP)
1450N/A#define DRM_IOCTL_RADEON_CLEAR \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
1450N/A#define DRM_IOCTL_RADEON_VERTEX \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
1450N/A#define DRM_IOCTL_RADEON_INDICES \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
1450N/A#define DRM_IOCTL_RADEON_STIPPLE \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
1450N/A#define DRM_IOCTL_RADEON_INDIRECT \
1450N/A DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
1450N/A#define DRM_IOCTL_RADEON_TEXTURE \
1450N/A DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
1450N/A#define DRM_IOCTL_RADEON_VERTEX2 \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
1450N/A#define DRM_IOCTL_RADEON_CMDBUF \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
1450N/A#define DRM_IOCTL_RADEON_GETPARAM \
1450N/A DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
1450N/A#define DRM_IOCTL_RADEON_FLIP \
1450N/A DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP)
1450N/A#define DRM_IOCTL_RADEON_ALLOC \
1450N/A DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
1450N/A#define DRM_IOCTL_RADEON_FREE \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
1450N/A#define DRM_IOCTL_RADEON_INIT_HEAP \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, \
1450N/A drm_radeon_mem_init_heap_t)
1450N/A#define DRM_IOCTL_RADEON_IRQ_EMIT \
1450N/A DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
1450N/A#define DRM_IOCTL_RADEON_IRQ_WAIT \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
1450N/A#define DRM_IOCTL_RADEON_CP_RESUME \
1450N/A DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
1450N/A#define DRM_IOCTL_RADEON_SETPARAM \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
1450N/A#define DRM_IOCTL_RADEON_SURF_ALLOC \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, \
1450N/A drm_radeon_surface_alloc_t)
1450N/A#define DRM_IOCTL_RADEON_SURF_FREE \
1450N/A DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, \
1450N/A drm_radeon_surface_free_t)
1450N/A
1450N/Atypedef struct drm_radeon_init {
1450N/A enum {
1450N/A RADEON_INIT_CP = 0x01,
1450N/A RADEON_CLEANUP_CP = 0x02,
1450N/A RADEON_INIT_R200_CP = 0x03,
1450N/A RADEON_INIT_R300_CP = 0x04
1450N/A } func;
1450N/A unsigned long sarea_priv_offset;
1450N/A int is_pci; /* for overriding only */
1450N/A int cp_mode;
1450N/A int gart_size;
1450N/A int ring_size;
1450N/A int usec_timeout;
1450N/A
1450N/A unsigned int fb_bpp;
1450N/A unsigned int front_offset, front_pitch;
1450N/A unsigned int back_offset, back_pitch;
1450N/A unsigned int depth_bpp;
1450N/A unsigned int depth_offset, depth_pitch;
1450N/A
1450N/A unsigned long fb_offset DEPRECATED; /* deprecated */
1450N/A unsigned long mmio_offset DEPRECATED; /* deprecated */
1450N/A unsigned long ring_offset;
1450N/A unsigned long ring_rptr_offset;
1450N/A unsigned long buffers_offset;
1450N/A unsigned long gart_textures_offset;
1450N/A} drm_radeon_init_t;
1450N/A
1450N/Atypedef struct drm_radeon_cp_stop {
1450N/A int flush;
1450N/A int idle;
1450N/A} drm_radeon_cp_stop_t;
1450N/A
1450N/Atypedef struct drm_radeon_fullscreen {
1450N/A enum {
1450N/A RADEON_INIT_FULLSCREEN = 0x01,
1450N/A RADEON_CLEANUP_FULLSCREEN = 0x02
1450N/A } func;
1450N/A} drm_radeon_fullscreen_t;
1450N/A
1450N/A#define CLEAR_X1 0
1450N/A#define CLEAR_Y1 1
1450N/A#define CLEAR_X2 2
1450N/A#define CLEAR_Y2 3
1450N/A#define CLEAR_DEPTH 4
1450N/A
1450N/Atypedef union drm_radeon_clear_rect {
1450N/A float f[5];
1450N/A unsigned int ui[5];
1450N/A} drm_radeon_clear_rect_t;
1450N/A
1450N/Atypedef struct drm_radeon_clear {
1450N/A unsigned int flags;
1450N/A unsigned int clear_color;
1450N/A unsigned int clear_depth;
1450N/A unsigned int color_mask;
1450N/A unsigned int depth_mask; /* misnamed field: should be stencil */
1450N/A drm_radeon_clear_rect_t __user *depth_boxes;
1450N/A} drm_radeon_clear_t;
1450N/A
1450N/Atypedef struct drm_radeon_vertex {
1450N/A int prim;
1450N/A int idx; /* Index of vertex buffer */
1450N/A int count; /* Number of vertices in buffer */
1450N/A int discard; /* Client finished with buffer? */
1450N/A} drm_radeon_vertex_t;
1450N/A
1450N/Atypedef struct drm_radeon_indices {
1450N/A int prim;
1450N/A int idx;
1450N/A int start;
1450N/A int end;
1450N/A int discard; /* Client finished with buffer? */
1450N/A} drm_radeon_indices_t;
1450N/A
1450N/A/*
1450N/A * v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
1450N/A * - allows multiple primitives and state changes in a single ioctl
1450N/A * - supports driver change to emit native primitives
1450N/A */
1450N/Atypedef struct drm_radeon_vertex2 {
1450N/A int idx; /* Index of vertex buffer */
1450N/A int discard; /* Client finished with buffer? */
1450N/A int nr_states;
1450N/A drm_radeon_state_t __user *state;
1450N/A int nr_prims;
1450N/A drm_radeon_prim_t __user *prim;
1450N/A} drm_radeon_vertex2_t;
1450N/A
1450N/A/*
1450N/A * v1.3 - obsoletes drm_radeon_vertex2
1450N/A * - allows arbitarily large cliprect list
1450N/A * - allows updating of tcl packet, vector and scalar state
1450N/A * - allows memory-efficient description of state updates
1450N/A * - allows state to be emitted without a primitive
1450N/A * (for clears, ctx switches)
1450N/A * - allows more than one dma buffer to be referenced per ioctl
1450N/A * - supports tcl driver
1450N/A * - may be extended in future versions with new cmd types, packets
1450N/A */
1450N/Atypedef struct drm_radeon_cmd_buffer {
1450N/A int bufsz;
1450N/A char __user *buf;
1450N/A int nbox;
1450N/A drm_clip_rect_t __user *boxes;
1450N/A} drm_radeon_cmd_buffer_t;
1450N/A
1450N/Atypedef struct drm_radeon_tex_image {
1450N/A unsigned int x, y; /* Blit coordinates */
1450N/A unsigned int width, height;
1450N/A const void __user *data;
1450N/A} drm_radeon_tex_image_t;
1450N/A
1450N/Atypedef struct drm_radeon_texture {
1450N/A unsigned int offset;
1450N/A int pitch;
1450N/A int format;
1450N/A int width; /* Texture image coordinates */
1450N/A int height;
1450N/A drm_radeon_tex_image_t __user *image;
1450N/A} drm_radeon_texture_t;
1450N/A
1450N/Atypedef struct drm_radeon_stipple {
1450N/A unsigned int __user *mask;
1450N/A} drm_radeon_stipple_t;
1450N/A
1450N/Atypedef struct drm_radeon_indirect {
1450N/A int idx;
1450N/A int start;
1450N/A int end;
1450N/A int discard;
1450N/A} drm_radeon_indirect_t;
1450N/A
1450N/A/* enum for card type parameters */
1450N/A#define RADEON_CARD_PCI 0
1450N/A#define RADEON_CARD_AGP 1
1450N/A#define RADEON_CARD_PCIE 2
1450N/A
1450N/A/*
1450N/A * 1.3: An ioctl to get parameters that aren't available to the 3d
1450N/A * client any other way.
1450N/A */
1450N/A
1450N/A/* card offset of 1st GART buffer */
1450N/A#define RADEON_PARAM_GART_BUFFER_OFFSET 1
1450N/A
1450N/A#define RADEON_PARAM_LAST_FRAME 2
1450N/A#define RADEON_PARAM_LAST_DISPATCH 3
1450N/A#define RADEON_PARAM_LAST_CLEAR 4
1450N/A/* Added with DRM version 1.6. */
1450N/A#define RADEON_PARAM_IRQ_NR 5
1450N/A#define RADEON_PARAM_GART_BASE 6 /* offset of GART base */
1450N/A/* Added with DRM version 1.8. */
1450N/A#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
1450N/A#define RADEON_PARAM_STATUS_HANDLE 8
1450N/A#define RADEON_PARAM_SAREA_HANDLE 9
1450N/A#define RADEON_PARAM_GART_TEX_HANDLE 10
1450N/A#define RADEON_PARAM_SCRATCH_OFFSET 11
1450N/A#define RADEON_PARAM_CARD_TYPE 12
1450N/A#define RADEON_PARAM_VBLANK_CRTC 13
1450N/A#define RADEON_PARAM_FB_LOCATION 14
1450N/A
1450N/Atypedef struct drm_radeon_getparam {
1450N/A int param;
1450N/A void __user *value;
1450N/A} drm_radeon_getparam_t;
1450N/A
1450N/A/* 1.6: Set up a memory manager for regions of shared memory: */
1450N/A#define RADEON_MEM_REGION_GART 1
1450N/A#define RADEON_MEM_REGION_FB 2
1450N/A
1450N/Atypedef struct drm_radeon_mem_alloc {
1450N/A int region;
1450N/A int alignment;
1450N/A int size;
1450N/A int __user *region_offset; /* offset from start of fb or GART */
1450N/A} drm_radeon_mem_alloc_t;
1450N/A
1450N/Atypedef struct drm_radeon_mem_free {
1450N/A int region;
1450N/A int region_offset;
1450N/A} drm_radeon_mem_free_t;
1450N/A
1450N/Atypedef struct drm_radeon_mem_init_heap {
1450N/A int region;
1450N/A int size;
1450N/A int start;
1450N/A} drm_radeon_mem_init_heap_t;
1450N/A
1450N/A/* 1.6: Userspace can request & wait on irq's: */
1450N/Atypedef struct drm_radeon_irq_emit {
1450N/A int __user *irq_seq;
1450N/A} drm_radeon_irq_emit_t;
1450N/A
1450N/Atypedef struct drm_radeon_irq_wait {
1450N/A int irq_seq;
1450N/A} drm_radeon_irq_wait_t;
1450N/A
1450N/A/*
1450N/A * 1.10: Clients tell the DRM where they think the framebuffer is located in
1450N/A * the card's address space, via a new generic ioctl to set parameters
1450N/A */
1450N/A
1450N/Atypedef struct drm_radeon_setparam {
1450N/A unsigned int param;
1450N/A int64_t value;
1450N/A} drm_radeon_setparam_t;
1450N/A
1450N/A/* determined framebuffer location */
1450N/A#define RADEON_SETPARAM_FB_LOCATION 1
1450N/A
1450N/A/* enable/disable color tiling */
1450N/A#define RADEON_SETPARAM_SWITCH_TILING 2
1450N/A
1450N/A/* PCI Gart Location */
1450N/A#define RADEON_SETPARAM_PCIGART_LOCATION 3
1450N/A
1450N/A/* Use new memory map */
1450N/A#define RADEON_SETPARAM_NEW_MEMMAP 4
1450N/A
1450N/A/* PCI GART Table Size */
1450N/A#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5
1450N/A
1450N/A/* VBLANK CRTC */
1450N/A#define RADEON_SETPARAM_VBLANK_CRTC 6
1450N/A
1450N/A
1450N/A/* 1.14: Clients can allocate/free a surface */
1450N/Atypedef struct drm_radeon_surface_alloc {
1450N/A unsigned int address;
1450N/A unsigned int size;
1450N/A unsigned int flags;
1450N/A} drm_radeon_surface_alloc_t;
1450N/A
1450N/Atypedef struct drm_radeon_surface_free {
1450N/A unsigned int address;
1450N/A} drm_radeon_surface_free_t;
1450N/A
1450N/A#define DRM_RADEON_VBLANK_CRTC1 1
1450N/A#define DRM_RADEON_VBLANK_CRTC2 2
1450N/A
1450N/A#endif /* __RADEON_DRM_H__ */