1450N/A/*
1450N/A * Copyright (c) 2008, 2011, Oracle and/or its affiliates. All rights reserved.
1450N/A */
1450N/A
1450N/A#ifndef _EFB_REG_H
1450N/A#define _EFB_REG_H
1450N/A
1450N/A#define RADEON_GMC_DST_8BPP (2 << 8)
1450N/A
1450N/A#define GMC_SRC_MONO 0x00000000
1450N/A#define GMC_SRC_MONO_LBKGD 0x00001000
1450N/A#define GMC_SRC_DSTCOLOR 0x00003000
1450N/A#define GMC_WRITE_MASK_LEAVE 0x00000000
1450N/A
1450N/A#define DST_X_LEFT_TO_RIGHT 0x00000001
1450N/A#define DST_Y_TOP_TO_BOTTOM 0x00000002
1450N/A#define DST_Y_BOTTOM_TO_TOP 0x00000000
1450N/A#define DST_X_RIGHT_TO_LEFT 0x00000000
1450N/A
1450N/A
1450N/A/* CRTC_PITCH */
1450N/A#define CRTC_PITCH__CRTC_PITCH_MASK 0x000007ff
1450N/A#define CRTC_PITCH__CRTC_PITCH_RIGHT_MASK 0x07ff0000
1450N/A
1450N/A/* CRTC_H_TOTAL_DISP */
1450N/A#define CRTC_H_TOTAL_DISP__CRTC_H_TOTAL_MASK 0x000003ffL
1450N/A#define CRTC_H_TOTAL_DISP__CRTC_H_DISP_MASK 0x01ff0000L
1450N/A
1450N/A/* CRTC_V_TOTAL_DISP */
1450N/A#define CRTC_V_TOTAL_DISP__CRTC_V_TOTAL_MASK 0x00000fffL
1450N/A#define CRTC_V_TOTAL_DISP__CRTC_V_DISP_MASK 0x0fff0000L
1450N/A
1450N/A/* CRTC_H_TOTAL_DISP */
1450N/A#define CRTC_H_TOTAL_DISP__CRTC_H_TOTAL__SHIFT 0x00000000
1450N/A#define CRTC_H_TOTAL_DISP__CRTC_H_DISP__SHIFT 0x00000010
1450N/A
1450N/A/* CRTC_V_TOTAL_DISP */
1450N/A#define CRTC_V_TOTAL_DISP__CRTC_V_TOTAL__SHIFT 0x00000000
1450N/A#define CRTC_V_TOTAL_DISP__CRTC_V_DISP__SHIFT 0x00000010
1450N/A
1450N/A
1450N/A/* DEFAULT_PITCH_OFFSET */
1450N/A#define DEFAULT_PITCH_OFFSET__DEFAULT_OFFSET__SHIFT 0x00000000
1450N/A#define DEFAULT_PITCH_OFFSET__DEFAULT_PITCH__SHIFT 0x00000016
1450N/A#define DEFAULT_PITCH_OFFSET__DEFAULT_TILE__SHIFT 0x0000001e
1450N/A
1450N/A/* CRTC_GEN_CNTL */
1450N/A#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
1450N/A#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
1450N/A#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
1450N/A#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
1450N/A#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
1450N/A#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
1450N/A#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
1450N/A#define CRTC_GEN_CNTL__CRTC_MODE9_COLOR_ORDER_MASK 0x00001000L
1450N/A#define CRTC_GEN_CNTL__CRTC_MODE9_COLOR_ORDER 0x00001000L
1450N/A#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
1450N/A#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
1450N/A#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
1450N/A#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
1450N/A#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
1450N/A#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
1450N/A#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
1450N/A#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
1450N/A#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
1450N/A#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
1450N/A#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
1450N/A#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
1450N/A
1450N/A#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN__SHIFT 0x00000000
1450N/A#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN__SHIFT 0x00000001
1450N/A#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN__SHIFT 0x00000004
1450N/A#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH__SHIFT 0x00000008
1450N/A#define CRTC_GEN_CNTL__CRTC_MODE9_COLOR_ORDER__SHIFT 0x0000000c
1450N/A#define CRTC_GEN_CNTL__CRTC_ICON_EN__SHIFT 0x0000000f
1450N/A#define CRTC_GEN_CNTL__CRTC_CUR_EN__SHIFT 0x00000010
1450N/A#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE__SHIFT 0x00000011
1450N/A#define CRTC_GEN_CNTL__CRTC_CUR_MODE__SHIFT 0x00000014
1450N/A#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN__SHIFT 0x00000018
1450N/A#define CRTC_GEN_CNTL__CRTC_EN__SHIFT 0x00000019
1450N/A#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B__SHIFT 0x0000001a
1450N/A
1450N/A/* PALETTE_INDEX */
1450N/A#define PALETTE_INDEX__PALETTE_W_INDEX_MASK 0x000000ffL
1450N/A#define PALETTE_INDEX__PALETTE_R_INDEX_MASK 0x00ff0000L
1450N/A
1450N/A/* PALETTE_DATA */
1450N/A#define PALETTE_DATA__PALETTE_DATA_B_MASK 0x000000ffL
1450N/A#define PALETTE_DATA__PALETTE_DATA_G_MASK 0x0000ff00L
1450N/A#define PALETTE_DATA__PALETTE_DATA_R_MASK 0x00ff0000L
1450N/A
1450N/A/* PALETTE_30_DATA */
1450N/A#define PALETTE_30_DATA__PALETTE_DATA_B_MASK 0x000003ffL
1450N/A#define PALETTE_30_DATA__PALETTE_DATA_G_MASK 0x000ffc00L
1450N/A#define PALETTE_30_DATA__PALETTE_DATA_R_MASK 0x3ff00000L
1450N/A
1450N/A/* PALETTE_INDEX */
1450N/A#define PALETTE_INDEX__PALETTE_W_INDEX__SHIFT 0x00000000
1450N/A#define PALETTE_INDEX__PALETTE_R_INDEX__SHIFT 0x00000010
1450N/A
1450N/A/* PALETTE_DATA */
1450N/A#define PALETTE_DATA__PALETTE_DATA_B__SHIFT 0x00000000
1450N/A#define PALETTE_DATA__PALETTE_DATA_G__SHIFT 0x00000008
1450N/A#define PALETTE_DATA__PALETTE_DATA_R__SHIFT 0x00000010
1450N/A
1450N/A/* PALETTE_30_DATA */
1450N/A#define PALETTE_30_DATA__PALETTE_DATA_B__SHIFT 0x00000000
1450N/A#define PALETTE_30_DATA__PALETTE_DATA_G__SHIFT 0x0000000a
1450N/A#define PALETTE_30_DATA__PALETTE_DATA_R__SHIFT 0x00000014
1450N/A
1450N/A/* DP_DATATYPE bit constants */
1450N/A#define DST_8BPP 0x00000002
1450N/A#define DST_15BPP 0x00000003
1450N/A#define DST_16BPP 0x00000004
1450N/A#define DST_24BPP 0x00000005
1450N/A#define DST_32BPP 0x00000006
1450N/A#define DST_8BPP_RGB332 0x00000007
1450N/A#define DST_8BPP_Y8 0x00000008
1450N/A#define DST_8BPP_RGB8 0x00000009
1450N/A#define DST_16BPP_VYUY422 0x0000000b
1450N/A#define DST_16BPP_YVYU422 0x0000000c
1450N/A#define DST_32BPP_AYUV444 0x0000000e
1450N/A#define DST_16BPP_ARGB4444 0x0000000f
1450N/A#define BRUSH_8x8MONO 0x00000000
1450N/A#define BRUSH_8x8MONO_LBKGD 0x00000100
1450N/A#define GMC_DST_8BPP 0x00000200
1450N/A#define GMC_DST_15BPP 0x00000300
1450N/A#define GMC_DST_16BPP 0x00000400
1450N/A#define GMC_DST_32BPP 0x00000600
1450N/A
1450N/A#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
1450N/A#define GMC_SRC_DSTCOLOR 0x00003000
1450N/A#define ROP3_P 0x00f00000
1450N/A#define GMC_DP_SRC_RECT 0x02000000
1450N/A#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
1450N/A#define GMC_WRITE_MASK_SET 0x40000000
1450N/A
1450N/A/* Registers from BIF block */
1450N/A
1450N/A#define CRTC_GEN_CNTL 0x050
1450N/A#define CRTC_EXT_CNTL 0x054
1450N/A#define CRTC2_GEN_CNTL 0x3F8
1450N/A
1450N/A/* Registers from DISPLAY block */
1450N/A
1450N/A#define GPIO_DDC1 0x60
1450N/A#define GPIO_DDC2 0x64
1450N/A#define GPIO_DDC3 0x68
1450N/A#define PALETTE_INDEX 0xB0
1450N/A#define PALETTE_DATA 0xB4
1450N/A#define PALETTE_30_DATA 0xB8
1450N/A#define DAC_CNTL2 0x7C
1450N/A
1450N/A#define CRTC_H_TOTAL_DISP 0x200
1450N/A#define CRTC_H_SYNC_STRT_WID 0x204
1450N/A#define CRTC_V_TOTAL_DISP 0x208
1450N/A#define CRTC_V_SYNC_STRT_WID 0x20C
1450N/A#define CRTC_VLINE_CRNT_VLINE 0x210
1450N/A#define CRTC_CRNT_FRAME 0x214
1450N/A#define CRTC_GUI_TRIG_VLINE 0x218
1450N/A#define CRTC_DEBUG 0x21C
1450N/A#define CRTC_OFFSET_RIGHT 0x220
1450N/A#define CRTC_OFFSET 0x224
1450N/A#define CRTC_OFFSET_CNTL 0x228
1450N/A#define CRTC_PITCH 0x22C
1450N/A#define DISPLAY_BASE_ADDR 0x23C
1450N/A
1450N/A#define CRTC2_H_TOTAL_DISP 0x300
1450N/A#define CRTC2_H_SYNC_STRT_WID 0x304
1450N/A#define CRTC2_V_TOTAL_DISP 0x308
1450N/A#define CRTC2_V_SYNC_STRT_WID 0x30C
1450N/A#define CRTC2_VLINE_CRNT_VLINE 0x310
1450N/A#define CRTC2_CRNT_FRAME 0x314
1450N/A#define CRTC2_GUI_TRIG_VLINE 0x318
1450N/A#define CRTC2_DEBUG 0x31C
1450N/A#define CRTC2_OFFSET_RIGHT 0x320
1450N/A#define CRTC2_OFFSET 0x324
1450N/A#define CRTC2_OFFSET_CNTL 0x328
1450N/A#define CRTC2_PITCH 0x32C
1450N/A
1450N/A
1450N/A
1450N/A/* Registers from E2 block */
1450N/A
1450N/A#define DST_OFFSET 0x1404
1450N/A#define DST_PITCH 0x1408
1450N/A#define DST_TILE 0x1700
1450N/A#define DST_PITCH_OFFSET 0x142C
1450N/A#define DST_X 0x141C
1450N/A#define DST_Y 0x1420
1450N/A#define DST_X_Y 0x1594
1450N/A#define DST_Y_X 0x1438
1450N/A#define DST_WIDTH 0x140C
1450N/A#define DST_HEIGHT 0x1410
1450N/A#define DST_WIDTH_HEIGHT 0x1598
1450N/A#define DST_HEIGHT_WIDTH 0x143C
1450N/A#define DST_HEIGHT_WIDTH_8 0x158C
1450N/A#define DST_HEIGHT_Y 0x15A0
1450N/A#define DST_WIDTH_X 0x1588
1450N/A#define DST_WIDTH_X_INCY 0x159C
1450N/A#define DST_LINE_START 0x1600
1450N/A#define DST_LINE_END 0x1604
1450N/A#define DST_LINE_PATCOUNT 0x1608
1450N/A#define DP_DST_ENDIAN 0x15D0
1450N/A#define DEFAULT_PITCH_OFFSET 0x16E0
1450N/A#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
1450N/A#define SRC_OFFSET 0x15AC
1450N/A#define SRC_PITCH 0x15B0
1450N/A#define SRC_TILE 0x1704
1450N/A#define SRC_PITCH_OFFSET 0x1428
1450N/A#define SRC_X 0x1414
1450N/A#define SRC_Y 0x1418
1450N/A#define SRC_X_Y 0x1590
1450N/A#define SRC_Y_X 0x1434
1450N/A#define SRC_CLUT_ADDRESS 0x1780
1450N/A#define SRC_CLUT_DATA 0x1784
1450N/A#define SRC_CLUT_DATA_RD 0x1788
1450N/A#define DP_CNTL 0x16C0
1450N/A#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
1450N/A#define DP_DATATYPE 0x16C4
1450N/A#define DP_MIX 0x16C8
1450N/A#define DP_WRITE_MSK 0x16CC
1450N/A#define DP_XOP 0x17F8
1450N/A#define CLR_CMP_CLR_SRC 0x15C4
1450N/A#define CLR_CMP_CLR_DST 0x15C8
1450N/A#define CLR_CMP_CNTL 0x15C0
1450N/A#define CLR_CMP_MSK 0x15CC
1450N/A#define DSTCACHE_MODE 0x1710
1450N/A#define DSTCACHE_CTLSTAT 0x1714
1450N/A
1450N/A/* DAC_CNTL2 */
1450N/A#define DAC_CNTL2__PALETTE_ACCESS_CNTL_MASK 0x00000020L
1450N/A#define DAC_CNTL2__PALETTE_ACCESS_CNTL 0x00000020L
1450N/A
1450N/A
1450N/A/* Registers from RBBM block */
1450N/A
1450N/A#define RBBM_GUICNTL 0x172C
1450N/A#define RBBM_STATUS 0xE40
1450N/A#define RBBM_CNTL 0xEC
1450N/A#define RBBM_SOFT_RESET 0xF0
1450N/A
1450N/A/* RBBM_SOFT_RESET */
1450N/A
1450N/A#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
1450N/A#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L
1450N/A#define RBBM_SOFT_RESET__SOFT_RESET_E2_MASK 0x00000020L
1450N/A#define RBBM_SOFT_RESET__SOFT_RESET_E2 0x00000020L
1450N/A
1450N/A/* RBBM_STATUS */
1450N/A#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000007fL
1450N/A
1450N/A#define GUI_ACTIVE 0x80000000
1450N/A
1450N/A
1450N/A/* Registers from MC block */
1450N/A
1450N/A#define MC_FB_LOCATION 0x148
1450N/A
1450N/A/* Registers from HDP block */
1450N/A
1450N/A#define HOST_PATH_CNTL 0x130
1450N/A
1450N/A
1450N/A#define RB3D_CNTL 0x1C3C
1450N/A
1450N/A
1450N/A/* defines for Coherent Console stuff for S11 and above */
1450N/A#define SRC_DSTCOLOR 0x00030000
1450N/A#define DP_SRC_RECT 0x00000200
1450N/A#define ROP3_SRCCOPY 0x00cc0000
1450N/A#define BRUSH_SOLIDCOLOR 0x00000d00
1450N/A
1450N/A#define DDC_DATA_OUTPUT 0x00000001
1450N/A#define DDC_CLK_OUTPUT 0x00000002
1450N/A#define DDC_DATA_INPUT 0x00000100
1450N/A#define DDC_CLK_INPUT 0x00000200
1450N/A#define DDC_DATA_OUT_EN 0x00010000
1450N/A#define DDC_CLK_OUT_EN 0x00020000
1450N/A
1450N/A#define DDC_DATA_INPUT_SHIFT 0x00000008
1450N/A#define DDC_CLK_INPUT_SHIFT 0x00000009
1450N/A
1450N/A
1450N/A#endif /* _EFB_REG_H */