/*
* Copyright (c) 2008, 2011, Oracle and/or its affiliates. All rights reserved.
*/
#ifndef _EFB_REG_H
#define _EFB_REG_H
#define RADEON_GMC_DST_8BPP (2 << 8)
#define GMC_SRC_MONO 0x00000000
#define GMC_SRC_MONO_LBKGD 0x00001000
#define GMC_SRC_DSTCOLOR 0x00003000
#define GMC_WRITE_MASK_LEAVE 0x00000000
#define DST_X_LEFT_TO_RIGHT 0x00000001
#define DST_Y_TOP_TO_BOTTOM 0x00000002
#define DST_Y_BOTTOM_TO_TOP 0x00000000
#define DST_X_RIGHT_TO_LEFT 0x00000000
/* CRTC_PITCH */
#define CRTC_PITCH__CRTC_PITCH_MASK 0x000007ff
#define CRTC_PITCH__CRTC_PITCH_RIGHT_MASK 0x07ff0000
/* CRTC_H_TOTAL_DISP */
#define CRTC_H_TOTAL_DISP__CRTC_H_TOTAL_MASK 0x000003ffL
#define CRTC_H_TOTAL_DISP__CRTC_H_DISP_MASK 0x01ff0000L
/* CRTC_V_TOTAL_DISP */
#define CRTC_V_TOTAL_DISP__CRTC_V_TOTAL_MASK 0x00000fffL
#define CRTC_V_TOTAL_DISP__CRTC_V_DISP_MASK 0x0fff0000L
/* CRTC_H_TOTAL_DISP */
#define CRTC_H_TOTAL_DISP__CRTC_H_TOTAL__SHIFT 0x00000000
#define CRTC_H_TOTAL_DISP__CRTC_H_DISP__SHIFT 0x00000010
/* CRTC_V_TOTAL_DISP */
#define CRTC_V_TOTAL_DISP__CRTC_V_TOTAL__SHIFT 0x00000000
#define CRTC_V_TOTAL_DISP__CRTC_V_DISP__SHIFT 0x00000010
/* DEFAULT_PITCH_OFFSET */
#define DEFAULT_PITCH_OFFSET__DEFAULT_OFFSET__SHIFT 0x00000000
#define DEFAULT_PITCH_OFFSET__DEFAULT_PITCH__SHIFT 0x00000016
#define DEFAULT_PITCH_OFFSET__DEFAULT_TILE__SHIFT 0x0000001e
/* CRTC_GEN_CNTL */
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
#define CRTC_GEN_CNTL__CRTC_MODE9_COLOR_ORDER_MASK 0x00001000L
#define CRTC_GEN_CNTL__CRTC_MODE9_COLOR_ORDER 0x00001000L
#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN__SHIFT 0x00000000
#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN__SHIFT 0x00000001
#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN__SHIFT 0x00000004
#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH__SHIFT 0x00000008
#define CRTC_GEN_CNTL__CRTC_MODE9_COLOR_ORDER__SHIFT 0x0000000c
#define CRTC_GEN_CNTL__CRTC_ICON_EN__SHIFT 0x0000000f
#define CRTC_GEN_CNTL__CRTC_CUR_EN__SHIFT 0x00000010
#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE__SHIFT 0x00000011
#define CRTC_GEN_CNTL__CRTC_CUR_MODE__SHIFT 0x00000014
#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN__SHIFT 0x00000018
#define CRTC_GEN_CNTL__CRTC_EN__SHIFT 0x00000019
#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B__SHIFT 0x0000001a
/* PALETTE_INDEX */
#define PALETTE_INDEX__PALETTE_W_INDEX_MASK 0x000000ffL
#define PALETTE_INDEX__PALETTE_R_INDEX_MASK 0x00ff0000L
/* PALETTE_DATA */
#define PALETTE_DATA__PALETTE_DATA_B_MASK 0x000000ffL
#define PALETTE_DATA__PALETTE_DATA_G_MASK 0x0000ff00L
#define PALETTE_DATA__PALETTE_DATA_R_MASK 0x00ff0000L
/* PALETTE_30_DATA */
#define PALETTE_30_DATA__PALETTE_DATA_B_MASK 0x000003ffL
#define PALETTE_30_DATA__PALETTE_DATA_G_MASK 0x000ffc00L
#define PALETTE_30_DATA__PALETTE_DATA_R_MASK 0x3ff00000L
/* PALETTE_INDEX */
#define PALETTE_INDEX__PALETTE_W_INDEX__SHIFT 0x00000000
#define PALETTE_INDEX__PALETTE_R_INDEX__SHIFT 0x00000010
/* PALETTE_DATA */
#define PALETTE_DATA__PALETTE_DATA_B__SHIFT 0x00000000
#define PALETTE_DATA__PALETTE_DATA_G__SHIFT 0x00000008
#define PALETTE_DATA__PALETTE_DATA_R__SHIFT 0x00000010
/* PALETTE_30_DATA */
#define PALETTE_30_DATA__PALETTE_DATA_B__SHIFT 0x00000000
#define PALETTE_30_DATA__PALETTE_DATA_G__SHIFT 0x0000000a
#define PALETTE_30_DATA__PALETTE_DATA_R__SHIFT 0x00000014
/* DP_DATATYPE bit constants */
#define DST_8BPP 0x00000002
#define DST_15BPP 0x00000003
#define DST_16BPP 0x00000004
#define DST_24BPP 0x00000005
#define DST_32BPP 0x00000006
#define DST_8BPP_RGB332 0x00000007
#define DST_8BPP_Y8 0x00000008
#define DST_8BPP_RGB8 0x00000009
#define DST_16BPP_VYUY422 0x0000000b
#define DST_16BPP_YVYU422 0x0000000c
#define DST_32BPP_AYUV444 0x0000000e
#define DST_16BPP_ARGB4444 0x0000000f
#define BRUSH_8x8MONO 0x00000000
#define BRUSH_8x8MONO_LBKGD 0x00000100
#define GMC_DST_8BPP 0x00000200
#define GMC_DST_15BPP 0x00000300
#define GMC_DST_16BPP 0x00000400
#define GMC_DST_32BPP 0x00000600
#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
#define GMC_SRC_DSTCOLOR 0x00003000
#define ROP3_P 0x00f00000
#define GMC_DP_SRC_RECT 0x02000000
#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
#define GMC_WRITE_MASK_SET 0x40000000
/* Registers from BIF block */
#define CRTC_GEN_CNTL 0x050
#define CRTC_EXT_CNTL 0x054
#define CRTC2_GEN_CNTL 0x3F8
/* Registers from DISPLAY block */
#define GPIO_DDC1 0x60
#define GPIO_DDC2 0x64
#define GPIO_DDC3 0x68
#define PALETTE_INDEX 0xB0
#define PALETTE_DATA 0xB4
#define PALETTE_30_DATA 0xB8
#define DAC_CNTL2 0x7C
#define CRTC_H_TOTAL_DISP 0x200
#define CRTC_H_SYNC_STRT_WID 0x204
#define CRTC_V_TOTAL_DISP 0x208
#define CRTC_V_SYNC_STRT_WID 0x20C
#define CRTC_VLINE_CRNT_VLINE 0x210
#define CRTC_CRNT_FRAME 0x214
#define CRTC_GUI_TRIG_VLINE 0x218
#define CRTC_DEBUG 0x21C
#define CRTC_OFFSET_RIGHT 0x220
#define CRTC_OFFSET 0x224
#define CRTC_OFFSET_CNTL 0x228
#define CRTC_PITCH 0x22C
#define DISPLAY_BASE_ADDR 0x23C
#define CRTC2_H_TOTAL_DISP 0x300
#define CRTC2_H_SYNC_STRT_WID 0x304
#define CRTC2_V_TOTAL_DISP 0x308
#define CRTC2_V_SYNC_STRT_WID 0x30C
#define CRTC2_VLINE_CRNT_VLINE 0x310
#define CRTC2_CRNT_FRAME 0x314
#define CRTC2_GUI_TRIG_VLINE 0x318
#define CRTC2_DEBUG 0x31C
#define CRTC2_OFFSET_RIGHT 0x320
#define CRTC2_OFFSET 0x324
#define CRTC2_OFFSET_CNTL 0x328
#define CRTC2_PITCH 0x32C
/* Registers from E2 block */
#define DST_OFFSET 0x1404
#define DST_PITCH 0x1408
#define DST_TILE 0x1700
#define DST_PITCH_OFFSET 0x142C
#define DST_X 0x141C
#define DST_Y 0x1420
#define DST_X_Y 0x1594
#define DST_Y_X 0x1438
#define DST_WIDTH 0x140C
#define DST_HEIGHT 0x1410
#define DST_WIDTH_HEIGHT 0x1598
#define DST_HEIGHT_WIDTH 0x143C
#define DST_HEIGHT_WIDTH_8 0x158C
#define DST_HEIGHT_Y 0x15A0
#define DST_WIDTH_X 0x1588
#define DST_WIDTH_X_INCY 0x159C
#define DST_LINE_START 0x1600
#define DST_LINE_END 0x1604
#define DST_LINE_PATCOUNT 0x1608
#define DP_DST_ENDIAN 0x15D0
#define DEFAULT_PITCH_OFFSET 0x16E0
#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
#define SRC_OFFSET 0x15AC
#define SRC_PITCH 0x15B0
#define SRC_TILE 0x1704
#define SRC_PITCH_OFFSET 0x1428
#define SRC_X 0x1414
#define SRC_Y 0x1418
#define SRC_X_Y 0x1590
#define SRC_Y_X 0x1434
#define SRC_CLUT_ADDRESS 0x1780
#define SRC_CLUT_DATA 0x1784
#define SRC_CLUT_DATA_RD 0x1788
#define DP_CNTL 0x16C0
#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
#define DP_DATATYPE 0x16C4
#define DP_MIX 0x16C8
#define DP_WRITE_MSK 0x16CC
#define DP_XOP 0x17F8
#define CLR_CMP_CLR_SRC 0x15C4
#define CLR_CMP_CLR_DST 0x15C8
#define CLR_CMP_CNTL 0x15C0
#define CLR_CMP_MSK 0x15CC
#define DSTCACHE_MODE 0x1710
#define DSTCACHE_CTLSTAT 0x1714
/* DAC_CNTL2 */
#define DAC_CNTL2__PALETTE_ACCESS_CNTL_MASK 0x00000020L
#define DAC_CNTL2__PALETTE_ACCESS_CNTL 0x00000020L
/* Registers from RBBM block */
#define RBBM_GUICNTL 0x172C
#define RBBM_STATUS 0xE40
#define RBBM_CNTL 0xEC
#define RBBM_SOFT_RESET 0xF0
/* RBBM_SOFT_RESET */
#define RBBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
#define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001L
#define RBBM_SOFT_RESET__SOFT_RESET_E2_MASK 0x00000020L
#define RBBM_SOFT_RESET__SOFT_RESET_E2 0x00000020L
/* RBBM_STATUS */
#define RBBM_STATUS__CMDFIFO_AVAIL_MASK 0x0000007fL
#define GUI_ACTIVE 0x80000000
/* Registers from MC block */
#define MC_FB_LOCATION 0x148
/* Registers from HDP block */
#define HOST_PATH_CNTL 0x130
#define RB3D_CNTL 0x1C3C
/* defines for Coherent Console stuff for S11 and above */
#define SRC_DSTCOLOR 0x00030000
#define DP_SRC_RECT 0x00000200
#define ROP3_SRCCOPY 0x00cc0000
#define BRUSH_SOLIDCOLOR 0x00000d00
#define DDC_DATA_OUTPUT 0x00000001
#define DDC_CLK_OUTPUT 0x00000002
#define DDC_DATA_INPUT 0x00000100
#define DDC_CLK_INPUT 0x00000200
#define DDC_DATA_OUT_EN 0x00010000
#define DDC_CLK_OUT_EN 0x00020000
#define DDC_DATA_INPUT_SHIFT 0x00000008
#define DDC_CLK_INPUT_SHIFT 0x00000009
#endif /* _EFB_REG_H */