/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright 2007 Jason King. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* The sparc disassembler is mostly straightforward, each instruction is
* represented by an inst_t structure. The inst_t definitions are organized
* into tables. The tables are correspond to the opcode maps documented in the
* various sparc architecture manuals. Each table defines the bit range of the
* instruction whose value act as an index into the array of instructions. A
* table can also refer to another table if needed. Each table also contains
* a function pointer of type format_fcn that knows how to output the
* instructions in the table, as well as handle any synthetic instructions
*
* Unfortunately, the changes from sparcv8 -> sparcv9 not only include new
* instructions, they sometimes renamed or just reused the same instruction to
* do different operations (i.e. the sparcv8 coprocessor instructions). To
* accommodate this, each table can define an overlay table. The overlay table
* is a list of (table index, architecture, new instruction definition) values.
*
*
* Traversal starts with the first table,
* get index value from the instruction
* if an relevant overlay entry exists for this index,
* grab the overlay definition
* else
* grab the definition from the array (corresponding to the index value)
*
* If the entry is an instruction,
* call print function of instruction.
* If the entry is a pointer to another table
* traverse the table
* If not valid,
* return an error
*
*
* To keep dis happy, for sparc, instead of actually returning an error, if
* the instruction cannot be disassembled, we instead merely place the value
* of the instruction into the output buffer.
*
* Adding new instructions:
*
* With the above information, it hopefully makes it clear how to add support
* for decoding new instructions. Presumably, with new instructions will come
* a new dissassembly mode (I.e. DIS_SPARC_V8, DIS_SPARC_V9, etc.).
*
* If the dissassembled format does not correspond to one of the existing
* formats, a new formatter will have to be written. The 'flags' value of
* inst_t is intended to instruct the corresponding formatter about how to
* output the instruction.
*
* If the corresponding entry in the correct table is currently unoccupied,
* simply replace the INVALID entry with the correct definition. The INST and
* TABLE macros are suggested to be used for this. If there is already an
* instruction defined, then the entry must be placed in an overlay table. If
* no overlay table exists for the instruction table, one will need to be
* created.
*/
#include <libdisasm.h>
#include <stdlib.h>
#include <stdio.h>
#include <sys/byteorder.h>
#include <string.h>
#include "libdisasm_impl.h"
#include "dis_sparc.h"
uint32_t);
#if !defined(DIS_STANDALONE)
#endif /* DIS_STANDALONE */
{
#if !defined(DIS_STANDALONE)
#endif
(void) dis_seterrno(E_DIS_INVALFLAG);
return (NULL);
}
(void) dis_seterrno(E_DIS_NOMEM);
return (NULL);
}
#if !defined(DIS_STANDALONE)
return (dhp);
(void) dis_seterrno(E_DIS_NOMEM);
return (NULL);
}
if (end != 0)
*end++ = '\0';
}
#endif /* DIS_STANDALONE */
return (dhp);
}
void
{
}
void
{
}
void
{
}
void
{
}
/* ARGSUSED */
int
{
return (4);
}
/*
* The dis_i386.c comment for this says it returns the previous instruction,
* however, I'm fairly sure it's actually returning the _address_ of the
* nth previous instruction.
*/
/* ARGSUSED */
{
if (n <= 0)
return (pc);
if (pc < n)
return (pc);
return (pc - n*4);
}
int
{
sizeof (instr))
return (-1);
buf[0] = '\0';
/* this allows sparc code to be tested on x86 */
#if !defined(DIS_STANDALONE)
#endif /* DIS_STANDALONE */
/* CONSTCOND */
while (1) {
goto error;
continue;
}
break;
}
return (0);
instr);
return (0);
}
static uint32_t
{
int i;
mask |= (1UL << i);
return (val);
}
static const inst_t *
{
int i;
return (ip);
continue;
continue;
break;
}
return (ip);
}
#if !defined(DIS_STANDALONE)
static void
{
}
#endif /* DIS_STANDALONE */