2N/A/*
2N/A * GRUB -- GRand Unified Bootloader
2N/A * Copyright (C) 2000,2001,2002,2003,2004,2005,2007,2008,2009,2010 Free Software Foundation, Inc.
2N/A *
2N/A * GRUB is free software: you can redistribute it and/or modify
2N/A * it under the terms of the GNU General Public License as published by
2N/A * the Free Software Foundation, either version 3 of the License, or
2N/A * (at your option) any later version.
2N/A *
2N/A * GRUB is distributed in the hope that it will be useful,
2N/A * but WITHOUT ANY WARRANTY; without even the implied warranty of
2N/A * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2N/A * GNU General Public License for more details.
2N/A *
2N/A * You should have received a copy of the GNU General Public License
2N/A * along with GRUB. If not, see <http://www.gnu.org/licenses/>.
2N/A */
2N/A
2N/A#include <grub/mips/loongson/serial.h>
2N/A#include <grub/mips/loongson/pci.h>
2N/A#include <grub/mips/loongson.h>
2N/A#include <grub/pci.h>
2N/A#include <grub/machine/serial.h>
2N/A#include <grub/machine/kernel.h>
2N/A#include <grub/ns8250.h>
2N/A#include <grub/cs5536.h>
2N/A#include <grub/smbus.h>
2N/A
2N/A#ifdef FULOONG2F
2N/A#define GRUB_MACHINE_SERIAL_PORT GRUB_MACHINE_SERIAL_PORT2
2N/A#define GRUB_MACHINE_SERIAL_DIVISOR_115200 GRUB_MACHINE_SERIAL_PORT2_DIVISOR_115200
2N/A#else
2N/A#define GRUB_MACHINE_SERIAL_PORT GRUB_MACHINE_SERIAL_PORT0
2N/A#define GRUB_MACHINE_SERIAL_DIVISOR_115200 GRUB_MACHINE_SERIAL_PORT0_DIVISOR_115200
2N/A#endif
2N/A
2N/A .set noreorder
2N/A .set noat
2N/A .set nomacro
2N/A .set mips3
2N/A
2N/A .global start,_start,__start
2N/Astart:
2N/A_start:
2N/A__start:
2N/A /* Put serial init as soon as possible. But on Fuloong2f serial is past
2N/A Geode, so on Fuloong2f we need Geode first.
2N/A */
2N/A#ifndef FULOONG2F
2N/A bal serial_hw_init
2N/A nop
2N/A#endif
2N/A
2N/A /* Find CS5536 controller. */
2N/A /* $t4 chooses device in priority encoding. */
2N/A /* Resulting value is kept in GRUB_MACHINE_PCI_CONF_CTRL_REG.
2N/A This way we don't need to sacrifice a register for it. */
2N/Aretry_cs5536:
2N/A /* We have only one bus (0). Function is 0. */
2N/A lui $t0, %hi(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR)
2N/A lui $t1, %hi(GRUB_MACHINE_PCI_CONFSPACE)
2N/A lui $t3, %hi(GRUB_CS5536_PCIID)
2N/A addiu $t3, $t3, %lo(GRUB_CS5536_PCIID)
2N/A ori $t4, $zero, 1
2N/A1:
2N/A andi $t4, $t4, ((1 << GRUB_PCI_NUM_DEVICES) - 1)
2N/A /* In case of failure try again. CS5536 may be slow to come up. */
2N/A beql $t4, $zero, retry_cs5536
2N/A nop
2N/A sw $t4, %lo(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR) ($t0)
2N/A lw $t2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_PCI_REG_PCI_ID) ($t1)
2N/A bnel $t2, $t3, 1b
2N/A sll $t4, $t4, 1
2N/A
2N/A#ifndef FULOONG2F
2N/A bal message
2N/A addiu $a0, $a0, %lo(cs5536_found)
2N/A bal printhex
2N/A move $a0, $t4
2N/A#endif
2N/A
2N/A lui $t0, %hi(GRUB_MACHINE_PCI_CONFSPACE)
2N/A li $t1, GRUB_CS5536_MSR_MAILBOX_CONFIG_ENABLED
2N/A sw $t1, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_CONFIG) ($t0)
2N/A
2N/A /* Set GPIO LBAR. */
2N/A lui $a0, %hi(GRUB_CS5536_MSR_GPIO_BAR)
2N/A addiu $a0, $a0, %lo(GRUB_CS5536_MSR_GPIO_BAR)
2N/A ori $a1, $zero, GRUB_CS5536_LBAR_GPIO
2N/A /* Set mask to 0xf and enabled bit to 1. */
2N/A bal wrmsr
2N/A ori $a2, $zero, ((GRUB_CS5536_LBAR_MASK_MASK \
2N/A | GRUB_CS5536_LBAR_ENABLE) >> 32)
2N/A
2N/A bal gpio_init
2N/A nop
2N/A
2N/A#ifdef FULOONG2F
2N/A bal serial_hw_init
2N/A nop
2N/A#endif
2N/A
2N/A /* Initialise SMBus controller. */
2N/A /* Set SMBUS LBAR. */
2N/A lui $a0, %hi(GRUB_CS5536_MSR_SMB_BAR)
2N/A addiu $a0, $a0, %lo(GRUB_CS5536_MSR_SMB_BAR)
2N/A ori $a1, $zero, GRUB_CS5536_LBAR_SMBUS
2N/A /* Set mask to 0xf and enabled bit to 1. */
2N/A bal wrmsr
2N/A ori $a2, $zero, ((GRUB_CS5536_LBAR_MASK_MASK \
2N/A | GRUB_CS5536_LBAR_ENABLE) >> 32)
2N/A
2N/A lui $a0, %hi(smbus_enabled)
2N/A bal message
2N/A addiu $a0, $a0, %lo(smbus_enabled)
2N/A
2N/A lui $t0, %hi(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS)
2N/A
2N/A /* Disable SMB. */
2N/A sb $zero, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL2) ($t0)
2N/A
2N/A /* Disable interrupts. */
2N/A sb $zero, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1) ($t0)
2N/A
2N/A /* Set as master. */
2N/A sb $zero, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_ADDR) ($t0)
2N/A
2N/A /* Launch SMBus controller at slowest speed possible. */
2N/A ori $t1, $zero, 0xff
2N/A sb $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL3) ($t0)
2N/A sb $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL2) ($t0)
2N/A
2N/A /* Yeeloong and Fuloong2f have only one memory slot. */
2N/A /* Output first byte on serial for debugging. */
2N/A ori $a1, $zero, GRUB_SMB_RAM_START_ADDR
2N/A bal read_spd
2N/A move $a0, $zero
2N/A bal printhex
2N/A move $a0, $v0
2N/A
2N/A bal read_spd
2N/A ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_TYPE_ADDR
2N/A ori $t0, $zero, GRUB_SMBUS_SPD_MEMORY_TYPE_DDR2
2N/A lui $a0, %hi(unimplemented_memory_type)
2N/A bne $t0, $v0, fatal
2N/A addiu $a0, $a0, %lo(unimplemented_memory_type)
2N/A
2N/A /* And here is our goal: DDR2 controller initialisation. */
2N/A lui $t0, %hi(GRUB_CPU_LOONGSON_CORECFG)
2N/A ld $t1, %lo(GRUB_CPU_LOONGSON_CORECFG) ($t0)
2N/A /* Use addiu for sign-extension. */
2N/A addiu $t2, $zero, ~(GRUB_CPU_LOONGSON_CORECFG_DISABLE_DDR2_SPACE|GRUB_CPU_LOONGSON_CORECFG_BUFFER_CPU)
2N/A and $t1, $t1, $t2
2N/A sd $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
2N/A
2N/A b continue
2N/A
2N/A . = start + GRUB_CPU_LOONGSON_FLASH_TLB_REFILL - GRUB_CPU_LOONGSON_FLASH_START
2N/Atlb_refill:
2N/A mfc0 $s1, GRUB_CPU_LOONGSON_COP0_EPC
2N/A mfc0 $s2, GRUB_CPU_LOONGSON_COP0_BADVADDR
2N/A move $s3, $ra
2N/A lui $a0, %hi(epc)
2N/A bal message
2N/A addiu $a0, $a0, %lo(epc)
2N/A
2N/A bal printhex
2N/A move $a0, $s1
2N/A
2N/A lui $a0, %hi(badvaddr)
2N/A bal message
2N/A addiu $a0, $a0, %lo(badvaddr)
2N/A
2N/A bal printhex
2N/A move $a0, $s2
2N/A
2N/A lui $a0, %hi(return_msg)
2N/A bal message
2N/A addiu $a0, $a0, %lo(return_msg)
2N/A
2N/A bal printhex
2N/A move $a0, $s3
2N/A
2N/A lui $a0, %hi(newline)
2N/A bal message
2N/A addiu $a0, $a0, %lo(newline)
2N/A
2N/A lui $a0, %hi(unhandled_tlb_refill)
2N/A b fatal
2N/A addiu $a0, $a0, %lo(unhandled_tlb_refill)
2N/A
2N/A . = start + GRUB_CPU_LOONGSON_FLASH_CACHE_ERROR - GRUB_CPU_LOONGSON_FLASH_START
2N/Acache_error:
2N/A lui $a0, %hi(unhandled_cache_error)
2N/A b fatal
2N/A addiu $a0, $a0, %lo(unhandled_cache_error)
2N/A
2N/A . = start + GRUB_CPU_LOONGSON_FLASH_OTHER_EXCEPTION - GRUB_CPU_LOONGSON_FLASH_START
2N/Aother_exception:
2N/A mfc0 $s0, GRUB_CPU_LOONGSON_COP0_CAUSE
2N/A mfc0 $s1, GRUB_CPU_LOONGSON_COP0_EPC
2N/A mfc0 $s2, GRUB_CPU_LOONGSON_COP0_BADVADDR
2N/A lui $a0, %hi(cause)
2N/A bal message
2N/A addiu $a0, $a0, %lo(cause)
2N/A
2N/A bal printhex
2N/A move $a0, $s0
2N/A
2N/A lui $a0, %hi(epc)
2N/A bal message
2N/A addiu $a0, $a0, %lo(epc)
2N/A
2N/A bal printhex
2N/A move $a0, $s1
2N/A
2N/A lui $a0, %hi(badvaddr)
2N/A bal message
2N/A addiu $a0, $a0, %lo(badvaddr)
2N/A
2N/A bal printhex
2N/A move $a0, $s2
2N/A
2N/A lui $a0, %hi(newline)
2N/A bal message
2N/A addiu $a0, $a0, %lo(newline)
2N/A
2N/A lui $a0, %hi(unhandled_exception)
2N/A b fatal
2N/A addiu $a0, $a0, %lo(unhandled_exception)
2N/A
2N/Agpio_init:
2N/A lui $t0, %hi(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO)
2N/A addiu $t0, $t0, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_GPIO)
2N/A lui $t1, %hi (gpio_dump)
2N/A addiu $t1, $t1, %lo (gpio_dump)
2N/A
2N/A1:
2N/A lw $t2, 0($t1)
2N/A sw $t2, 0($t0)
2N/A addiu $t0, $t0, 4
2N/A addiu $t1, $t1, 4
2N/A lui $t2, %hi (gpio_dump_end)
2N/A addiu $t2, $t2, %lo (gpio_dump_end)
2N/A bne $t1, $t2, 1b
2N/A nop
2N/A jr $ra
2N/A nop
2N/A
2N/A /* Same as similarly named C function but in asm since
2N/A we need it early. */
2N/A /* In: none. Out: none. Clobbered: $t0, $t1, $t2, $a0, $a1, $a2. */
2N/Aserial_hw_init:
2N/A move $t2, $ra
2N/A#ifdef FULOONG2F
2N/A lui $a0, %hi(GRUB_CS5536_MSR_DIVIL_LEG_IO)
2N/A addiu $a0, $a0, %lo(GRUB_CS5536_MSR_DIVIL_LEG_IO)
2N/A lui $a1, %hi (GRUB_CS5536_MSR_DIVIL_LEG_IO_UART2_COM3 \
2N/A | GRUB_CS5536_MSR_DIVIL_LEG_IO_F_REMAP \
2N/A | GRUB_CS5536_MSR_DIVIL_LEG_IO_MODE_X86 \
2N/A | GRUB_CS5536_MSR_DIVIL_LEG_IO_UART1_COM1)
2N/A ori $a1, $a1, (GRUB_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE0 \
2N/A | GRUB_CS5536_MSR_DIVIL_LEG_IO_RTC_ENABLE1)
2N/A bal wrmsr
2N/A move $a2, $zero
2N/A
2N/A lui $a0, %hi(GRUB_CS5536_MSR_DIVIL_UART1_CONF)
2N/A addiu $a0, $a0, %lo(GRUB_CS5536_MSR_DIVIL_UART1_CONF)
2N/A li $a1, 2
2N/A bal wrmsr
2N/A move $a2, $zero
2N/A
2N/A lui $a0, %hi(GRUB_CS5536_MSR_DIVIL_UART2_CONF)
2N/A addiu $a0, $a0, %lo(GRUB_CS5536_MSR_DIVIL_UART2_CONF)
2N/A li $a1, 2
2N/A bal wrmsr
2N/A move $a2, $zero
2N/A#endif
2N/A
2N/A lui $t0, %hi (GRUB_MACHINE_SERIAL_PORT)
2N/A
2N/A /* Turn off the interrupt. */
2N/A sb $zero, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_IER)($t0)
2N/A
2N/A /* Set DLAB. */
2N/A ori $t1, $zero, UART_DLAB
2N/A sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LCR)($t0)
2N/A
2N/A /* Set the baud rate 115200. */
2N/A ori $t1, $zero, GRUB_MACHINE_SERIAL_DIVISOR_115200
2N/A sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_DLL)($t0)
2N/A sb $zero, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_DLH)($t0)
2N/A
2N/A /* Set the line status. */
2N/A ori $t1, $zero, (UART_NO_PARITY | UART_8BITS_WORD | UART_1_STOP_BIT)
2N/A sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LCR)($t0)
2N/A
2N/A /* Enable the FIFO. */
2N/A ori $t1, $zero, UART_ENABLE_FIFO_TRIGGER1
2N/A sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_FCR)($t0)
2N/A
2N/A /* Turn on DTR and RTS. */
2N/A ori $t1, $zero, UART_ENABLE_DTRRTS
2N/A sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_MCR)($t0)
2N/A
2N/A /* Let message return to original caller. */
2N/A lui $a0, %hi(notification_string)
2N/A addiu $a0, $a0, %lo(notification_string)
2N/A move $ra, $t2
2N/A
2N/A /* Print message on serial console. */
2N/A /* In: $a0 = asciiz message. Out: none. Clobbered: $t0, $t1, $a0. */
2N/Amessage:
2N/A lui $t0, %hi (GRUB_MACHINE_SERIAL_PORT)
2N/A1:
2N/A lb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LSR)($t0)
2N/A andi $t1, $t1, UART_EMPTY_TRANSMITTER
2N/A beq $t1, $zero, 1b
2N/A nop
2N/A lb $t1, 0($a0)
2N/A sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_TX)($t0)
2N/A bne $t1, $zero, 1b
2N/A addiu $a0, $a0, 1
2N/A jr $ra
2N/A nop
2N/A
2N/A /* Print 32-bit hexadecimal on serial.
2N/A In: $a0. Out: None. Clobbered: $a0, $t0, $t1, $t2
2N/A */
2N/Aprinthex:
2N/A lui $t0, %hi (GRUB_MACHINE_SERIAL_PORT)
2N/A ori $t2, $zero, 8
2N/A1:
2N/A lb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LSR)($t0)
2N/A andi $t1, $t1, UART_EMPTY_TRANSMITTER
2N/A beq $t1, $zero, 1b
2N/A nop
2N/A srl $t1, $a0, 28
2N/A addiu $t1, $t1, -10
2N/A blt $t1, $zero, 2f
2N/A sll $a0, $a0, 4
2N/A addiu $t1, $t1, 'A'-10-'0'
2N/A2: addiu $t1, $t1, '0'+10
2N/A sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_TX)($t0)
2N/A addiu $t2, $t2, -1
2N/A bne $t2, $zero, 1b
2N/A nop
2N/A jr $ra
2N/A nop
2N/A
2N/Afatal:
2N/A bal message
2N/A nop
2N/Aself:
2N/A b self
2N/A nop
2N/A
2N/A /* Write CS5536 MSR.
2N/A In: $a0 address, $a1 lower word, $a2 upper word.
2N/A Out: None
2N/A Clobbered: $t0
2N/A */
2N/Awrmsr:
2N/A lui $t0, %hi(GRUB_MACHINE_PCI_CONFSPACE)
2N/A sw $a0, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_ADDR) ($t0)
2N/A sw $a1, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_DATA0) ($t0)
2N/A jr $ra
2N/A sw $a2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_CS5536_MSR_MAILBOX_DATA1) ($t0)
2N/A
2N/A /* Wait for SMBus data or empty transmitter. */
2N/A /* In: $a0 = exception handler. Out: none. Clobbered: $t0, $t1 */
2N/Asmbus_wait:
2N/A1:
2N/A lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_STATUS + GRUB_MACHINE_PCI_IO_BASE)
2N/A lb $t0, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_STATUS + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A andi $t1, $t0, GRUB_CS5536_SMB_REG_STATUS_SDAST
2N/A bne $t1, $zero, return
2N/A nop
2N/A andi $t1, $t0, (GRUB_CS5536_SMB_REG_STATUS_BER | GRUB_CS5536_SMB_REG_STATUS_NACK)
2N/A beq $t1, $zero, 1b
2N/A nop
2N/A jr $a0
2N/A nop
2N/Areturn:
2N/A jr $ra
2N/A nop
2N/A
2N/A /* Read SPD byte. In: $a0 byte, $a1 device. Out: $v0 read byte (0x100 on failure).
2N/A Clobbered: $t0, $t1, $t2, $t3, $a0. */
2N/Aread_spd:
2N/A move $t2, $a0
2N/A move $t3, $ra
2N/A lui $a0, %hi(read_spd_fail)
2N/A addiu $a0, $a0, %hi(read_spd_fail)
2N/A
2N/A /* Send START. */
2N/A lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
2N/A lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_START
2N/A bal smbus_wait
2N/A sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A
2N/A /* Send device address. */
2N/A lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
2N/A sll $t1, $a1, 1
2N/A bal smbus_wait
2N/A sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A
2N/A /* Send ACK. */
2N/A lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
2N/A lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_ACK
2N/A sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A
2N/A /* Send byte address. */
2N/A lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
2N/A bal smbus_wait
2N/A sb $t2, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A
2N/A /* Send START. */
2N/A lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
2N/A lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_START
2N/A bal smbus_wait
2N/A sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A
2N/A /* Send device address. */
2N/A lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
2N/A sll $t1, $a1, 1
2N/A ori $t1, $t1, 1
2N/A bal smbus_wait
2N/A sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A
2N/A /* Send STOP. */
2N/A lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
2N/A lb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A ori $t1, $t1, GRUB_CS5536_SMB_REG_CTRL1_STOP
2N/A bal smbus_wait
2N/A sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A
2N/A lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
2N/A lb $v0, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
2N/A jr $t3
2N/A andi $v0, $v0, 0xff
2N/Aread_spd_fail:
2N/A jr $t3
2N/A ori $v0, $v0, 0x100
2N/A
2N/Anotification_string: .asciz "GRUB "
2N/Acs5536_found: .asciz "CS5536 at "
2N/Asm_failed: .asciz "SM transaction failed.\n\r"
2N/Aunhandled_tlb_refill: .asciz "Unhandled TLB refill.\n\r"
2N/Aunhandled_cache_error: .asciz "Unhandled cache error.\n\r"
2N/Aunhandled_exception: .asciz "Unhandled exception.\n\r"
2N/Asmbus_enabled: .asciz "SMBus controller enabled.\n\r"
2N/Aunimplemented_memory_type: .asciz "non-DDR2 memory isn't supported.\n\r"
2N/Ano_cas_latency: .asciz "Couldn't determine CAS latency.\n\r"
2N/Acause: .asciz "Cause: "
2N/Aepc: .asciz "\n\rEPC: "
2N/Abadvaddr: .asciz "\n\rBadVaddr: "
2N/Anewline: .asciz "\n\r"
2N/Areturn_msg: .asciz "\n\rReturn address: "
2N/Acaches_enabled: .asciz "Caches enabled\n\r"
2N/A
2N/A .p2align 3
2N/A
2N/Aregdump:
2N/A .quad 0x0100010000000101 /* 0 */
2N/A .quad 0x0100010100000000 /* 2 */
2N/A .quad 0x0101000001000000 /* 3 */
2N/A .quad 0x0100020200010101 /* 4 */
2N/A .quad 0x0a04030603050203 /* 6 */
2N/A .quad 0x0f0e040000010a0b /* 7 */
2N/A#ifdef FULOONG2F
2N/A .quad 0x0000000100000001 /* 8 */
2N/A#else
2N/A .quad 0x0000010200000102 /* 8 */
2N/A#endif
2N/A .quad 0x0000060c00000000 /* 9 */
2N/A .quad 0x2323233f3f1f0200 /* a */
2N/A .quad 0x5f7f232323232323 /* b */
2N/A .quad 0x002a3c0615000000 /* c */
2N/A .quad 0x002a002a002a002a /* d */
2N/A .quad 0x002a002a002a002a /* e */
2N/A#ifdef FULOONG2F
2N/A .quad 0x00b40020005b0004 /* f */
2N/A#else
2N/A .quad 0x00b40020006d0004 /* f */
2N/A#endif
2N/A .quad 0x070007ff00000087 /* 10 */
2N/A .quad 0x000000000016101f /* 11 */
2N/A .quad 0x001c000000000000 /* 12 */
2N/A .quad 0x28e1000200c8006b /* 13 */
2N/A .quad 0x0000204200c8002f /* 14 */
2N/A .quad 0x0000000000030d40 /* 15 */
2N/A .quad 0 /* 16 */
2N/A .quad 0 /* 17 */
2N/A .quad 0 /* 18 */
2N/A .quad 0 /* 19 */
2N/A .quad 0 /* 1a */
2N/A .quad 0 /* 1b */
2N/A .quad 0 /* 1c */
2N/A
2N/A/* Dump of GPIO connections. FIXME: Remove useless and macroify. */
2N/Agpio_dump:
2N/A#ifdef FULOONG2F
2N/A .long 0xffff0000, 0x2eefd110, 0xffff0000, 0xffff0000
2N/A .long 0x2eefd110, 0xffff0000, 0x1000efff, 0xefff1000
2N/A .long 0x3df3c20c, 0xffff0000, 0xffff0000, 0xffff0000
2N/A .long 0x7df3820c, 0x3df3c20c, 0xffff0000, 0x00000000
2N/A .long 0xffff0000, 0xffff0000, 0x3de3c21c, 0x3d83c27c
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0xffff0000, 0xffff0000, 0xffff0000, 0xffff0000
2N/A .long 0xffff0000, 0xffff0000, 0x0000ffff, 0xffff0000
2N/A .long 0xefff1000, 0xffff0000, 0xffff0000, 0xffff0000
2N/A .long 0xefff1000, 0xefff1000, 0xffff0000, 0x00000000
2N/A .long 0xffff0000, 0xffff0000, 0xefff1000, 0xefff1000
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A#else
2N/A .long 0xffff0000, 0x2ffdd002, 0xffff0000, 0xffff0000
2N/A .long 0x2fffd000, 0xffff0000, 0x1000efff, 0xefff1000
2N/A .long 0x3ffbc004, 0xffff0000, 0xffff0000, 0xffff0000
2N/A .long 0x3ffbc004, 0x3ffbc004, 0xffff0000, 0x00000000
2N/A .long 0xffff0000, 0xffff0000, 0x3ffbc004, 0x3f9bc064
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0xffff0000, 0xffff0000, 0xffff0000, 0xffff0000
2N/A .long 0xffff0000, 0xffff0000, 0x0000ffff, 0xffff0000
2N/A .long 0xefff1000, 0xffff0000, 0xffff0000, 0xffff0000
2N/A .long 0xefff1000, 0xefff1000, 0xffff0000, 0x00000000
2N/A .long 0xffff0000, 0xffff0000, 0xefff1000, 0xffff0000
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0x00000000, 0x00000000, 0x00000000, 0x00000000
2N/A .long 0x00000000, 0x50000000, 0x00000000, 0x00000000
2N/A#endif
2N/Agpio_dump_end:
2N/A
2N/A .p2align
2N/A
2N/Awrite_dumpreg:
2N/A ld $t2, 0($t6)
2N/A sd $t2, 0($t4)
2N/A addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
2N/A jr $ra
2N/A addiu $t6, $t6, GRUB_CPU_LOONGSON_DDR2_REG_SIZE
2N/A
2N/Acontinue:
2N/A lui $t4, %hi(GRUB_CPU_LOONGSON_DDR2_BASE)
2N/A addiu $t4, $t4, %lo(GRUB_CPU_LOONGSON_DDR2_BASE)
2N/A lui $t6, %hi(regdump)
2N/A
2N/A /* 0 */
2N/A bal write_dumpreg
2N/A addiu $t6, $t6, %lo(regdump)
2N/A
2N/A /* 1 */
2N/A ori $a1, $a1, GRUB_SMB_RAM_START_ADDR
2N/A move $t8, $zero
2N/A lui $t5, 0x0001
2N/A bal read_spd
2N/A ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_BANKS_ADDR
2N/A ori $t7, $zero, 8
2N/A bne $v0, $t7, 1f
2N/A ori $t5, $t5, 0x0001
2N/A ori $t8, $t8, GRUB_CPU_LOONGSON_DDR2_REG1_HI_8BANKS
2N/A1:
2N/A dsll $t8, $t8, 32
2N/A or $t5, $t5, $t8
2N/A sd $t5, 0 ($t4)
2N/A addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
2N/A
2N/A /* 2 */
2N/A bal write_dumpreg
2N/A nop
2N/A
2N/A /* 3 */
2N/A bal write_dumpreg
2N/A nop
2N/A
2N/A /* 4 */
2N/A bal write_dumpreg
2N/A nop
2N/A
2N/A /* 5 */
2N/A /* FIXME: figure termination resistance. */
2N/A ori $t5, $zero, 0x2
2N/A bal read_spd
2N/A ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_ROWS_ADDR
2N/A /* $v0 = 15 - $v0. */
2N/A xori $v0, $v0, 0xf
2N/A andi $v0, $v0, 0x7
2N/A sll $v0, $v0, 8
2N/A or $t5, $t5, $v0
2N/A
2N/A /* Find the fastest supported CAS latency. */
2N/A bal read_spd
2N/A ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_ADDR
2N/A ori $t0, $zero, GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_MIN_VALUE
2N/A ori $t1, $zero, (1 << GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_MIN_VALUE)
2N/A2:
2N/A and $t2, $t1, $v0
2N/A bne $t2, $zero, 1f
2N/A ori $t3, $zero, 8
2N/A lui $a0, %hi(no_cas_latency)
2N/A beq $t0, $t3, fatal
2N/A addiu $a0, $a0, %lo(no_cas_latency)
2N/A addiu $t0, $t0, 1
2N/A b 2b
2N/A sll $t1, $t1, 1
2N/A1:
2N/A sll $t0, $t0, 16
2N/A or $t5, $t5, $t0
2N/A
2N/A bal read_spd
2N/A ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_COLUMNS_ADDR
2N/A /* $v0 = 15 - ($v0 + 1) = 14 - $v0. */
2N/A addiu $v0, $v0, 1
2N/A xori $v0, $v0, 0xf
2N/A andi $v0, $v0, 0x7
2N/A sll $v0, 24
2N/A or $t5, $t5, $v0
2N/A sd $t5, 0 ($t4)
2N/A
2N/A addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
2N/A
2N/A ori $t7, $zero, 0x16
2N/A
2N/A1:
2N/A ld $t2, 0($t6)
2N/A sd $t2, 0($t4)
2N/A addiu $t4, $t4, GRUB_CPU_LOONGSON_DDR2_REG_STEP
2N/A addiu $t7, $t7, -1
2N/A bne $t7, $zero, 1b
2N/A addiu $t6, $t6, GRUB_CPU_LOONGSON_DDR2_REG_SIZE
2N/A
2N/A lui $t4, %hi(GRUB_CPU_LOONGSON_DDR2_BASE)
2N/A ld $t5, (%lo(GRUB_CPU_LOONGSON_DDR2_BASE) + 0x30) ($t4)
2N/A ori $t0, $zero, 1
2N/A dsll $t0, $t0, 40
2N/A or $t5, $t5, $t0
2N/A sd $t5, (%lo(GRUB_CPU_LOONGSON_DDR2_BASE) + 0x30) ($t4)
2N/A
2N/A /* Desactivate DDR2 registers. */
2N/A lui $t0, %hi (GRUB_CPU_LOONGSON_CORECFG)
2N/A ld $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
2N/A ori $t1, $t1, GRUB_CPU_LOONGSON_CORECFG_DISABLE_DDR2_SPACE
2N/A sd $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
2N/A
2N/A /* Enable cache. */
2N/A mfc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
2N/A addiu $t1, $zero, ~GRUB_CPU_LOONGSON_CACHE_TYPE_MASK
2N/A and $t0, $t1, $t1
2N/A /* Set line size to 32 bytes and disabled cache. */
2N/A ori $t0, $t0, (GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_ILINESIZE \
2N/A | GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_DLINESIZE \
2N/A | GRUB_CPU_LOONGSON_CACHE_ACCELERATED)
2N/A mtc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
2N/A
2N/A /* Invalidate all I-cache entries. */
2N/A srl $t1, $t0, GRUB_CPU_LOONGSON_COP0_CACHE_ISIZE_SHIFT
2N/A andi $t1, $t1, GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_MASK
2N/A ori $t2, $zero, (1 << (GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_OFFSET \
2N/A - GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
2N/A - GRUB_CPU_LOONGSON_I_CACHE_LOG_WAYS))
2N/A sll $t1, $t2, $t1
2N/A lui $t2, 0x8000
2N/A
2N/A1:
2N/A cache GRUB_CPU_LOONGSON_COP0_I_INDEX_INVALIDATE, 0($t2)
2N/A addiu $t1, $t1, -1
2N/A bne $t1, $zero, 1b
2N/A addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_I_INDEX_BIT_OFFSET)
2N/A
2N/A /* Invalidate all D-cache entries. */
2N/A srl $t1, $t0, GRUB_CPU_LOONGSON_COP0_CACHE_DSIZE_SHIFT
2N/A andi $t1, $t1, GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_MASK
2N/A ori $t2, $zero, (1 << (GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_OFFSET \
2N/A - GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
2N/A - GRUB_CPU_LOONGSON_D_CACHE_LOG_WAYS))
2N/A sll $t1, $t2, $t1
2N/A lui $t2, 0x8000
2N/A mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGLO
2N/A mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGHI
2N/A1:
2N/A /* All four ways. */
2N/A cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 0($t2)
2N/A cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 1($t2)
2N/A cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 2($t2)
2N/A cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 3($t2)
2N/A addiu $t1, $t1, -1
2N/A bne $t1, $zero, 1b
2N/A addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_D_INDEX_BIT_OFFSET)
2N/A
2N/A /* Invalidate all S-cache entries. */
2N/A ori $t1, $zero, (1 << (GRUB_CPU_LOONGSON_SECONDARY_CACHE_LOG_SIZE \
2N/A - GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
2N/A - GRUB_CPU_LOONGSON_S_CACHE_LOG_WAYS))
2N/A lui $t2, 0x8000
2N/A mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGLO
2N/A mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGHI
2N/A1:
2N/A /* All four ways. */
2N/A cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 0($t2)
2N/A cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 1($t2)
2N/A cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 2($t2)
2N/A cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 3($t2)
2N/A addiu $t1, $t1, -1
2N/A bne $t1, $zero, 1b
2N/A addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_D_INDEX_BIT_OFFSET)
2N/A
2N/A /* Finally enable cache. */
2N/A mfc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
2N/A addiu $t1, $zero, ~GRUB_CPU_LOONGSON_CACHE_TYPE_MASK
2N/A and $t0, $t1, $t1
2N/A ori $t0, $t0, GRUB_CPU_LOONGSON_CACHE_CACHED
2N/A mtc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
2N/A
2N/A lui $a0, %hi(caches_enabled)
2N/A bal message
2N/A addiu $a0, $a0, %lo(caches_enabled)
2N/A
2N/A /* Set ROM delay cycles to 1. */
2N/A lui $t0, %hi(GRUB_CPU_LOONGSON_LIOCFG)
2N/A lw $t1, %lo(GRUB_CPU_LOONGSON_LIOCFG) ($t0)
2N/A addiu $t2, $zero, ~(GRUB_CPU_LOONGSON_ROM_DELAY_MASK \
2N/A << GRUB_CPU_LOONGSON_ROM_DELAY_OFFSET)
2N/A and $t1, $t1, $t2
2N/A ori $t1, $t1, (1 << GRUB_CPU_LOONGSON_ROM_DELAY_OFFSET)
2N/A sw $t1, %lo(GRUB_CPU_LOONGSON_LIOCFG) ($t0)
2N/A
2N/A addiu $a0, $zero, -1
2N/A addiu $a1, $zero, -1
2N/A
2N/A /* Take advantage of cache. */
2N/A lui $t0, %hi(cached_continue - 0x20000000)
2N/A addiu $t0, $t0, %lo(cached_continue - 0x20000000)
2N/A jr $t0
2N/A#ifdef FULOONG2F
2N/A addiu $a2, $zero, -(1 + GRUB_ARCH_MACHINE_FULOONG2F)
2N/A#else
2N/A addiu $a2, $zero, -(1 + GRUB_ARCH_MACHINE_YEELOONG)
2N/A#endif
2N/A
2N/Acached_continue: