/* -*- Mode:C; c-basic-offset:4; -*- */
/*
natsemi.c: An Etherboot driver for the NatSemi DP8381x series.
Copyright (C) 2001 Entity Cyber, Inc.
This development of this Etherboot driver was funded by
Sicom Systems: http://www.sicompos.com/
Author: Marty Connor (mdc@thinguin.org)
Adapted from a Linux driver which was written by Donald Becker
This software may be used and distributed according to the terms
of the GNU Public License (GPL), incorporated herein by reference.
Original Copyright Notice:
This software may be used and distributed according to the terms of
the GNU General Public License (GPL), incorporated herein by reference.
Drivers based on or derived from this code fall under the GPL and must
retain the authorship, copyright and license notice. This file is not
a complete program and may only be used when the entire operating
system is licensed under the GPL. License for under other terms may be
available. Contact the original author for details.
The original author may be reached as becker@scyld.com, or at
Scyld Computing Corporation
410 Severn Ave., Suite 210
Annapolis MD 21403
Support information and updates available at
References:
Datasheet is available from:
*/
/* Revision History */
/*
13 Dec 2003 timlegge 1.1 Enabled Multicast Support
29 May 2001 mdc 1.0
Initial Release. Tested with Netgear FA311 and FA312 boards
*/
/* Includes */
#include "etherboot.h"
#include "nic.h"
#include "pci.h"
/* defines */
/* Time in ticks before concluding the transmitter is hung. */
/* helpful macroes if on a big_endian machine for changing byte order.
not strictly needed on Intel */
enum pcistuff {
};
/* MMIO operations required */
/* Offsets to the device registers.
Unlike software-only systems, device drivers interact with complex hardware.
It's not useful to define symbolic names for every register bit in the
device.
*/
enum register_offsets {
/* These are from the spec, around page 78... on a separate table. */
};
/* Bit in ChipCmd. */
enum ChipCmdBits {
};
/* Bits in the RxMode register. */
enum rx_mode_bits {
};
typedef struct _BufferDesc {
} BufferDesc;
/* Bits in network_desc.status */
enum desc_status_bits {
};
/* Globals */
const char *nic_name;
static unsigned long ioaddr;
static unsigned int cur_rx;
static unsigned int advertising;
static unsigned int rx_config;
static unsigned int tx_config;
/* Note: transmit and receive buffers and descriptors must be
longword aligned
*/
/* Function Prototypes */
static void natsemi_transmit(struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p);
/*
* Function: natsemi_probe
*
* Description: Retrieves the MAC address of the card, and sets up some
* globals required by other routines, and initializes the NIC, making it
* ready to send and receive packets.
*
* Side effects:
* leaves the ioaddress of the natsemi chip in the variable ioaddr.
* leaves the natsemi initialized, and ready to recieve packets.
*
* Returns: struct nic *: pointer to NIC data structure
*/
static int
{
int i;
int prev_eedata;
return 0;
/* initialize some commonly used globals */
/* natsemi has a non-standard PM control register
* in PCI config space. Some boards apparently need
* to be brought to D0 in this manner.
*/
/* D0 state, disable PME assertion */
}
/* get MAC address */
for (i = 0; i < 3; i++) {
}
printf("\nnatsemi_probe: MAC addr %! at ioaddr %#hX\n",
/* Reset the chip to erase any previous misconfiguration. */
{
printf("%s: Transceiver default autoneg. %s "
"10%s %s duplex.\n",
}
printf("%s: Transceiver status %hX advertising %hX\n",
/* Disable PME:
* The PME bit is initialized from the EEPROM contents.
* PCI cards probably have PME disabled, but motherboard
* implementations may have PME set to enable WakeOnLan.
* With PME set the chip will scan incoming packets but
* nothing will be written to memory. */
/* initialize device */
return 1;
}
/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses.
*/
/* Delay between EEPROM clock transitions.
No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
a delay. */
enum EEPROM_Ctrl_Bits {
};
/* The EEPROM commands include the alway-set leading bit. */
enum EEPROM_Cmds {
};
{
int i;
int retval = 0;
/* Shift the read command bits out. */
for (i = 10; i >= 0; i--) {
}
for (i = 0; i < 16; i++) {
}
/* Terminate the EEPROM access. */
return retval;
}
/* MII transceiver control section.
The 83815 series has an internal transceiver, and we present the
management registers as if they were MII connected. */
{
else
return 0xffff;
}
/* Function: natsemi_init
*
* Description: resets the ethernet controller chip and configures
* registers and data structures required for sending and receiving packets.
*
* Arguments: struct nic *nic: NIC data structure
*
* returns: void.
*/
static void
{
/* Disable PME:
* The PME bit is initialized from the EEPROM contents.
* PCI cards probably have PME disabled, but motherboard
* implementations may have PME set to enable WakeOnLan.
* With PME set the chip will scan incoming packets but
* nothing will be written to memory. */
/* Initialize other registers. */
/* Configure the PCI bus bursts and FIFO thresholds. */
/* Configure for standard, in-spec Ethernet. */
tx_config = 0xD0801002;
rx_config = 0x10000020;
} else {
tx_config = 0x10801002;
rx_config = 0x0020;
}
}
/*
* Function: natsemi_reset
*
* Description: soft resets the controller chip
*
* Arguments: struct nic *nic: NIC data structure
*
* Returns: void.
*/
static void
{
/* On page 78 of the spec, they recommend some settings for "optimum
performance" to be done in sequence. These settings optimize some
of the 100Mbit autodetection circuitry. Also, we only want to do
this for rev C of the chip.
*/
}
/* Disable interrupts using the mask. */
}
/* Function: natsemi_init_rxfilter
*
* Description: sets receive filter address to our MAC address
*
* Arguments: struct nic *nic: NIC data structure
*
* returns: void.
*/
static void
{
int i;
for (i = 0; i < ETH_ALEN; i += 2) {
}
}
/*
* Function: natsemi_init_txd
*
* Description: initializes the Tx descriptor
*
* Arguments: struct nic *nic: NIC data structure
*
* returns: void.
*/
static void
{
/* load Transmit Descriptor Register */
if (natsemi_debug > 1)
printf("natsemi_init_txd: TX descriptor register loaded with: %X\n",
}
/* Function: natsemi_init_rxd
*
* Description: initializes the Rx descriptor ring
*
* Arguments: struct nic *nic: NIC data structure
*
* Returns: void.
*/
static void
{
int i;
cur_rx = 0;
/* init RX descriptor */
for (i = 0; i < NUM_RX_DESC; i++) {
if (natsemi_debug > 1)
printf("natsemi_init_rxd: rxd[%d]=%X link=%X cmdsts=%X bufptr=%X\n",
}
/* load Receive Descriptor Register */
if (natsemi_debug > 1)
printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n",
}
/* Function: natsemi_set_rx_mode
*
* Description:
* sets the receive mode to accept all broadcast packets and packets
* with our MAC address, and reject all multicast packets.
*
* Arguments: struct nic *nic: NIC data structure
*
* Returns: void.
*/
{
}
{
if (natsemi_debug)
printf("%s: Setting %s-duplex based on negotiated link"
" capability.\n", nic_name,
if (duplex) {
rx_config |= 0x10000000;
tx_config |= 0xC0000000;
} else {
rx_config &= ~0x10000000;
tx_config &= ~0xC0000000;
}
}
/* Function: natsemi_transmit
*
* Description: transmits a packet and waits for completion or timeout.
*
* Arguments: char d[6]: destination ethernet address.
* unsigned short t: ethernet protocol type.
* unsigned short s: size of the data-part of the packet.
* char *p: the data for the packet.
*
* Returns: void.
*/
static void
const char *d, /* Destination */
unsigned int t, /* Type */
unsigned int s, /* size */
const char *p) /* Packet */
{
/* Stop the transmitter */
/* load Transmit Descriptor Register */
if (natsemi_debug > 1)
printf("natsemi_transmit: TX descriptor register loaded with: %X\n",
s += ETH_HLEN;
s &= DSIZE;
if (natsemi_debug > 1)
printf("natsemi_transmit: sending %d bytes ethtype %hX\n", (int) s, t);
/* pad to minimum packet size */
while (s < ETH_ZLEN)
txb[s++] = '\0';
/* set the transmit buffer descriptor and enable Transmit State Machine */
/* restart the transmitter */
if (natsemi_debug > 1)
printf("natsemi_transmit: Queued Tx packet size %d.\n", (int) s);
/* wait */ ;
}
if (!(tx_status & 0x08000000)) {
}
}
/* Function: natsemi_poll
*
* Description: checks for a received packet and returns it if found.
*
* Arguments: struct nic *nic: NIC data structure
*
* Returns: 1 if packet was received.
* 0 if no packet was received.
*
* Side effects:
* Returns (copies) the packet to the array nic->packet.
* Returns the length of the packet in nic->packetlen.
*/
static int
{
int retstat = 0;
if (natsemi_debug > 2)
return retstat;
if ( ! retrieve ) return 1;
if (natsemi_debug > 1)
printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n",
/* corrupted packet received */
printf("natsemi_poll: Corrupted packet received, buffer status = %X\n",
retstat = 0;
} else {
/* give packet to higher level routine */
retstat = 1;
}
/* return the descriptor and buffer to receive ring */
if (++cur_rx == NUM_RX_DESC)
cur_rx = 0;
/* re-enable the potentially idle receive state machine */
return retstat;
}
/* Function: natsemi_disable
*
* Description: Turns off interrupts and stops Tx and Rx engines
*
* Arguments: struct nic *nic: NIC data structure
*
* Returns: void.
*/
static void
{
/* merge reset and disable */
/* Disable interrupts using the mask. */
/* Stop the chip's Tx and Rx processes. */
/* Restore PME enable bit */
}
/* Function: natsemi_irq
*
* Description: Enable, Disable, or Force interrupts
*
* Arguments: struct nic *nic: NIC data structure
* irq_action_t action: requested action to perform
*
* Returns: void.
*/
static void
{
switch ( action ) {
case DISABLE :
break;
case ENABLE :
break;
case FORCE :
break;
}
}
};
.type = NIC_DRIVER,
.name = "NATSEMI",
.probe = natsemi_probe,
.ids = natsemi_nics,
.class = 0,
};