/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/* e1000_hw.h
* Structures, enums, and macros for the MAC
*/
#ifndef _E1000_HW_H_
#define _E1000_HW_H_
/* Forward declarations of structures used by the shared code */
struct e1000_hw;
struct e1000_hw_stats;
/* Enumerated types specific to the e1000 hardware */
/* Media Access Controlers */
typedef enum {
e1000_undefined = 0,
typedef enum {
/* Media Types */
typedef enum {
typedef enum {
e1000_10_half = 0,
/* Flow Control Settings */
typedef enum {
e1000_fc_none = 0,
/* PCI bus types */
typedef enum {
/* PCI bus speeds */
typedef enum {
/* PCI bus widths */
typedef enum {
/* PHY status info structure and supporting enums */
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
typedef enum {
e1000_phy_m88 = 0,
typedef enum {
e1000_ms_hw_default = 0,
typedef enum {
typedef enum {
struct e1000_phy_info {
};
struct e1000_phy_stats {
};
struct e1000_eeprom_info {
};
/* Error Codes */
#define E1000_SUCCESS 0
/* PCI Device IDs */
/* MAC decode size is 128K - This is the size of BAR0 */
/* The sizes (in bytes) of a ethernet packet */
#define MAXIMUM_ETHERNET_PACKET_SIZE \
#define MINIMUM_ETHERNET_PACKET_SIZE \
/* 802.1q VLAN Packet Sizes */
/* Ethertype field values */
/* Packet Header defines */
/* This defines the bits that are set in the Interrupt Mask
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
* o RXSEQ = Receive Sequence Error
*/
#define POLL_IMS_ENABLE_MASK ( \
E1000_IMS_RXDMT0 | \
/* This defines the bits that are set in the Interrupt Mask
* o RXT0 = Receiver Timer Interrupt (ring 0)
* o TXDW = Transmit Descriptor Written Back
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
* o RXSEQ = Receive Sequence Error
* o LSC = Link Status Change
*/
#define IMS_ENABLE_MASK ( \
E1000_IMS_RXT0 | \
E1000_IMS_TXDW | \
E1000_IMS_RXDMT0 | \
E1000_IMS_RXSEQ | \
* Registers) holds the directed and multicast addresses that we monitor. We
* reserve one of these spots for our directed address, allowing us room for
* E1000_RAR_ENTRIES - 1 multicast addresses.
*/
/* Receive Descriptor */
struct e1000_rx_desc {
};
/* Receive Decriptor bit definitions */
/* mask to determine if packets should be dropped due to frame errors */
#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
E1000_RXD_ERR_CE | \
E1000_RXD_ERR_SE | \
/* Transmit Descriptor */
struct e1000_tx_desc {
union {
struct {
} flags;
} lower;
union {
struct {
} fields;
} upper;
};
/* Transmit Descriptor bit definitions */
/* Offload Context Descriptor */
struct e1000_context_desc {
union {
struct {
} ip_fields;
} lower_setup;
union {
struct {
} tcp_fields;
} upper_setup;
union {
struct {
} fields;
};
/* Offload data descriptor */
struct e1000_data_desc {
union {
struct {
} flags;
} lower;
union {
struct {
} fields;
} upper;
};
/* Filters */
/* Receive Address Register */
struct e1000_rar {
};
/* Number of entries in the Multicast Table Array (MTA). */
/* IPv4 Address Table Entry */
struct e1000_ipv4_at_entry {
};
/* Four wakeup IP addresses are supported */
/* IPv6 Address Table Entry */
struct e1000_ipv6_at_entry {
};
/* Flexible Filter Length Table Entry */
struct e1000_fflt_entry {
};
/* Flexible Filter Mask Table Entry */
struct e1000_ffmt_entry {
};
/* Flexible Filter Value Table Entry */
struct e1000_ffvt_entry {
};
/* Four Flexible Filters are supported */
/* Each Flexible Filter is at most 128 (0x80) bytes in length */
/* Register Set. (82543, 82544)
*
* Registers are defined to be 32 bits and should be accessed as 32 bit values.
* These registers are physically located on the NIC, but are mapped into the
* host memory address space.
*
* RW - register is both readable and writable
* RO - register is read only
* WO - register is write only
* A - register array
*/
/* Register Set (82542)
*
* Some of the 82542 registers are located at different offsets than they are
* in more current versions of the 8254x. Despite the difference in location,
* the registers function in the same manner.
*/
/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
};
/* Structure containing variables used by the shared code (e1000_hw.c) */
struct e1000_hw {
#if 0
#endif
#if 0
#endif
#if 0
#endif
#ifdef LINUX_DRIVER
#endif
#if 0
#endif
#if 0
#endif
#if 0
#endif
#if 0
#endif
#if 0
#endif
#if 0
#endif
#if 0
#endif
};
/* Register Bit Masks */
/* Device Control */
/* Device Status */
/* Constants used to intrepret the masked PCI-X bus speed. */
* (0-small, 1-large) */
#ifndef E1000_EEPROM_GRANT_ATTEMPTS
#endif
/* EEPROM Read */
/* SPI EEPROM Status Register */
/* Extended Device Control */
/* MDI Control */
/* LED Control */
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
/* Receive Address */
/* Interrupt Cause Read */
/* Interrupt Cause Set */
/* Interrupt Mask Set */
/* Interrupt Mask Clear */
/* Receive Control */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
/* Receive Descriptor */
/* Flow Control */
/* Receive Descriptor Control */
/* Transmit Descriptor Control */
/* Transmit Configuration Word */
/* Receive Configuration Word */
/* Transmit Control */
/* Receive Checksum Control */
/* Definitions for power management and wakeup registers */
/* Wake Up Control */
/* Wake Up Filter Control */
/* Wake Up Status */
/* Management Control */
* Filtering */
/* Wake Up Packet Length */
/* EEPROM Commands - Microwire */
/* EEPROM Commands - SPI */
/* EEPROM Size definitions */
/* EEPROM Word Offsets */
/* Word definitions for ID LED Settings */
(ID_LED_OFF1_OFF2 << 8) | \
(ID_LED_DEF1_DEF2 << 4) | \
/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
/* Mask bits for fields in Word 0x0a of the EEPROM */
/* Mask bits for fields in Word 0x0f of the EEPROM */
/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
/* EEPROM Map defines (WORD OFFSETS)*/
#define EEPROM_NODE_ADDRESS_BYTE_0 0
/* EEPROM Map Sizes (Byte Counts) */
/* Collision related configuration parameters */
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
/* Default values for the transmit IPG register */
/* Adaptive IFS defines */
#define TX_THRESHOLD_DISABLE 0
/* PBA constants */
/* Flow Control Constants */
/* The historical defaults for the flow control values are given below. */
/* PCIX Config space */
/* Number of bits required to shift right the "pause" bits from the
* EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
*/
/* Number of bits required to shift left the "SWDPIO" bits from the
* EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
*/
/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
* EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
*/
/* Number of bits required to shift left the "ILOS" bit from the EEPROM
* (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
*/
/* Number of milliseconds we wait for auto-negotiation to complete */
/* The carrier extension symbol, as received by the NIC. */
/* TBI_ACCEPT macro definition:
*
* This macro requires:
* adapter = a pointer to struct e1000_hw
* status = the 8 bit status field of the RX descriptor with EOP set
* error = the 8 bit error field of the RX descriptor with EOP set
* length = the sum of all the length fields of the RX descriptors that
* make up the current frame
* last_byte = the last byte of the frame DMAed by the hardware
* max_frame_length = the maximum frame length we want to accept.
* min_frame_length = the minimum frame length we want to accept.
*
* This macro is a conditional that should be used in the interrupt
* handler's Rx processing routine when RxErrors have been detected.
*
* Typical use:
* ...
* if (TBI_ACCEPT) {
* accept_frame = TRUE;
* e1000_tbi_adjust_stats(adapter, MacAddress);
* frame_length--;
* } else {
* accept_frame = FALSE;
* }
* ...
*/
((adapter)->tbi_compatibility_on && \
((last_byte) == CARRIER_EXTENSION) && \
(((status) & E1000_RXD_STAT_VP) ? \
/* Structures, enums, and macros for the PHY */
/* Bit definitions for the Management Data IO (MDIO) and Management Data
* Clock (MDC) pins in the Device Control Register.
*/
/* PHY Registers defined by IEEE */
/* M88E1000 Specific Registers */
/* IGP01E1000 Specific Registers */
/* IGP01E1000 AGC Registers - stores the cable length values*/
/* IGP01E1000 DSP Reset Register */
/* IGP01E1000 PCS Initialization register - stores the polarity status when
* speed = 1000 Mbps. */
/* PHY Control Register */
/* PHY Status Register */
/* Autoneg Advertisement Register */
/* Link Partner Ability Register (Base Page) */
/* Autoneg Expansion Register */
/* Next Page TX Register */
* of different NP
*/
* 0 = cannot comply with msg
*/
* 0 = sending last NP
*/
/* Link Partner Next Page Register */
* of different NP
*/
* 0 = cannot comply with msg
*/
* 0 = sending last NP
*/
/* 1000BASE-T Control Register */
/* 0=DTE device */
/* 0=Configure PHY as Slave */
/* 1000BASE-T Status Register */
/* Extended Status Register */
/* (0=enable, 1=disable) */
/* M88E1000 PHY Specific Control Register */
* 0=CLK125 toggling
*/
/* Manual MDI configuration */
* 100BASE-TX/10BASE-T:
* MDI Mode
*/
* all speeds.
*/
/* 1=Enable Extended 10BASE-T distance
* (Lower 10BASE-T RX Threshold)
* 0=Normal 10BASE-T RX Threshold */
/* 1=5-Bit interface in 100BASE-TX
* 0=MII interface in 100BASE-TX */
/* M88E1000 PHY Specific Status Register */
* 3=110-140M;4=>140M */
/* M88E1000 Extended PHY Specific Control Register */
* Will assert lost lock and bring
* link down if idle not seen
* within 1ms in 1000BASE-T
*/
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the master */
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the slave */
/* IGP01E1000 Specific Port Config Register - R/W */
/* IGP01E1000 Specific Port Status Register - R/O */
/* IGP01E1000 Specific Port Control Register - R/W */
/* IGP01E1000 Specific Port Link Health Register */
/* IGP01E1000 Channel Quality Register */
/* IGP01E1000 DSP reset macros */
/* IGP01E1000 AGC Registers */
/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
/* The precision of the length is +/- 10 meters */
/* IGP01E1000 PCS Initialization register */
/* bits 3:6 in the PCS registers stores the channels polarity */
/* IGP01E1000 GMII FIFO Register */
* on Link-Up */
/* IGP01E1000 Analog Register */
/* Bit definitions for valid PHY IDs. */
/* Miscellaneous PHY bit definitions. */
#endif /* _E1000_HW_H_ */