1N/A/************************************************************************** 1N/AInter Pro 1000 for Etherboot 1N/ADrivers are port from Intel's Linux driver e1000-4.3.15 1N/A***************************************************************************/ 1N/A/******************************************************************************* 1N/A Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved. 1N/A This program is free software; you can redistribute it and/or modify it 1N/A under the terms of the GNU General Public License as published by the Free 1N/A Software Foundation; either version 2 of the License, or (at your option) 1N/A This program is distributed in the hope that it will be useful, but WITHOUT 1N/A ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1N/A FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1N/A You should have received a copy of the GNU General Public License along with 1N/A this program; if not, write to the Free Software Foundation, Inc., 59 1N/A Temple Place - Suite 330, Boston, MA 02111-1307, USA. 1N/A The full GNU General Public License is included in this distribution in the 1N/A file called LICENSE. 1N/A Contact Information: 1N/A Linux NICS <linux.nics@intel.com> 1N/A Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 1N/A*******************************************************************************/ 1N/A * Copyright (C) Archway Digital Solutions. 1N/A * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org> 1N/A * Copyright (C) Linux Networx. 1N/A * Massive upgrade to work with the new intel gigabit NICs. 1N/A * <ebiederman at lnxi dot com> 1N/A * Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by 1N/A * Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc. 1N/A * 01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net> 1N/A/* to get some global routines like printf */ 1N/A/* to get the interface to the body of the program */ 1N/A/* to get the PCI support functions, if this is a PCI NIC */ 1N/A/* Some pieces of code are disabled with #if 0 ... #endif. 1N/A * They are not deleted to show where the etherboot driver differs 1N/A * from the linux driver below the function level. 1N/A * Some member variables of the hw struct have been eliminated 1N/A * and the corresponding inplace checks inserted instead. 1N/A * Pieces such as LED handling that we definitely don't need are deleted. 1N/A * The following defines should not be needed normally, 1N/A * but may be helpful for debugging purposes. */ 1N/A/* Define this if you want to program the transmission control register 1N/A * the way the Linux driver does it. */ 1N/A/* Define this to behave more like the Linux driver. */ 1N/A/* NIC specific static variables go here */ 1N/A/* Function forward declarations */ 1N/A/* Printing macros... */ 1N/A#
define DEBUGOUT7(S,A,B,C,D,E,F,G)
printf(S,A,B,C,D,E,F,G)
1N/A/****************************************************************************** 1N/A * Raises the EEPROM's clock input. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * eecd - EECD's current value 1N/A *****************************************************************************/ 1N/A /* Raise the clock input to the EEPROM (by setting the SK bit), and then 1N/A * wait <delay> microseconds. 1N/A/****************************************************************************** 1N/A * Lowers the EEPROM's clock input. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * eecd - EECD's current value 1N/A *****************************************************************************/ 1N/A /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 1N/A * wait 50 microseconds. 1N/A/****************************************************************************** 1N/A * Shift data bits out to the EEPROM. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * data - data to send to the EEPROM 1N/A * count - number of bits to shift out 1N/A *****************************************************************************/ 1N/A /* We need to shift "count" bits out to the EEPROM. So, value in the 1N/A * "data" parameter will be shifted out to the EEPROM one bit at a time. 1N/A * In order to do this, "data" must be broken down into bits. 1N/A /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 1N/A * and then raising and then lowering the clock (the SK bit controls 1N/A * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 1N/A * by setting "DI" to "0" and then raising and then lowering the clock. 1N/A /* We leave the "DI" bit set to "0" when we leave this routine. */ 1N/A/****************************************************************************** 1N/A * Shift data bits in from the EEPROM 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A /* In order to read a register from the EEPROM, we need to shift 'count' 1N/A * bits in from the EEPROM. Bits are "shifted in" by raising the clock 1N/A * input to the EEPROM (setting the SK bit), and then reading the value of 1N/A * the "DO" bit. During this "shifting in" process the "DI" bit should 1N/A/****************************************************************************** 1N/A * Prepares EEPROM for access 1N/A * hw - Struct containing variables accessed by shared code 1N/A * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 1N/A * function should be called before issuing a command to the EEPROM. 1N/A *****************************************************************************/ 1N/A /* Request EEPROM Access */ 1N/A /* Clear SK and DI */ 1N/A /* Clear SK and CS */ 1N/A/****************************************************************************** 1N/A * Returns EEPROM to a "standby" state 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A /* Deselect EEPROM */ 1N/A /* Toggle CS to flush commands */ 1N/A/****************************************************************************** 1N/A * Terminates a command by inverting the EEPROM's chip select pin 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A /* cleanup eeprom */ 1N/A /* CS on Microwire is active-high */ 1N/A /* Rising edge of clock */ 1N/A /* Falling edge of clock */ 1N/A /* Stop requesting EEPROM access */ 1N/A/****************************************************************************** 1N/A * Reads a 16 bit word from the EEPROM. 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A /* Read "Status Register" repeatedly until the LSB is cleared. The 1N/A * EEPROM will signal that the command has been completed by clearing 1N/A * bit 0 of the internal status register. If it's not cleared within 1N/A * 5 milliseconds, then error out. 1N/A /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 1N/A * only 0-5mSec on 5V devices) 1N/A/****************************************************************************** 1N/A * Reads a 16 bit word from the EEPROM. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * offset - offset of word in the EEPROM to read 1N/A * data - word read from the EEPROM 1N/A * words - number of words to read 1N/A *****************************************************************************/ 1N/A /* A check for invalid values: offset too large, too many words, and not 1N/A /* Prepare the EEPROM for reading */ 1N/A /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 1N/A /* Send the READ command (opcode + addr) */ 1N/A /* Read the data. The address of the eeprom internally increments with 1N/A * each byte (spi) being read, saving on the overhead of eeprom setup 1N/A * and tear-down. The address counter will roll over if reading beyond 1N/A * the size of the eeprom, thus allowing the entire memory to be read 1N/A * starting from any offset. */ 1N/A /* Send the READ command (opcode + addr) */ 1N/A /* Read the data. For microwire, each word requires the overhead 1N/A * of eeprom setup and tear-down. */ 1N/A /* End this read operation */ 1N/A/****************************************************************************** 1N/A * Verifies that the EEPROM has a valid checksum 1N/A * hw - Struct containing variables accessed by shared code 1N/A * Reads the first 64 16 bit words of the EEPROM and sums the values read. 1N/A * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 1N/A *****************************************************************************/ 1N/A/****************************************************************************** 1N/A * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 1N/A * second function of dual function devices 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A /* Invert the last bit if this is the second device */ 1N/A/****************************************************************************** 1N/A * Initializes receive address filters. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * Places the MAC address in receive address register 0 and clears the rest 1N/A * of the receive addresss registers. Clears the multicast table. Assumes 1N/A * the receiver is in reset when the routine is called. 1N/A *****************************************************************************/ 1N/A /* Setup the receive address. */ 1N/A /* Zero out the other 15 receive addresses. */ 1N/A/****************************************************************************** 1N/A * Clears the VLAN filer table 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A/****************************************************************************** 1N/A* Writes a value to one of the devices registers using port I/O (as opposed to 1N/A* memory mapped I/O). Only 82544 and newer devices support port I/O. * 1N/A* hw - Struct containing variables accessed by shared code 1N/A* offset - offset to write to * value - value to write 1N/A*****************************************************************************/ 1N/A/****************************************************************************** 1N/A * Set the phy type member in the hw struct. 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A /* Should never have loaded on this device */ 1N/A/****************************************************************************** 1N/A * IGP phy init script - initializes the GbE PHY 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A /* See e1000_sw_init() of the Linux driver */ 1N/A /* Move to analog registers page */ 1N/A/****************************************************************************** 1N/A * Set the mac type member in the hw struct. 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A /* Invalid 82542 revision ID */ 1N/A /* Should never have loaded on this device */ 1N/A/***************************************************************************** 1N/A * Set media type and TBI compatibility. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * **************************************************************************/ 1N/A /* tbi_compatibility is only valid on 82543 */ 1N/A /* tbi_compatibility not valid on fiber */ 1N/A /* This is an 82542 (fiber only) */ 1N/A/****************************************************************************** 1N/A * Reset the transmit and receive units; mask and clear all interrupts. 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 1N/A /* Clear interrupt mask to stop board from generating interrupts */ 1N/A /* Disable the Transmit and Receive units. Then delay to allow 1N/A * any pending transactions to complete before we hit the MAC with 1N/A /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 1N/A /* Delay to allow any outstanding PCI transactions to complete before 1N/A * resetting the device 1N/A /* Must reset the PHY before resetting the MAC */ 1N/A /* Issue a global reset to the MAC. This will reset the chip's 1N/A * transmit, receive, DMA, and link units. It will not effect 1N/A * the current PCI configuration. The global reset bit is self- 1N/A * clearing, and should clear within a microsecond. 1N/A /* These controllers can't ack the 64-bit write when issuing the 1N/A * reset, so use IO-mapping as a workaround to issue the reset */ 1N/A /* Reset is performed on a shadow of the control register */ 1N/A /* After MAC reset, force reload of EEPROM to restore power-on settings to 1N/A * device. Later controllers reload the EEPROM automatically, so just wait 1N/A * for reload to complete. 1N/A /* Wait for reset to complete */ 1N/A /* Wait for EEPROM reload */ 1N/A /* Wait for EEPROM reload */ 1N/A /* Wait for EEPROM reload (it happens automatically) */ 1N/A /* Disable HW ARPs on ASF enabled adapters */ 1N/A /* Clear interrupt mask to stop board from generating interrupts */ 1N/A /* Clear any pending interrupt events. */ 1N/A /* If MWI was previously enabled, reenable it. */ 1N/A/****************************************************************************** 1N/A * Performs basic configuration of the adapter. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * Assumes that the controller has previously been reset and is in a 1N/A * post-reset uninitialized state. Initializes the receive address registers, 1N/A * multicast table, and VLAN filter table. Calls routines to setup link 1N/A * configuration and flow control settings. Clears all on-chip counters. Leaves 1N/A * the transmit and receive units disabled and uninitialized. 1N/A *****************************************************************************/ 1N/A /* Set the media type and TBI compatibility */ 1N/A /* Disabling VLAN filtering. */ 1N/A /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1N/A /* Setup the receive address. This involves initializing all of the Receive 1N/A * Address Registers (RARs 0 - 15). 1N/A /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 1N/A /* Zero out the Multicast HASH table */ 1N/A /* Set the PCI priority bit correctly in the CTRL register. This 1N/A * determines if the adapter gives priority to receives, or if it 1N/A * gives equal priority to transmits and receives. 1N/A /* See e1000_get_bus_info() of the Linux driver */ 1N/A /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 1N/A /* Call a subroutine to configure the link and setup flow control. */ 1N/A /* Set the transmit descriptor write-back policy */ 1N/A /* Clear all of the statistics registers (clear on read). It is 1N/A * important that we do this after we have tried to establish link 1N/A * because the symbol error count will increment wildly if there 1N/A/****************************************************************************** 1N/A * Adjust SERDES output amplitude based on EEPROM setting. 1N/A * hw - Struct containing variables accessed by shared code. 1N/A *****************************************************************************/ 1N/A /* Adjust SERDES output amplitude only. */ 1N/A/****************************************************************************** 1N/A * Configures flow control and link settings. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * Determines which flow control settings to use. Calls the apropriate media- 1N/A * specific link configuration function. Configures the flow control settings. 1N/A * Assuming the adapter has a valid link partner, a valid link should be 1N/A * established. Assumes the hardware has previously been reset and the 1N/A * transmitter and receiver are not enabled. 1N/A *****************************************************************************/ 1N/A /* Read and store word 0x0F of the EEPROM. This word contains bits 1N/A * that determine the hardware's default PAUSE (flow control) mode, 1N/A * a bit that determines whether the HW defaults to enabling or 1N/A * disabling auto-negotiation, and the direction of the 1N/A * SW defined pins. If there is no SW over-ride of the flow 1N/A * control setting, then the variable hw->fc will 1N/A * be initialized based on a value in the EEPROM. 1N/A /* We want to save off the original Flow Control configuration just 1N/A * in case we get disconnected and then reconnected into a different 1N/A * hub or switch with different Flow Control capabilities. 1N/A /* See e1000_sw_init() of the Linux driver */ 1N/A /* Take the 4 bits from EEPROM word 0x0F that determine the initial 1N/A * polarity value for the SW controlled pins, and setup the 1N/A * Extended Device Control reg with that info. 1N/A * This is needed because one of the SW controlled pins is used for 1N/A * signal detection. So this should be done before e1000_setup_pcs_link() 1N/A * or e1000_phy_setup() is called. 1N/A /* Call the necessary subroutine to configure the link. */ 1N/A /* Initialize the flow control address, type, and PAUSE timer 1N/A * registers to their default values. This is done even if flow 1N/A * control is disabled, because it does not hurt anything to 1N/A * initialize these registers. 1N/A DEBUGOUT(
"Initializing the Flow Control address, type and timer regs\n");
1N/A /* Set the flow control receive threshold registers. Normally, 1N/A * these registers will be set to a default threshold that may be 1N/A * adjusted later by the driver's runtime code. However, if the 1N/A * ability to transmit pause frames in not enabled, then these 1N/A * registers will be set to 0. 1N/A /* We need to set up the Receive Threshold high and low water marks 1N/A * as well as (optionally) enabling the transmission of XON frames. 1N/A/****************************************************************************** 1N/A * Sets up link for a fiber based or serdes based adapter 1N/A * hw - Struct containing variables accessed by shared code 1N/A * Manipulates Physical Coding Sublayer functions in order to configure 1N/A * link. Assumes the hardware has been previously reset and the transmitter 1N/A * and receiver are not enabled. 1N/A *****************************************************************************/ 1N/A /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 1N/A * set when the optics detect a signal. On older adapters, it will be 1N/A * cleared when there is a signal. This applies to fiber media only. 1N/A * If we're on serdes media, adjust the output amplitude to value set in 1N/A /* Take the link out of reset */ 1N/A /* Adjust VCO speed to improve BER performance */ 1N/A /* Check for a software override of the flow control settings, and setup 1N/A * the device accordingly. If auto-negotiation is enabled, then software 1N/A * will have to set the "PAUSE" bits to the correct value in the Tranmsit 1N/A * Config Word Register (TXCW) and re-start auto-negotiation. However, if 1N/A * auto-negotiation is disabled, then software will have to manually 1N/A * configure the two flow control enable bits in the CTRL register. 1N/A * The possible values of the "fc" parameter are: 1N/A * 0: Flow control is completely disabled 1N/A * 1: Rx flow control is enabled (we can receive pause frames, but 1N/A * not send pause frames). 1N/A * 2: Tx flow control is enabled (we can send pause frames but we do 1N/A * not support receiving pause frames). 1N/A * 3: Both Rx and TX flow control (symmetric) are enabled. 1N/A /* Flow control is completely disabled by a software over-ride. */ 1N/A /* RX Flow control is enabled and TX Flow control is disabled by a 1N/A * software over-ride. Since there really isn't a way to advertise 1N/A * that we are capable of RX Pause ONLY, we will advertise that we 1N/A * support both symmetric and asymmetric RX PAUSE. Later, we will 1N/A * disable the adapter's ability to send PAUSE frames. 1N/A /* TX Flow control is enabled, and RX Flow control is disabled, by a 1N/A * software over-ride. 1N/A /* Flow control (both RX and TX) is enabled by a software over-ride. */ 1N/A /* Since auto-negotiation is enabled, take the link out of reset (the link 1N/A * will be in reset, because we previously reset the chip). This will 1N/A * restart auto-negotiation. If auto-neogtiation is successful then the 1N/A * link-up status bit will be set and the flow control enable bits (RFCE 1N/A * and TFCE) will be set according to their negotiated value. 1N/A /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 1N/A * indication in the Device Status Register. Time-out if a link isn't 1N/A * seen in 500 milliseconds seconds (Auto-negotiation should complete in 1N/A * less than 500 milliseconds even if the other end is doing it in SW). 1N/A * For internal serdes, we just assume a signal is present, then poll. 1N/A /* AutoNeg failed to achieve a link, so we'll call 1N/A * e1000_check_for_link. This routine will force the link up if 1N/A * we detect a signal. This will allow us to communicate with 1N/A * non-autonegotiating link partners. 1N/A/****************************************************************************** 1N/A* Detects which PHY is present and the speed and duplex 1N/A* hw - Struct containing variables accessed by shared code 1N/A******************************************************************************/ 1N/A /* With 82543, we need to force speed and duplex on the MAC equal to what 1N/A * the PHY speed and duplex configuration is. In addition, we need to 1N/A * perform a hardware reset on the PHY to take it out of reset. 1N/A /* Make sure we have a valid PHY */ 1N/A /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1N/A /* disable lplu d3 during driver init */ 1N/A /* Configure mdi-mdix settings */ 1N/A /* Force MDI for IGP B-0 PHY */ 1N/A /* set auto-master slave resolution settings */ 1N/A /* when autonegotiation advertisment is only 1000Mbps then we 1N/A * should disable SmartSpeed and enable Auto MasterSlave 1N/A * resolution as hardware default. */ 1N/A /* Disable SmartSpeed */ 1N/A /* load defaults for future use */ 1N/A /* Enable CRS on TX. This must be set for half-duplex operation. */ 1N/A * 0 - Auto for all speeds 1N/A * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1N/A * disable_polarity_correction = 0 (default) 1N/A * Automatic Correction for Reversed Cable Polarity 1N/A /* Force TX_CLK in the Extended PHY Specific Control Register 1N/A /* Configure Master and Slave downshift values */ 1N/A /* SW Reset the PHY so all changes take effect */ 1N/A * autoneg = 1 (default) 1N/A * PHY will advertise value(s) parsed from 1N/A * autoneg_advertised and fc 1N/A * PHY will be set to 10H, 10F, 100H, or 100F 1N/A * depending on value parsed from forced_speed_duplex. 1N/A /* Is autoneg enabled? This is enabled by default or by software 1N/A * override. If so, call e1000_phy_setup_autoneg routine to parse the 1N/A * autoneg_advertised and fc options. If autoneg is NOT enabled, then 1N/A * call e1000_phy_force_speed_duplex to parse and set this up. 1N/A /* Perform some bounds checking on the hw->autoneg_advertised 1N/A * parameter. If this variable is zero, then set it to the default. 1N/A /* If autoneg_advertised is zero, we assume it was not defaulted 1N/A * by the calling code so we set to advertise full capability. 1N/A DEBUGOUT(
"Reconfiguring auto-neg advertisement params\n");
1N/A /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1N/A * the Auto Neg Restart bit in the PHY control register. 1N/A /* Does the user want to wait for Auto-Neg to complete here, or 1N/A * check at a later time (for example, callback routine). 1N/A DEBUGOUT(
"Error while waiting for autoneg to complete\n");
1N/A /* If we do not wait for autonegotiation to complete I 1N/A * do not see a valid link status. 1N/A DEBUGOUT(
"Error while waiting for autoneg to complete\n");
1N/A }
/* !hw->phy_reset_disable */ 1N/A /* Check link status. Wait up to 100 microseconds for link to become 1N/A for(i = 0; i <
10; i++) {
1N/A /* We have link, so we need to finish the config process: 1N/A * if we are on 82543. If we 1N/A * are on newer silicon, we only need to configure 1N/A * collision distance in the Transmit Control Register. 1N/A * 2) Set up flow control on the MAC to that established with 1N/A/****************************************************************************** 1N/A* Configures PHY autoneg and flow control advertisement settings 1N/A* hw - Struct containing variables accessed by shared code 1N/A******************************************************************************/ 1N/A /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1N/A /* Read the MII 1000Base-T Control Register (Address 9). */ 1N/A /* Need to parse both autoneg_advertised and fc and set up 1N/A * the appropriate PHY registers. First we will parse for 1N/A * autoneg_advertised software override. Since we can advertise 1N/A * a plethora of combinations, we need to check each bit 1N/A /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1N/A * Advertisement Register (Address 4) and the 1000 mb speed bits in 1N/A * the 1000Base-T Control Register (Address 9). 1N/A /* Do we want to advertise 10 Mb Half Duplex? */ 1N/A /* Do we want to advertise 10 Mb Full Duplex? */ 1N/A /* Do we want to advertise 100 Mb Half Duplex? */ 1N/A /* Do we want to advertise 100 Mb Full Duplex? */ 1N/A /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1N/A DEBUGOUT(
"Advertise 1000mb Half duplex requested, request denied!\n");
1N/A /* Do we want to advertise 1000 Mb Full Duplex? */ 1N/A /* Check for a software override of the flow control settings, and 1N/A * setup the PHY advertisement registers accordingly. If 1N/A * auto-negotiation is enabled, then software will have to set the 1N/A * "PAUSE" bits to the correct value in the Auto-Negotiation 1N/A * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1N/A * The possible values of the "fc" parameter are: 1N/A * 0: Flow control is completely disabled 1N/A * 1: Rx flow control is enabled (we can receive pause frames 1N/A * but not send pause frames). 1N/A * 2: Tx flow control is enabled (we can send pause frames 1N/A * but we do not support receiving pause frames). 1N/A * 3: Both Rx and TX flow control (symmetric) are enabled. 1N/A * other: No software override. The flow control configuration 1N/A * in the EEPROM is used. 1N/A /* Flow control (RX & TX) is completely disabled by a 1N/A * software over-ride. 1N/A /* RX Flow control is enabled, and TX Flow control is 1N/A * disabled, by a software over-ride. 1N/A /* Since there really isn't a way to advertise that we are 1N/A * capable of RX Pause ONLY, we will advertise that we 1N/A * support both symmetric and asymmetric RX PAUSE. Later 1N/A * (in e1000_config_fc_after_link_up) we will disable the 1N/A *hw's ability to send PAUSE frames. 1N/A /* TX Flow control is enabled, and RX Flow control is 1N/A * disabled, by a software over-ride. 1N/A /* Flow control (both RX and TX) is enabled by a software 1N/A/****************************************************************************** 1N/A* Sets the collision distance in the Transmit Control register 1N/A* hw - Struct containing variables accessed by shared code 1N/A* Link should have been established previously. Reads the speed and duplex 1N/A* information from the Device Status register. 1N/A******************************************************************************/ 1N/A/****************************************************************************** 1N/A* Sets MAC speed and duplex settings to reflect the those in the PHY 1N/A* hw - Struct containing variables accessed by shared code 1N/A* mii_reg - data to write to the MII control register 1N/A* The contents of the PHY register containing the needed information need to 1N/A******************************************************************************/ 1N/A /* Read the Device Control Register and set the bits to Force Speed 1N/A /* Set up duplex in the Device Control and Transmit Control 1N/A * registers depending on negotiated values. 1N/A /* Set up speed in the Device Control register depending on 1N/A * negotiated values. 1N/A /* Set up speed in the Device Control register depending on 1N/A * negotiated values. 1N/A /* Write the configured values back to the Device Control Reg. */ 1N/A/****************************************************************************** 1N/A * Forces the MAC's flow control settings. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * Sets the TFCE and RFCE bits in the device control register to reflect 1N/A * the adapter settings. TFCE and RFCE need to be explicitly set by 1N/A * software when a Copper PHY is used because autonegotiation is managed 1N/A * by the PHY rather than the MAC. Software must also configure these 1N/A * bits when link is forced on a fiber connection. 1N/A *****************************************************************************/ 1N/A /* Get the current configuration of the Device Control Register */ 1N/A /* Because we didn't get link via the internal auto-negotiation 1N/A * mechanism (we either forced link or we got link via PHY 1N/A * receive flow control. 1N/A * according to the "hw->fc" parameter. 1N/A * The possible values of the "fc" parameter are: 1N/A * 0: Flow control is completely disabled 1N/A * 1: Rx flow control is enabled (we can receive pause 1N/A * frames but not send pause frames). 1N/A * 2: Tx flow control is enabled (we can send pause frames 1N/A * frames but we do not receive pause frames). 1N/A * 3: Both Rx and TX flow control (symmetric) is enabled. 1N/A * other: No other values should be possible at this point. 1N/A /* Disable TX Flow Control for 82542 (rev 2.0) */ 1N/A/****************************************************************************** 1N/A * Configures flow control settings after link is established 1N/A * hw - Struct containing variables accessed by shared code 1N/A * Should be called immediately after a valid link has been established. 1N/A * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1N/A * and autonegotiation is enabled, the MAC flow control settings will be set 1N/A * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1N/A * and RFCE bits will be automaticaly set to the negotiated flow control mode. 1N/A *****************************************************************************/ 1N/A /* Check for the case where we have fiber media and auto-neg failed 1N/A * so we had to force link. In this case, we need to force the 1N/A * configuration of the MAC to match the "fc" parameter. 1N/A /* Check for the case where we have copper media and auto-neg is 1N/A * enabled. In this case, we need to check and see if Auto-Neg 1N/A * has completed, and if so, how the PHY and link partner has 1N/A * flow control configured. 1N/A /* Read the MII Status Register and check to see if AutoNeg 1N/A * has completed. We read this twice because this reg has 1N/A * some "sticky" (latched) bits. 1N/A /* The AutoNeg process has completed, so we now need to 1N/A * read both the Auto Negotiation Advertisement Register 1N/A * (Address 4) and the Auto_Negotiation Base Page Ability 1N/A * Register (Address 5) to determine how flow control was 1N/A /* Two bits in the Auto Negotiation Advertisement Register 1N/A * (Address 4) and two bits in the Auto Negotiation Base 1N/A * Page Ability Register (Address 5) determine flow control 1N/A * for both the PHY and the link partner. The following 1N/A * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1N/A * 1999, describes these PAUSE resolution bits and how flow 1N/A * control is determined based upon these settings. 1N/A * NOTE: DC = Don't Care 1N/A * LOCAL DEVICE | LINK PARTNER 1N/A * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1N/A *-------|---------|-------|---------|-------------------- 1N/A * 0 | 0 | DC | DC | e1000_fc_none 1N/A * 0 | 1 | 0 | DC | e1000_fc_none 1N/A * 0 | 1 | 1 | 0 | e1000_fc_none 1N/A * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1N/A * 1 | 0 | 0 | DC | e1000_fc_none 1N/A * 1 | DC | 1 | DC | e1000_fc_full 1N/A * 1 | 1 | 0 | 0 | e1000_fc_none 1N/A * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1N/A /* Are both PAUSE bits set to 1? If so, this implies 1N/A * Symmetric Flow Control is enabled at both ends. The 1N/A * ASM_DIR bits are irrelevant per the spec. 1N/A * For Symmetric Flow Control: 1N/A * LOCAL DEVICE | LINK PARTNER 1N/A * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1N/A *-------|---------|-------|---------|-------------------- 1N/A * 1 | DC | 1 | DC | e1000_fc_full 1N/A /* Now we need to check if the user selected RX ONLY 1N/A * of pause frames. In this case, we had to advertise 1N/A * FULL flow control because we could not advertise RX 1N/A * ONLY. Hence, we must now check to see if we need to 1N/A * turn OFF the TRANSMISSION of PAUSE frames. 1N/A /* For receiving PAUSE frames ONLY. 1N/A * LOCAL DEVICE | LINK PARTNER 1N/A * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1N/A *-------|---------|-------|---------|-------------------- 1N/A * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1N/A /* For transmitting PAUSE frames ONLY. 1N/A * LOCAL DEVICE | LINK PARTNER 1N/A * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1N/A *-------|---------|-------|---------|-------------------- 1N/A * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1N/A /* Per the IEEE spec, at this point flow control should be 1N/A * disabled. However, we want to consider that we could 1N/A * be connected to a legacy switch that doesn't advertise 1N/A * desired flow control, but can be forced on the link 1N/A * partner. So if we advertised no flow control, that is 1N/A * what we will resolve to. If we advertised some kind of 1N/A * receive capability (Rx Pause Only or Full Flow Control) 1N/A * and the link partner advertised none, we will configure 1N/A * ourselves to enable Rx Flow Control only. We can do 1N/A * this safely for two reasons: If the link partner really 1N/A * didn't want flow control enabled, and we enable Rx, no 1N/A * harm done since we won't be receiving any PAUSE frames 1N/A * anyway. If the intent on the link partner was to have 1N/A * flow control enabled, then by us enabling RX only, we 1N/A * can at least receive pause frames and process them. 1N/A * This is a good idea because in most cases, since we are 1N/A * predominantly a server NIC, more times than not we will 1N/A * be asked to delay transmission of packets than asking 1N/A * our link partner to pause transmission of frames. 1N/A /* Now we need to do one last check... If we auto- 1N/A * negotiated to HALF DUPLEX, flow control should not be 1N/A * enabled per IEEE 802.3 spec. 1N/A /* Now we call a subroutine to actually force the MAC 1N/A * controller to use the correct flow control settings. 1N/A DEBUGOUT(
"Copper PHY and Auto Neg has not completed.\r\n");
1N/A/****************************************************************************** 1N/A * Checks to see if the link status of the hardware has changed. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * Called by any function that needs to check the link status of the adapter. 1N/A *****************************************************************************/ 1N/A /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 1N/A * set when the optics detect a signal. On older adapters, it will be 1N/A * cleared when there is a signal. This applies to fiber media only. 1N/A /* If we have a copper PHY then we only want to go out to the PHY 1N/A * registers to see if Auto-Neg has completed and/or if our link 1N/A * status has changed. The get_link_status flag will be set if we 1N/A * receive a Link Status Change interrupt or we have Rx Sequence 1N/A /* First we want to see if the MII Status Register reports 1N/A * Read the register twice since the link bit is sticky. 1N/A /* No link detected */ 1N/A /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 1N/A * have Si on board that is 82544 or newer, Auto 1N/A * configuration. So we only need to configure Collision 1N/A * Distance in the MAC. Otherwise, we need to force 1N/A /* Configure Flow Control now that Auto-Neg has completed. First, we 1N/A * need to restore the desired flow control settings because we may 1N/A * have had to re-autoneg with a different link partner. 1N/A /* At this point we know that we are on copper and we have 1N/A * auto-negotiated link. These are conditions for checking the link 1N/A * parter capability register. We use the link partner capability to 1N/A * determine if TBI Compatibility needs to be turned on or off. If 1N/A * the link partner advertises any speed in addition to Gigabit, then 1N/A * we assume that they are GMII-based, and TBI compatibility is not 1N/A * needed. If no other speeds are advertised, we assume the link 1N/A * partner is TBI-based, and we turn on TBI Compatibility. 1N/A /* If our link partner advertises anything in addition to 1N/A * gigabit, we do not need to enable TBI compatibility. 1N/A /* If we previously were in the mode, turn it off. */ 1N/A /* If TBI compatibility is was previously off, turn it on. For 1N/A * compatibility with a TBI link partner, we will store bad 1N/A * packets. Some frames have an additional byte on the end and 1N/A * will look like CRC errors to to the hardware. 1N/A /* If we don't have link (auto-negotiation failed or link partner cannot 1N/A * auto-negotiate), the cable is plugged in (we have signal), and our 1N/A * link partner is not trying to auto-negotiate with us (we are receiving 1N/A * idles or data), we need to force link up. We also need to give 1N/A * auto-negotiation time to complete, in case the cable was just plugged 1N/A * in. The autoneg_failed flag does this. 1N/A DEBUGOUT(
"NOT RXing /C/, disable AutoNeg and force link.\r\n");
1N/A /* Disable auto-negotiation in the TXCW register */ 1N/A /* Force link-up and also force full-duplex. */ 1N/A /* Configure Flow Control after forcing link up. */ 1N/A /* If we are forcing link and we are receiving /C/ ordered sets, re-enable 1N/A * auto-negotiation in the TXCW register and disable forced link in the 1N/A * Device Control register in an attempt to auto-negotiate with our link 1N/A DEBUGOUT(
"RXing /C/, enable AutoNeg and stop forcing link.\r\n");
1N/A /* If we force link for non-auto-negotiation switch, check link status 1N/A * based on MAC synchronization for internal serdes media type. 1N/A /* SYNCH bit and IV bit are sticky. */ 1N/A/****************************************************************************** 1N/A * Detects the current speed and duplex settings of the hardware. 1N/A * hw - Struct containing variables accessed by shared code 1N/A * speed - Speed of the connection 1N/A * duplex - Duplex setting of the connection 1N/A *****************************************************************************/ 1N/A/****************************************************************************** 1N/A* Blocks until autoneg completes or times out (~4.5 seconds) 1N/A* hw - Struct containing variables accessed by shared code 1N/A******************************************************************************/ 1N/A /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 1N/A /* Read the MII Status Register and wait for Auto-Neg 1N/A * Complete bit to be set. 1N/A/****************************************************************************** 1N/A* Raises the Management Data Clock 1N/A* hw - Struct containing variables accessed by shared code 1N/A* ctrl - Device control register's current value 1N/A******************************************************************************/ 1N/A /* Raise the clock input to the Management Data Clock (by setting the MDC 1N/A * bit), and then delay 10 microseconds. 1N/A/****************************************************************************** 1N/A* Lowers the Management Data Clock 1N/A* hw - Struct containing variables accessed by shared code 1N/A* ctrl - Device control register's current value 1N/A******************************************************************************/ 1N/A /* Lower the clock input to the Management Data Clock (by clearing the MDC 1N/A * bit), and then delay 10 microseconds. 1N/A/****************************************************************************** 1N/A* Shifts data bits out to the PHY 1N/A* hw - Struct containing variables accessed by shared code 1N/A* data - Data to send out to the PHY 1N/A* count - Number of bits to shift out 1N/A* Bits are shifted out in MSB to LSB order. 1N/A******************************************************************************/ 1N/A /* We need to shift "count" number of bits out to the PHY. So, the value 1N/A * in the "data" parameter will be shifted out to the PHY one bit at a 1N/A * time. In order to do this, "data" must be broken down into bits. 1N/A /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 1N/A /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 1N/A * then raising and lowering the Management Data Clock. A "0" is 1N/A * shifted out to the PHY by setting the MDIO bit to "0" and then 1N/A * raising and lowering the clock. 1N/A/****************************************************************************** 1N/A* Shifts data bits in from the PHY 1N/A* hw - Struct containing variables accessed by shared code 1N/A* Bits are shifted in in MSB to LSB order. 1N/A******************************************************************************/ 1N/A /* In order to read a register from the PHY, we need to shift in a total 1N/A * of 18 bits from the PHY. The first two bit (turnaround) times are used 1N/A * to avoid contention on the MDIO pin when a read operation is performed. 1N/A * These two bits are ignored by us and thrown away. Bits are "shifted in" 1N/A * by raising the input to the Management Data Clock (setting the MDC bit), 1N/A * and then reading the value of the MDIO bit. 1N/A /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 1N/A /* Raise and Lower the clock before reading in the data. This accounts for 1N/A * the turnaround bits. The first clock occurred when we clocked out the 1N/A * last bit of the Register Address. 1N/A for(
data = 0, i = 0; i <
16; i++) {
1N/A /* Check to see if we shifted in a "1". */ 1N/A/***************************************************************************** 1N/A* Reads the value from a PHY register, if the value is on a specific non zero 1N/A* page, sets the page first. 1N/A* hw - Struct containing variables accessed by shared code 1N/A* reg_addr - address of the PHY register to read 1N/A******************************************************************************/ 1N/A /* Set up Op-code, Phy Address, and register address in the MDI 1N/A * Control register. The MAC will take care of interfacing with the 1N/A * PHY to retrieve the desired data. 1N/A /* Poll the ready bit to see if the MDI read completed */ 1N/A for(i = 0; i <
64; i++) {
1N/A /* We must first send a preamble through the MDIO pin to signal the 1N/A * beginning of an MII instruction. This is done by sending 32 1N/A * consecutive "1" bits. 1N/A /* Now combine the next few fields that are required for a read 1N/A * operation. We use this method instead of calling the 1N/A * e1000_shift_out_mdi_bits routine five different times. The format of 1N/A * a MII read instruction consists of a shift out of 14 bits and is 1N/A * defined as follows: 1N/A * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 1N/A * followed by a shift in of 18 bits. This first two bits shifted in 1N/A * are TurnAround bits used to avoid contention on the MDIO pin when a 1N/A * READ operation is performed. These two bits are thrown away 1N/A * followed by a shift in of 16 bits which contains the desired data. 1N/A /* Now that we've shifted out the read command to the MII, we need to 1N/A * "shift in" the 16-bit value (18 total bits) of the requested PHY 1N/A/****************************************************************************** 1N/A* Writes a value to a PHY register 1N/A* hw - Struct containing variables accessed by shared code 1N/A* reg_addr - address of the PHY register to write 1N/A* data - data to write to the PHY 1N/A******************************************************************************/ 1N/A /* Set up Op-code, Phy Address, register address, and data intended 1N/A * for the PHY register in the MDI Control register. The MAC will take 1N/A * care of interfacing with the PHY to send the desired data. 1N/A /* Poll the ready bit to see if the MDI read completed */ 1N/A for(i = 0; i <
640; i++) {
1N/A /* We'll need to use the SW defined pins to shift the write command 1N/A * out to the PHY. We first send a preamble to the PHY to signal the 1N/A * beginning of the MII instruction. This is done by sending 32 1N/A * consecutive "1" bits. 1N/A /* Now combine the remaining required fields that will indicate a 1N/A * write operation. We use this method instead of calling the 1N/A * e1000_shift_out_mdi_bits routine for each field in the command. The 1N/A * format of a MII write instruction is as follows: 1N/A * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 1N/A/****************************************************************************** 1N/A* Returns the PHY to the power-on reset state 1N/A* hw - Struct containing variables accessed by shared code 1N/A******************************************************************************/ 1N/A /* Read the device control register and assert the E1000_CTRL_PHY_RST 1N/A * bit. Then, take it out of reset. 1N/A /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 1N/A * bit to put the PHY into reset. Then, take it out of reset. 1N/A/****************************************************************************** 1N/A* hw - Struct containing variables accessed by shared code 1N/A* Sets bit 15 of the MII Control regiser 1N/A******************************************************************************/ 1N/A/****************************************************************************** 1N/A* Probes the expected PHY address for known PHY IDs 1N/A* hw - Struct containing variables accessed by shared code 1N/A******************************************************************************/ 1N/A /* Read the PHY ID Registers to identify which PHY is onboard. */ 1N/A/****************************************************************************** 1N/A * Sets up eeprom variables in the hw struct. Must be called after mac_type 1N/A * hw - Struct containing variables accessed by shared code 1N/A *****************************************************************************/ 1N/A * e1000_reset - Reset the adapter 1N/A /* Repartition Pba for greater than 9k mtu 1N/A * To take effect CTRL.RST is required. 1N/A /* flow control settings */ 1N/A * e1000_sw_init - Initialize general software structures (struct e1000_adapter) 1N/A * @adapter: board private structure to initialize 1N/A * e1000_sw_init initializes the Adapter private data structure. 1N/A * Fields are initialized based on PCI device information and 1N/A * OS network device settings (MTU size). 1N/A /* PCI config space info */ 1N/A /* identify the MAC */ 1N/A /* initialize eeprom parameters */ 1N/A /* Copper options */ 1N/A /* Setup the HW Tx Head and Tail descriptor pointers */ 1N/A /* Program the Transmit Control Register */ 1N/A /* disable receive */ 1N/A /* Setup the Base and Length of the Rx Descriptor Ring */ 1N/A /* Setup the HW Rx Head and Tail Descriptor Pointers */ 1N/A/************************************************************************** 1N/APOLL - Wait for a frame 1N/A***************************************************************************/ 1N/A /* return true if there's an ethernet packet ready to read */ 1N/A /* nic->packet should contain data on return */ 1N/A /* nic->packetlen should contain length of data */ 1N/A // printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length); 1N/A/************************************************************************** 1N/ATRANSMIT - Transmit a frame 1N/A***************************************************************************/ 1N/A const char *p)
/* Packet */ 1N/A /* send the packet to destination */ 1N/A udelay(
10);
/* give the nic a chance to write to the register */ 1N/A/************************************************************************** 1N/ADISABLE - Turn off ethernet interface 1N/A***************************************************************************/ 1N/A /* Clear the transmit ring */ 1N/A /* Clear the receive ring */ 1N/A /* put the card in its initial state */ 1N/A /* Turn off the ethernet interface */ 1N/A /* Unmap my window to the device */ 1N/A/************************************************************************** 1N/AIRQ - Enable, Disable, or Force interrupts 1N/A***************************************************************************/ 1N/A/************************************************************************** 1N/APROBE - Look for an adapter, this routine's visible to the outside 1N/AYou should omit the last argument struct pci_device * for a non-PCI NIC 1N/A***************************************************************************/ 1N/A /* Initialize hw with default values */ 1N/A /* Are these variables needed? */ 1N/A /* From Matt Hortman <mbhortman@acpthinclient.com> */ 1N/A /* MAC and Phy settings */ 1N/A /* setup the private structure */ 1N/A /* make sure the EEPROM is good */ 1N/A printf (
"The EEPROM Checksum Is Not Valid\n");
1N/A /* copy the MAC address out of the EEPROM */ 1N/A /* reset the hardware with the new settings */ 1N/A /* point to NIC specific routines */ 1N/APCI_ROM(
0x8086,
0x1000,
"e1000-82542",
"Intel EtherExpressPro1000"),
1N/APCI_ROM(
0x8086,
0x1001,
"e1000-82543gc-fiber",
"Intel EtherExpressPro1000 82543GC Fiber"),
1N/APCI_ROM(
0x8086,
0x1004,
"e1000-82543gc-copper",
"Intel EtherExpressPro1000 82543GC Copper"),
1N/APCI_ROM(
0x8086,
0x1008,
"e1000-82544ei-copper",
"Intel EtherExpressPro1000 82544EI Copper"),
1N/APCI_ROM(
0x8086,
0x1009,
"e1000-82544ei-fiber",
"Intel EtherExpressPro1000 82544EI Fiber"),
1N/APCI_ROM(
0x8086,
0x100C,
"e1000-82544gc-copper",
"Intel EtherExpressPro1000 82544GC Copper"),
1N/APCI_ROM(
0x8086,
0x100D,
"e1000-82544gc-lom",
"Intel EtherExpressPro1000 82544GC LOM"),
1N/APCI_ROM(
0x8086,
0x100E,
"e1000-82540em",
"Intel EtherExpressPro1000 82540EM"),
1N/APCI_ROM(
0x8086,
0x100F,
"e1000-82545em-copper",
"Intel EtherExpressPro1000 82545EM Copper"),
1N/APCI_ROM(
0x8086,
0x1010,
"e1000-82546eb-copper",
"Intel EtherExpressPro1000 82546EB Copper"),
1N/APCI_ROM(
0x8086,
0x1011,
"e1000-82545em-fiber",
"Intel EtherExpressPro1000 82545EM Fiber"),
1N/APCI_ROM(
0x8086,
0x1012,
"e1000-82546eb-fiber",
"Intel EtherExpressPro1000 82546EB Copper"),
1N/APCI_ROM(
0x8086,
0x1013,
"e1000-82541ei",
"Intel EtherExpressPro1000 82541EI"),
1N/APCI_ROM(
0x8086,
0x1015,
"e1000-82540em-lom",
"Intel EtherExpressPro1000 82540EM LOM"),
1N/APCI_ROM(
0x8086,
0x1016,
"e1000-82540ep-lom",
"Intel EtherExpressPro1000 82540EP LOM"),
1N/APCI_ROM(
0x8086,
0x1017,
"e1000-82540ep",
"Intel EtherExpressPro1000 82540EP"),
1N/APCI_ROM(
0x8086,
0x1018,
"e1000-82541ep",
"Intel EtherExpressPro1000 82541EP"),
1N/APCI_ROM(
0x8086,
0x1019,
"e1000-82547ei",
"Intel EtherExpressPro1000 82547EI"),
1N/APCI_ROM(
0x8086,
0x101d,
"e1000-82546eb-quad-copper",
"Intel EtherExpressPro1000 82546EB Quad Copper"),
1N/APCI_ROM(
0x8086,
0x101e,
"e1000-82540ep-lp",
"Intel EtherExpressPro1000 82540EP LP"),
1N/APCI_ROM(
0x8086,
0x1026,
"e1000-82545gm-copper",
"Intel EtherExpressPro1000 82545GM Copper"),
1N/APCI_ROM(
0x8086,
0x1027,
"e1000-82545gm-fiber",
"Intel EtherExpressPro1000 82545GM Fiber"),
1N/APCI_ROM(
0x8086,
0x1028,
"e1000-82545gm-serdes",
"Intel EtherExpressPro1000 82545GM SERDES"),
1N/APCI_ROM(
0x8086,
0x1075,
"e1000-82547gi",
"Intel EtherExpressPro1000 82547GI"),
1N/APCI_ROM(
0x8086,
0x1076,
"e1000-82541gi",
"Intel EtherExpressPro1000 82541GI"),
1N/APCI_ROM(
0x8086,
0x1077,
"e1000-82541gi-mobile",
"Intel EtherExpressPro1000 82541GI Mobile"),
1N/APCI_ROM(
0x8086,
0x1078,
"e1000-82541er",
"Intel EtherExpressPro1000 82541ER"),
1N/APCI_ROM(
0x8086,
0x1079,
"e1000-82546gb-copper",
"Intel EtherExpressPro1000 82546GB Copper"),
1N/APCI_ROM(
0x8086,
0x107a,
"e1000-82546gb-fiber",
"Intel EtherExpressPro1000 82546GB Fiber"),
1N/APCI_ROM(
0x8086,
0x107b,
"e1000-82546gb-serdes",
"Intel EtherExpressPro1000 82546GB SERDES"),