/**************************************************************************
Inter Pro 1000 for Etherboot
Drivers are port from Intel's Linux driver e1000-4.3.15
***************************************************************************/
/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/*
* Copyright (C) Archway Digital Solutions.
*
* written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
* 2/9/2002
*
* Copyright (C) Linux Networx.
* Massive upgrade to work with the new intel gigabit NICs.
* <ebiederman at lnxi dot com>
*
* Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
* Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
*
* 01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
*/
/* to get some global routines like printf */
#include "etherboot.h"
/* to get the interface to the body of the program */
#include "nic.h"
/* to get the PCI support functions, if this is a PCI NIC */
#include "pci.h"
#include "timer.h"
typedef unsigned char *dma_addr_t;
typedef enum {
FALSE = 0,
} boolean_t;
#define DEBUG 0
/* Some pieces of code are disabled with #if 0 ... #endif.
* They are not deleted to show where the etherboot driver differs
* from the linux driver below the function level.
* Some member variables of the hw struct have been eliminated
* and the corresponding inplace checks inserted instead.
* Pieces such as LED handling that we definitely don't need are deleted.
*
* The following defines should not be needed normally,
* but may be helpful for debugging purposes. */
/* Define this if you want to program the transmission control register
* the way the Linux driver does it. */
/* Define this to behave more like the Linux driver. */
#include "e1000_hw.h"
/* NIC specific static variables go here */
static int tx_tail;
/* Function forward declarations */
/* Printing macros... */
#if DEBUG >= 3
#else
#endif
#if DEBUG >= 2
#else
#define DEBUGFUNC(F)
#endif
#if DEBUG >= 1
#else
#define DEBUGOUT(S)
#define DEBUGOUT1(S,A)
#define DEBUGOUT2(S,A,B)
#define DEBUGOUT3(S,A,B,C)
#define DEBUGOUT7(S,A,B,C,D,E,F,G)
#endif
((a)->mac_type >= e1000_82543) ? \
((a)->mac_type >= e1000_82543) ? \
((a)->mac_type >= e1000_82543) ? \
((a)->mac_type >= e1000_82543) ? \
{
}
void
{
}
{
}
{
}
/******************************************************************************
* Raises the EEPROM's clock input.
*
* hw - Struct containing variables accessed by shared code
* eecd - EECD's current value
*****************************************************************************/
static void
{
/* Raise the clock input to the EEPROM (by setting the SK bit), and then
* wait <delay> microseconds.
*/
}
/******************************************************************************
* Lowers the EEPROM's clock input.
*
* hw - Struct containing variables accessed by shared code
* eecd - EECD's current value
*****************************************************************************/
static void
{
/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
* wait 50 microseconds.
*/
}
/******************************************************************************
* Shift data bits out to the EEPROM.
*
* hw - Struct containing variables accessed by shared code
* data - data to send to the EEPROM
* count - number of bits to shift out
*****************************************************************************/
static void
{
/* We need to shift "count" bits out to the EEPROM. So, value in the
* "data" parameter will be shifted out to the EEPROM one bit at a time.
* In order to do this, "data" must be broken down into bits.
*/
eecd &= ~E1000_EECD_DO;
eecd |= E1000_EECD_DO;
}
do {
/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
* and then raising and then lowering the clock (the SK bit controls
* the clock input to the EEPROM). A "0" is shifted out to the EEPROM
* by setting "DI" to "0" and then raising and then lowering the clock.
*/
eecd &= ~E1000_EECD_DI;
eecd |= E1000_EECD_DI;
} while(mask);
/* We leave the "DI" bit set to "0" when we leave this routine. */
eecd &= ~E1000_EECD_DI;
}
/******************************************************************************
* Shift data bits in from the EEPROM
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static uint16_t
{
uint32_t i;
/* In order to read a register from the EEPROM, we need to shift 'count'
* bits in from the EEPROM. Bits are "shifted in" by raising the clock
* input to the EEPROM (setting the SK bit), and then reading the value of
* the "DO" bit. During this "shifting in" process the "DI" bit should
* always be clear.
*/
data = 0;
for(i = 0; i < count; i++) {
eecd &= ~(E1000_EECD_DI);
if(eecd & E1000_EECD_DO)
data |= 1;
}
return data;
}
/******************************************************************************
* Prepares EEPROM for access
*
* hw - Struct containing variables accessed by shared code
*
* Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
* function should be called before issuing a command to the EEPROM.
*****************************************************************************/
static int32_t
{
/* Request EEPROM Access */
eecd |= E1000_EECD_REQ;
while((!(eecd & E1000_EECD_GNT)) &&
(i < E1000_EEPROM_GRANT_ATTEMPTS)) {
i++;
udelay(5);
}
if(!(eecd & E1000_EECD_GNT)) {
eecd &= ~E1000_EECD_REQ;
DEBUGOUT("Could not acquire EEPROM grant\n");
return -E1000_ERR_EEPROM;
}
}
/* Clear SK and DI */
/* Set CS */
eecd |= E1000_EECD_CS;
/* Clear SK and CS */
udelay(1);
}
return E1000_SUCCESS;
}
/******************************************************************************
* Returns EEPROM to a "standby" state
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
{
/* Deselect EEPROM */
/* Clock high */
eecd |= E1000_EECD_SK;
/* Select EEPROM */
eecd |= E1000_EECD_CS;
/* Clock low */
eecd &= ~E1000_EECD_SK;
/* Toggle CS to flush commands */
eecd |= E1000_EECD_CS;
eecd &= ~E1000_EECD_CS;
}
}
/******************************************************************************
* Terminates a command by inverting the EEPROM's chip select pin
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
{
/* cleanup eeprom */
/* CS on Microwire is active-high */
/* Rising edge of clock */
eecd |= E1000_EECD_SK;
/* Falling edge of clock */
eecd &= ~E1000_EECD_SK;
}
/* Stop requesting EEPROM access */
eecd &= ~E1000_EECD_REQ;
}
}
/******************************************************************************
* Reads a 16 bit word from the EEPROM.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static int32_t
{
/* Read "Status Register" repeatedly until the LSB is cleared. The
* EEPROM will signal that the command has been completed by clearing
* bit 0 of the internal status register. If it's not cleared within
* 5 milliseconds, then error out.
*/
retry_count = 0;
do {
if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
break;
udelay(5);
retry_count += 5;
} while(retry_count < EEPROM_MAX_RETRY_SPI);
/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
* only 0-5mSec on 5V devices)
*/
if(retry_count >= EEPROM_MAX_RETRY_SPI) {
DEBUGOUT("SPI EEPROM Status error\n");
return -E1000_ERR_EEPROM;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Reads a 16 bit word from the EEPROM.
*
* hw - Struct containing variables accessed by shared code
* offset - offset of word in the EEPROM to read
* data - word read from the EEPROM
* words - number of words to read
*****************************************************************************/
static int
{
uint32_t i = 0;
DEBUGFUNC("e1000_read_eeprom");
/* A check for invalid values: offset too large, too many words, and not
* enough words.
*/
(words == 0)) {
DEBUGOUT("\"words\" parameter out of bounds\n");
return -E1000_ERR_EEPROM;
}
/* Prepare the EEPROM for reading */
return -E1000_ERR_EEPROM;
if(e1000_spi_eeprom_ready(hw)) {
return -E1000_ERR_EEPROM;
}
/* Some SPI eeproms use the 8th address bit embedded in the opcode */
/* Send the READ command (opcode + addr) */
/* Read the data. The address of the eeprom internally increments with
* each byte (spi) being read, saving on the overhead of eeprom setup
* and tear-down. The address counter will roll over if reading beyond
* the size of the eeprom, thus allowing the entire memory to be read
* starting from any offset. */
for (i = 0; i < words; i++) {
}
for (i = 0; i < words; i++) {
/* Send the READ command (opcode + addr) */
/* Read the data. For microwire, each word requires the overhead
* of eeprom setup and tear-down. */
}
}
/* End this read operation */
return E1000_SUCCESS;
}
/******************************************************************************
* Verifies that the EEPROM has a valid checksum
*
* hw - Struct containing variables accessed by shared code
*
* Reads the first 64 16 bit words of the EEPROM and sums the values read.
* If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
* valid.
*****************************************************************************/
static int
{
DEBUGFUNC("e1000_validate_eeprom_checksum");
for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
checksum += eeprom_data;
}
return E1000_SUCCESS;
else {
DEBUGOUT("EEPROM Checksum Invalid\n");
return -E1000_ERR_EEPROM;
}
}
/******************************************************************************
* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
* second function of dual function devices
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static int
{
int i;
DEBUGFUNC("e1000_read_mac_addr");
for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
offset = i >> 1;
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
}
/* Invert the last bit if this is the second device */
return E1000_SUCCESS;
}
/******************************************************************************
* Initializes receive address filters.
*
* hw - Struct containing variables accessed by shared code
*
* Places the MAC address in receive address register 0 and clears the rest
* of the receive addresss registers. Clears the multicast table. Assumes
* the receiver is in reset when the routine is called.
*****************************************************************************/
static void
{
uint32_t i;
DEBUGFUNC("e1000_init_rx_addrs");
/* Setup the receive address. */
DEBUGOUT("Programming MAC Address into RAR[0]\n");
/* Zero out the other 15 receive addresses. */
DEBUGOUT("Clearing RAR[1-15]\n");
for(i = 1; i < E1000_RAR_ENTRIES; i++) {
}
}
/******************************************************************************
* Clears the VLAN filer table
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
{
}
/******************************************************************************
* Writes a value to one of the devices registers using port I/O (as opposed to
* memory mapped I/O). Only 82544 and newer devices support port I/O. *
* hw - Struct containing variables accessed by shared code
* offset - offset to write to * value - value to write
*****************************************************************************/
}
/******************************************************************************
* Set the phy type member in the hw struct.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static int32_t
{
DEBUGFUNC("e1000_set_phy_type");
case M88E1000_E_PHY_ID:
case M88E1000_I_PHY_ID:
case M88E1011_I_PHY_ID:
break;
case IGP01E1000_I_PHY_ID:
break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_PHY_TYPE;
}
return E1000_SUCCESS;
}
/******************************************************************************
* IGP phy init script - initializes the GbE PHY
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
{
DEBUGFUNC("e1000_phy_init_script");
#if 0
/* See e1000_sw_init() of the Linux driver */
if(hw->phy_init_script) {
#else
#endif
mdelay(20);
mdelay(5);
} else {
}
/* Move to analog registers page */
if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
} else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
}
}
}
}
/******************************************************************************
* Set the mac type member in the hw struct.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static int
{
DEBUGFUNC("e1000_set_mac_type");
case E1000_DEV_ID_82542:
switch (hw->revision_id) {
case E1000_82542_2_0_REV_ID:
break;
case E1000_82542_2_1_REV_ID:
break;
default:
/* Invalid 82542 revision ID */
return -E1000_ERR_MAC_TYPE;
}
break;
break;
case E1000_DEV_ID_82544GC_LOM:
break;
case E1000_DEV_ID_82540EM:
case E1000_DEV_ID_82540EM_LOM:
case E1000_DEV_ID_82540EP:
case E1000_DEV_ID_82540EP_LOM:
case E1000_DEV_ID_82540EP_LP:
break;
break;
break;
break;
break;
case E1000_DEV_ID_82541EI:
break;
case E1000_DEV_ID_82541ER:
case E1000_DEV_ID_82541GI:
break;
case E1000_DEV_ID_82547EI:
break;
case E1000_DEV_ID_82547GI:
break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
}
return E1000_SUCCESS;
}
/*****************************************************************************
* Set media type and TBI compatibility.
*
* hw - Struct containing variables accessed by shared code
* **************************************************************************/
static void
{
DEBUGFUNC("e1000_set_media_type");
/* tbi_compatibility is only valid on 82543 */
}
break;
default:
if(status & E1000_STATUS_TBIMODE) {
/* tbi_compatibility not valid on fiber */
} else {
}
} else {
/* This is an 82542 (fiber only) */
}
}
}
/******************************************************************************
* Reset the transmit and receive units; mask and clear all interrupts.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
{
DEBUGFUNC("e1000_reset_hw");
/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
}
/* Clear interrupt mask to stop board from generating interrupts */
DEBUGOUT("Masking off all interrupts\n");
/* Disable the Transmit and Receive units. Then delay to allow
* any pending transactions to complete before we hit the MAC with
* the global reset.
*/
/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
/* Delay to allow any outstanding PCI transactions to complete before
* resetting the device
*/
mdelay(10);
/* Must reset the PHY before resetting the MAC */
mdelay(5);
}
/* Issue a global reset to the MAC. This will reset the chip's
* transmit, receive, DMA, and link units. It will not effect
* the current PCI configuration. The global reset bit is self-
* clearing, and should clear within a microsecond.
*/
DEBUGOUT("Issuing a global reset to MAC\n");
case e1000_82544:
case e1000_82540:
case e1000_82545:
case e1000_82546:
case e1000_82541:
case e1000_82541_rev_2:
/* These controllers can't ack the 64-bit write when issuing the
* reset, so use IO-mapping as a workaround to issue the reset */
break;
case e1000_82545_rev_3:
case e1000_82546_rev_3:
/* Reset is performed on a shadow of the control register */
break;
default:
break;
}
/* After MAC reset, force reload of EEPROM to restore power-on settings to
* device. Later controllers reload the EEPROM automatically, so just wait
* for reload to complete.
*/
case e1000_82542_rev2_0:
case e1000_82542_rev2_1:
case e1000_82543:
case e1000_82544:
/* Wait for reset to complete */
udelay(10);
/* Wait for EEPROM reload */
mdelay(2);
break;
case e1000_82541:
case e1000_82541_rev_2:
case e1000_82547:
case e1000_82547_rev_2:
/* Wait for EEPROM reload */
mdelay(20);
break;
default:
/* Wait for EEPROM reload (it happens automatically) */
mdelay(5);
break;
}
/* Disable HW ARPs on ASF enabled adapters */
manc &= ~(E1000_MANC_ARP_EN);
}
}
/* Clear interrupt mask to stop board from generating interrupts */
DEBUGOUT("Masking off all interrupts\n");
/* Clear any pending interrupt events. */
/* If MWI was previously enabled, reenable it. */
#ifdef LINUX_DRIVER
#endif
}
}
/******************************************************************************
* Performs basic configuration of the adapter.
*
* hw - Struct containing variables accessed by shared code
*
* Assumes that the controller has previously been reset and is in a
* post-reset uninitialized state. Initializes the receive address registers,
* multicast table, and VLAN filter table. Calls routines to setup link
* configuration and flow control settings. Clears all on-chip counters. Leaves
* the transmit and receive units disabled and uninitialized.
*****************************************************************************/
static int
{
uint32_t i;
DEBUGFUNC("e1000_init_hw");
/* Set the media type and TBI compatibility */
/* Disabling VLAN filtering. */
DEBUGOUT("Initializing the IEEE VLAN\n");
/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
mdelay(5);
}
/* Setup the receive address. This involves initializing all of the Receive
* Address Registers (RARs 0 - 15).
*/
/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
mdelay(1);
#ifdef LINUX_DRIVER
#endif
}
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
for(i = 0; i < E1000_MC_TBL_SIZE; i++)
#if 0
/* Set the PCI priority bit correctly in the CTRL register. This
* determines if the adapter gives priority to receives, or if it
* gives equal priority to transmits and receives.
*/
if(hw->dma_fairness) {
}
#endif
case e1000_82545_rev_3:
case e1000_82546_rev_3:
break;
default:
/* See e1000_get_bus_info() of the Linux driver */
}
/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
if(bus_type == e1000_bus_type_pcix) {
if(cmd_mmrbc > stat_mmrbc) {
}
}
break;
}
/* Call a subroutine to configure the link and setup flow control. */
/* Set the transmit descriptor write-back policy */
}
#if 0
/* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
*/
#endif
return ret_val;
}
/******************************************************************************
* Adjust SERDES output amplitude based on EEPROM setting.
*
* hw - Struct containing variables accessed by shared code.
*****************************************************************************/
static int32_t
{
DEBUGFUNC("e1000_adjust_serdes_amplitude");
return E1000_SUCCESS;
case e1000_82545_rev_3:
case e1000_82546_rev_3:
break;
default:
return E1000_SUCCESS;
}
&eeprom_data))) {
return ret_val;
}
if(eeprom_data != EEPROM_RESERVED_WORD) {
/* Adjust SERDES output amplitude only. */
eeprom_data)))
return ret_val;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Configures flow control and link settings.
*
* hw - Struct containing variables accessed by shared code
*
* Determines which flow control settings to use. Calls the apropriate media-
* specific link configuration function. Configures the flow control settings.
* Assuming the adapter has a valid link partner, a valid link should be
* established. Assumes the hardware has previously been reset and the
* transmitter and receiver are not enabled.
*****************************************************************************/
static int
{
DEBUGFUNC("e1000_setup_link");
/* Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
* a bit that determines whether the HW defaults to enabling or
* disabling auto-negotiation, and the direction of the
* SW defined pins. If there is no SW over-ride of the flow
* control setting, then the variable hw->fc will
* be initialized based on a value in the EEPROM.
*/
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
else
}
/* We want to save off the original Flow Control configuration just
* in case we get disconnected and then reconnected into a different
* hub or switch with different Flow Control capabilities.
*/
#if 0
/* See e1000_sw_init() of the Linux driver */
#else
#endif
#if 0
#endif
/* Take the 4 bits from EEPROM word 0x0F that determine the initial
* polarity value for the SW controlled pins, and setup the
* Extended Device Control reg with that info.
* This is needed because one of the SW controlled pins is used for
* signal detection. So this should be done before e1000_setup_pcs_link()
* or e1000_phy_setup() is called.
*/
}
/* Call the necessary subroutine to configure the link. */
if (ret_val < 0) {
return ret_val;
}
/* Initialize the flow control address, type, and PAUSE timer
* registers to their default values. This is done even if flow
* control is disabled, because it does not hurt anything to
* initialize these registers.
*/
DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
#if 0
#else
#endif
/* Set the flow control receive threshold registers. Normally,
* these registers will be set to a default threshold that may be
* adjusted later by the driver's runtime code. However, if the
* ability to transmit pause frames in not enabled, then these
* registers will be set to 0.
*/
} else {
/* We need to set up the Receive Threshold high and low water marks
* as well as (optionally) enabling the transmission of XON frames.
*/
#if 0
if(hw->fc_send_xon) {
} else {
}
#else
#endif
}
return ret_val;
}
/******************************************************************************
* Sets up link for a fiber based or serdes based adapter
*
* hw - Struct containing variables accessed by shared code
*
* Manipulates Physical Coding Sublayer functions in order to configure
* link. Assumes the hardware has been previously reset and the transmitter
* and receiver are not enabled.
*****************************************************************************/
static int
{
uint32_t i;
DEBUGFUNC("e1000_setup_fiber_serdes_link");
/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
* cleared when there is a signal. This applies to fiber media only.
* If we're on serdes media, adjust the output amplitude to value set in
* the EEPROM.
*/
return ret_val;
/* Take the link out of reset */
ctrl &= ~(E1000_CTRL_LRST);
#if 0
/* Adjust VCO speed to improve BER performance */
return ret_val;
#endif
/* Check for a software override of the flow control settings, and setup
* the device accordingly. If auto-negotiation is enabled, then software
* will have to set the "PAUSE" bits to the correct value in the Tranmsit
* Config Word Register (TXCW) and re-start auto-negotiation. However, if
* auto-negotiation is disabled, then software will have to manually
* configure the two flow control enable bits in the CTRL register.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames, but
* not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but we do
* not support receiving pause frames).
* 3: Both Rx and TX flow control (symmetric) are enabled.
*/
case e1000_fc_none:
/* Flow control is completely disabled by a software over-ride. */
break;
case e1000_fc_rx_pause:
/* RX Flow control is enabled and TX Flow control is disabled by a
* software over-ride. Since there really isn't a way to advertise
* that we are capable of RX Pause ONLY, we will advertise that we
* support both symmetric and asymmetric RX PAUSE. Later, we will
* disable the adapter's ability to send PAUSE frames.
*/
break;
case e1000_fc_tx_pause:
/* TX Flow control is enabled, and RX Flow control is disabled, by a
* software over-ride.
*/
break;
case e1000_fc_full:
/* Flow control (both RX and TX) is enabled by a software over-ride. */
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
return -E1000_ERR_CONFIG;
break;
}
/* Since auto-negotiation is enabled, take the link out of reset (the link
* will be in reset, because we previously reset the chip). This will
* restart auto-negotiation. If auto-neogtiation is successful then the
* link-up status bit will be set and the flow control enable bits (RFCE
* and TFCE) will be set according to their negotiated value.
*/
DEBUGOUT("Auto-negotiation enabled\n");
mdelay(1);
/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
* indication in the Device Status Register. Time-out if a link isn't
* seen in 500 milliseconds seconds (Auto-negotiation should complete in
* less than 500 milliseconds even if the other end is doing it in SW).
* For internal serdes, we just assume a signal is present, then poll.
*/
DEBUGOUT("Looking for Link\n");
for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
mdelay(10);
if(status & E1000_STATUS_LU) break;
}
if(i == (LINK_UP_TIMEOUT / 10)) {
DEBUGOUT("Never got a valid link from auto-neg!!!\n");
/* AutoNeg failed to achieve a link, so we'll call
* e1000_check_for_link. This routine will force the link up if
* we detect a signal. This will allow us to communicate with
* non-autonegotiating link partners.
*/
DEBUGOUT("Error while checking for link\n");
return ret_val;
}
hw->autoneg_failed = 0;
} else {
hw->autoneg_failed = 0;
DEBUGOUT("Valid Link Found\n");
}
} else {
DEBUGOUT("No Signal Detected\n");
}
return E1000_SUCCESS;
}
/******************************************************************************
* Detects which PHY is present and the speed and duplex
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int
{
uint16_t i;
DEBUGFUNC("e1000_setup_copper_link");
/* With 82543, we need to force speed and duplex on the MAC equal to what
* the PHY speed and duplex configuration is. In addition, we need to
* perform a hardware reset on the PHY to take it out of reset.
*/
ctrl |= E1000_CTRL_SLU;
} else {
}
/* Make sure we have a valid PHY */
DEBUGOUT("Error, did not detect valid phy.\n");
return ret_val;
}
#if 0
if(!hw->phy_reset_disable) {
#else
#endif
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
}
/* Wait 10ms for MAC to configure PHY from eeprom settings */
mdelay(15);
#if 0
/* disable lplu d3 during driver init */
DEBUGOUT("Error Disabling LPLU D3\n");
return ret_val;
}
/* Configure mdi-mdix settings */
&phy_data)))
return ret_val;
/* Force MDI for IGP B-0 PHY */
} else {
case 1:
break;
case 2:
break;
case 0:
default:
break;
}
}
phy_data)))
return ret_val;
/* set auto-master slave resolution settings */
#endif
/* when autonegotiation advertisment is only 1000Mbps then we
* should disable SmartSpeed and enable Auto MasterSlave
* resolution as hardware default. */
/* Disable SmartSpeed */
&phy_data)))
return ret_val;
phy_data)))
return ret_val;
&phy_data)))
return ret_val;
phy_data)))
return ret_val;
}
&phy_data)))
return ret_val;
#if 0
/* load defaults for future use */
((phy_data & CR_1000T_MS_VALUE) ?
switch (phy_ms_setting) {
case e1000_ms_force_master:
break;
case e1000_ms_force_slave:
phy_data &= ~(CR_1000T_MS_VALUE);
break;
case e1000_ms_auto:
default:
break;
}
#endif
phy_data)))
return ret_val;
} else {
/* Enable CRS on TX. This must be set for half-duplex operation. */
&phy_data)))
return ret_val;
/* Options:
* 0 - Auto for all speeds
* 1 - MDI mode
* 2 - MDI-X mode
* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
*/
#if 0
case 1:
break;
case 2:
break;
case 3:
break;
case 0:
default:
#endif
#if 0
break;
}
#endif
/* Options:
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
* 1 - Enabled
*/
phy_data)))
return ret_val;
/* Force TX_CLK in the Extended PHY Specific Control Register
* to 25MHz clock.
*/
&phy_data)))
return ret_val;
#ifdef LINUX_DRIVER
#endif
/* Configure Master and Slave downshift values */
phy_data)))
return ret_val;
}
/* SW Reset the PHY so all changes take effect */
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
#ifdef LINUX_DRIVER
}
#endif
}
/* Options:
* autoneg = 1 (default)
* PHY will advertise value(s) parsed from
* autoneg_advertised and fc
* autoneg = 0
* PHY will be set to 10H, 10F, 100H, or 100F
* depending on value parsed from forced_speed_duplex.
*/
/* Is autoneg enabled? This is enabled by default or by software
* override. If so, call e1000_phy_setup_autoneg routine to parse the
* autoneg_advertised and fc options. If autoneg is NOT enabled, then
* call e1000_phy_force_speed_duplex to parse and set this up.
*/
/* Perform some bounds checking on the hw->autoneg_advertised
* parameter. If this variable is zero, then set it to the default.
*/
/* If autoneg_advertised is zero, we assume it was not defaulted
* by the calling code so we set to advertise full capability.
*/
if(hw->autoneg_advertised == 0)
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
DEBUGOUT("Error Setting up Auto-Negotiation\n");
return ret_val;
}
DEBUGOUT("Restarting Auto-Neg\n");
/* Restart auto-negotiation by setting the Auto Neg Enable bit and
* the Auto Neg Restart bit in the PHY control register.
*/
return ret_val;
return ret_val;
#if 0
/* Does the user want to wait for Auto-Neg to complete here, or
* check at a later time (for example, callback routine).
*/
if(hw->wait_autoneg_complete) {
DEBUGOUT("Error while waiting for autoneg to complete\n");
return ret_val;
}
}
#else
/* If we do not wait for autonegotiation to complete I
* do not see a valid link status.
*/
DEBUGOUT("Error while waiting for autoneg to complete\n");
return ret_val;
}
#endif
} /* !hw->phy_reset_disable */
/* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
for(i = 0; i < 10; i++) {
return ret_val;
return ret_val;
if(phy_data & MII_SR_LINK_STATUS) {
/* We have link, so we need to finish the config process:
* if we are on 82543. If we
* are on newer silicon, we only need to configure
* collision distance in the Transmit Control Register.
* 2) Set up flow control on the MAC to that established with
* the link partner.
*/
} else {
DEBUGOUT("Error configuring MAC to PHY settings\n");
return ret_val;
}
}
DEBUGOUT("Error Configuring Flow Control\n");
return ret_val;
}
#if 0
DEBUGOUT("Error Configuring DSP after link up\n");
return ret_val;
}
}
#endif
DEBUGOUT("Valid link established!!!\n");
return E1000_SUCCESS;
}
udelay(10);
}
DEBUGOUT("Unable to establish link!!!\n");
return -E1000_ERR_NOLINK;
}
/******************************************************************************
* Configures PHY autoneg and flow control advertisement settings
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int
{
DEBUGFUNC("e1000_phy_setup_autoneg");
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
return ret_val;
/* Read the MII 1000Base-T Control Register (Address 9). */
return ret_val;
/* Need to parse both autoneg_advertised and fc and set up
* the appropriate PHY registers. First we will parse for
* autoneg_advertised software override. Since we can advertise
* a plethora of combinations, we need to check each bit
* individually.
*/
/* First we clear all the 10/100 mb speed bits in the Auto-Neg
* Advertisement Register (Address 4) and the 1000 mb speed bits in
* the 1000Base-T Control Register (Address 9).
*/
/* Do we want to advertise 10 Mb Half Duplex? */
DEBUGOUT("Advertise 10mb Half duplex\n");
}
/* Do we want to advertise 10 Mb Full Duplex? */
DEBUGOUT("Advertise 10mb Full duplex\n");
}
/* Do we want to advertise 100 Mb Half Duplex? */
DEBUGOUT("Advertise 100mb Half duplex\n");
}
/* Do we want to advertise 100 Mb Full Duplex? */
DEBUGOUT("Advertise 100mb Full duplex\n");
}
/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
}
/* Do we want to advertise 1000 Mb Full Duplex? */
DEBUGOUT("Advertise 1000mb Full duplex\n");
}
/* Check for a software override of the flow control settings, and
* setup the PHY advertisement registers accordingly. If
* auto-negotiation is enabled, then software will have to set the
* "PAUSE" bits to the correct value in the Auto-Negotiation
* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* but we do not support receiving pause frames).
* 3: Both Rx and TX flow control (symmetric) are enabled.
* other: No software override. The flow control configuration
* in the EEPROM is used.
*/
case e1000_fc_none: /* 0 */
/* Flow control (RX & TX) is completely disabled by a
* software over-ride.
*/
break;
case e1000_fc_rx_pause: /* 1 */
/* RX Flow control is enabled, and TX Flow control is
* disabled, by a software over-ride.
*/
/* Since there really isn't a way to advertise that we are
* capable of RX Pause ONLY, we will advertise that we
* support both symmetric and asymmetric RX PAUSE. Later
* (in e1000_config_fc_after_link_up) we will disable the
*hw's ability to send PAUSE frames.
*/
break;
case e1000_fc_tx_pause: /* 2 */
/* TX Flow control is enabled, and RX Flow control is
* disabled, by a software over-ride.
*/
break;
case e1000_fc_full: /* 3 */
/* Flow control (both RX and TX) is enabled by a software
* over-ride.
*/
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
return -E1000_ERR_CONFIG;
}
return ret_val;
return ret_val;
return E1000_SUCCESS;
}
/******************************************************************************
* Sets the collision distance in the Transmit Control register
*
* hw - Struct containing variables accessed by shared code
*
* Link should have been established previously. Reads the speed and duplex
* information from the Device Status register.
******************************************************************************/
static void
{
tctl &= ~E1000_TCTL_COLD;
}
/******************************************************************************
* Sets MAC speed and duplex settings to reflect the those in the PHY
*
* hw - Struct containing variables accessed by shared code
* mii_reg - data to write to the MII control register
*
* The contents of the PHY register containing the needed information need to
* be passed in.
******************************************************************************/
static int
{
DEBUGFUNC("e1000_config_mac_to_phy");
/* Read the Device Control Register and set the bits to Force Speed
* and Duplex.
*/
/* Set up duplex in the Device Control and Transmit Control
* registers depending on negotiated values.
*/
&phy_data)))
return ret_val;
else ctrl &= ~E1000_CTRL_FD;
/* Set up speed in the Device Control register depending on
* negotiated values.
*/
if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
} else {
&phy_data)))
return ret_val;
else ctrl &= ~E1000_CTRL_FD;
/* Set up speed in the Device Control register depending on
* negotiated values.
*/
}
/* Write the configured values back to the Device Control Reg. */
return E1000_SUCCESS;
}
/******************************************************************************
* Forces the MAC's flow control settings.
*
* hw - Struct containing variables accessed by shared code
*
* Sets the TFCE and RFCE bits in the device control register to reflect
* the adapter settings. TFCE and RFCE need to be explicitly set by
* software when a Copper PHY is used because autonegotiation is managed
* by the PHY rather than the MAC. Software must also configure these
* bits when link is forced on a fiber connection.
*****************************************************************************/
static int
{
DEBUGFUNC("e1000_force_mac_fc");
/* Get the current configuration of the Device Control Register */
/* Because we didn't get link via the internal auto-negotiation
* mechanism (we either forced link or we got link via PHY
* receive flow control.
*
* according to the "hw->fc" parameter.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause
* frames but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* frames but we do not receive pause frames).
* 3: Both Rx and TX flow control (symmetric) is enabled.
* other: No other values should be possible at this point.
*/
case e1000_fc_none:
break;
case e1000_fc_rx_pause:
ctrl &= (~E1000_CTRL_TFCE);
ctrl |= E1000_CTRL_RFCE;
break;
case e1000_fc_tx_pause:
ctrl &= (~E1000_CTRL_RFCE);
ctrl |= E1000_CTRL_TFCE;
break;
case e1000_fc_full:
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
return -E1000_ERR_CONFIG;
}
/* Disable TX Flow Control for 82542 (rev 2.0) */
ctrl &= (~E1000_CTRL_TFCE);
return E1000_SUCCESS;
}
/******************************************************************************
* Configures flow control settings after link is established
*
* hw - Struct containing variables accessed by shared code
*
* Should be called immediately after a valid link has been established.
* and autonegotiation is enabled, the MAC flow control settings will be set
* based on the flow control negotiated by the PHY. In TBI mode, the TFCE
* and RFCE bits will be automaticaly set to the negotiated flow control mode.
*****************************************************************************/
static int
{
DEBUGFUNC("e1000_config_fc_after_link_up");
/* Check for the case where we have fiber media and auto-neg failed
* so we had to force link. In this case, we need to force the
* configuration of the MAC to match the "fc" parameter.
*/
DEBUGOUT("Error forcing flow control settings\n");
return ret_val;
}
}
/* Check for the case where we have copper media and auto-neg is
* enabled. In this case, we need to check and see if Auto-Neg
* has completed, and if so, how the PHY and link partner has
* flow control configured.
*/
/* Read the MII Status Register and check to see if AutoNeg
* has completed. We read this twice because this reg has
* some "sticky" (latched) bits.
*/
return ret_val;
return ret_val;
/* The AutoNeg process has completed, so we now need to
* read both the Auto Negotiation Advertisement Register
* (Address 4) and the Auto_Negotiation Base Page Ability
* Register (Address 5) to determine how flow control was
* negotiated.
*/
&mii_nway_adv_reg)))
return ret_val;
return ret_val;
/* Two bits in the Auto Negotiation Advertisement Register
* (Address 4) and two bits in the Auto Negotiation Base
* Page Ability Register (Address 5) determine flow control
* for both the PHY and the link partner. The following
* 1999, describes these PAUSE resolution bits and how flow
* control is determined based upon these settings.
* NOTE: DC = Don't Care
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
*-------|---------|-------|---------|--------------------
* 0 | 0 | DC | DC | e1000_fc_none
* 0 | 1 | 0 | DC | e1000_fc_none
* 0 | 1 | 1 | 0 | e1000_fc_none
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
* 1 | 0 | 0 | DC | e1000_fc_none
* 1 | DC | 1 | DC | e1000_fc_full
* 1 | 1 | 0 | 0 | e1000_fc_none
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
*
*/
/* Are both PAUSE bits set to 1? If so, this implies
* Symmetric Flow Control is enabled at both ends. The
* ASM_DIR bits are irrelevant per the spec.
*
* For Symmetric Flow Control:
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
*-------|---------|-------|---------|--------------------
* 1 | DC | 1 | DC | e1000_fc_full
*
*/
if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
/* Now we need to check if the user selected RX ONLY
* of pause frames. In this case, we had to advertise
* FULL flow control because we could not advertise RX
* ONLY. Hence, we must now check to see if we need to
* turn OFF the TRANSMISSION of PAUSE frames.
*/
#if 0
#else
#endif
DEBUGOUT("Flow Control = FULL.\r\n");
} else {
DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
}
}
/* For receiving PAUSE frames ONLY.
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
*-------|---------|-------|---------|--------------------
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
*
*/
else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
}
/* For transmitting PAUSE frames ONLY.
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
*-------|---------|-------|---------|--------------------
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
*
*/
else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
}
/* Per the IEEE spec, at this point flow control should be
* disabled. However, we want to consider that we could
* be connected to a legacy switch that doesn't advertise
* desired flow control, but can be forced on the link
* partner. So if we advertised no flow control, that is
* what we will resolve to. If we advertised some kind of
* receive capability (Rx Pause Only or Full Flow Control)
* and the link partner advertised none, we will configure
* ourselves to enable Rx Flow Control only. We can do
* this safely for two reasons: If the link partner really
* didn't want flow control enabled, and we enable Rx, no
* harm done since we won't be receiving any PAUSE frames
* anyway. If the intent on the link partner was to have
* flow control enabled, then by us enabling RX only, we
* can at least receive pause frames and process them.
* This is a good idea because in most cases, since we are
* predominantly a server NIC, more times than not we will
* be asked to delay transmission of packets than asking
* our link partner to pause transmission of frames.
*/
#if 0
#else
DEBUGOUT("Flow Control = NONE.\r\n");
#endif
DEBUGOUT("Flow Control = NONE.\r\n");
} else {
DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
}
/* Now we need to do one last check... If we auto-
* negotiated to HALF DUPLEX, flow control should not be
* enabled per IEEE 802.3 spec.
*/
if(duplex == HALF_DUPLEX)
/* Now we call a subroutine to actually force the MAC
* controller to use the correct flow control settings.
*/
DEBUGOUT("Error forcing flow control settings\n");
return ret_val;
}
} else {
DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
}
}
return E1000_SUCCESS;
}
/******************************************************************************
* Checks to see if the link status of the hardware has changed.
*
* hw - Struct containing variables accessed by shared code
*
* Called by any function that needs to check the link status of the adapter.
*****************************************************************************/
static int
{
DEBUGFUNC("e1000_check_for_link");
/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
* cleared when there is a signal. This applies to fiber media only.
*/
/* If we have a copper PHY then we only want to go out to the PHY
* status has changed. The get_link_status flag will be set if we
* receive a Link Status Change interrupt or we have Rx Sequence
* Errors.
*/
#if 0
#else
#endif
/* First we want to see if the MII Status Register reports
* of the PHY.
* Read the register twice since the link bit is sticky.
*/
return ret_val;
return ret_val;
if(phy_data & MII_SR_LINK_STATUS) {
#if 0
#endif
} else {
/* No link detected */
return -E1000_ERR_NOLINK;
}
/* We have a M88E1000 PHY and Auto-Neg is enabled. If we
* have Si on board that is 82544 or newer, Auto
* configuration. So we only need to configure Collision
* Distance in the MAC. Otherwise, we need to force
* settings.
*/
else {
DEBUGOUT("Error configuring MAC to PHY settings\n");
return ret_val;
}
}
/* Configure Flow Control now that Auto-Neg has completed. First, we
* need to restore the desired flow control settings because we may
* have had to re-autoneg with a different link partner.
*/
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
/* At this point we know that we are on copper and we have
* auto-negotiated link. These are conditions for checking the link
* parter capability register. We use the link partner capability to
* determine if TBI Compatibility needs to be turned on or off. If
* the link partner advertises any speed in addition to Gigabit, then
* we assume that they are GMII-based, and TBI compatibility is not
* needed. If no other speeds are advertised, we assume the link
* partner is TBI-based, and we turn on TBI Compatibility.
*/
if(hw->tbi_compatibility_en) {
&lp_capability)))
return ret_val;
if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
/* If our link partner advertises anything in addition to
* gigabit, we do not need to enable TBI compatibility.
*/
if(hw->tbi_compatibility_on) {
/* If we previously were in the mode, turn it off. */
rctl &= ~E1000_RCTL_SBP;
}
} else {
/* If TBI compatibility is was previously off, turn it on. For
* compatibility with a TBI link partner, we will store bad
* packets. Some frames have an additional byte on the end and
* will look like CRC errors to to the hardware.
*/
if(!hw->tbi_compatibility_on) {
rctl |= E1000_RCTL_SBP;
}
}
}
}
/* If we don't have link (auto-negotiation failed or link partner cannot
* auto-negotiate), the cable is plugged in (we have signal), and our
* link partner is not trying to auto-negotiate with us (we are receiving
* idles or data), we need to force link up. We also need to give
* auto-negotiation time to complete, in case the cable was just plugged
* in. The autoneg_failed flag does this.
*/
(!(status & E1000_STATUS_LU)) &&
(!(rxcw & E1000_RXCW_C))) {
if(hw->autoneg_failed == 0) {
return 0;
}
DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
/* Disable auto-negotiation in the TXCW register */
/* Force link-up and also force full-duplex. */
/* Configure Flow Control after forcing link up. */
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
}
/* If we are forcing link and we are receiving /C/ ordered sets, re-enable
* auto-negotiation in the TXCW register and disable forced link in the
* Device Control register in an attempt to auto-negotiate with our link
* partner.
*/
(ctrl & E1000_CTRL_SLU) &&
(rxcw & E1000_RXCW_C)) {
DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
}
#if 0
/* If we force link for non-auto-negotiation switch, check link status
* based on MAC synchronization for internal serdes media type.
*/
/* SYNCH bit and IV bit are sticky. */
udelay(10);
if(!(rxcw & E1000_RXCW_IV)) {
DEBUGOUT("SERDES: Link is up.\n");
}
} else {
DEBUGOUT("SERDES: Link is down.\n");
}
}
#endif
return E1000_SUCCESS;
}
/******************************************************************************
* Detects the current speed and duplex settings of the hardware.
*
* hw - Struct containing variables accessed by shared code
* speed - Speed of the connection
* duplex - Duplex setting of the connection
*****************************************************************************/
static void
{
DEBUGFUNC("e1000_get_speed_and_duplex");
if(status & E1000_STATUS_SPEED_1000) {
*speed = SPEED_1000;
DEBUGOUT("1000 Mbs, ");
} else if(status & E1000_STATUS_SPEED_100) {
DEBUGOUT("100 Mbs, ");
} else {
DEBUGOUT("10 Mbs, ");
}
if(status & E1000_STATUS_FD) {
*duplex = FULL_DUPLEX;
DEBUGOUT("Full Duplex\r\n");
} else {
*duplex = HALF_DUPLEX;
DEBUGOUT(" Half Duplex\r\n");
}
} else {
DEBUGOUT("1000 Mbs, Full Duplex\r\n");
*speed = SPEED_1000;
*duplex = FULL_DUPLEX;
}
}
/******************************************************************************
* Blocks until autoneg completes or times out (~4.5 seconds)
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int
{
uint16_t i;
DEBUGFUNC("e1000_wait_autoneg");
DEBUGOUT("Waiting for Auto-Neg to complete.\n");
/* We will wait for autoneg to complete or 4.5 seconds to expire. */
for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
/* Read the MII Status Register and wait for Auto-Neg
* Complete bit to be set.
*/
return ret_val;
return ret_val;
if(phy_data & MII_SR_AUTONEG_COMPLETE) {
DEBUGOUT("Auto-Neg complete.\n");
return E1000_SUCCESS;
}
mdelay(100);
}
DEBUGOUT("Auto-Neg timedout.\n");
return -E1000_ERR_TIMEOUT;
}
/******************************************************************************
* Raises the Management Data Clock
*
* hw - Struct containing variables accessed by shared code
* ctrl - Device control register's current value
******************************************************************************/
static void
{
/* Raise the clock input to the Management Data Clock (by setting the MDC
* bit), and then delay 10 microseconds.
*/
udelay(10);
}
/******************************************************************************
* Lowers the Management Data Clock
*
* hw - Struct containing variables accessed by shared code
* ctrl - Device control register's current value
******************************************************************************/
static void
{
/* Lower the clock input to the Management Data Clock (by clearing the MDC
* bit), and then delay 10 microseconds.
*/
udelay(10);
}
/******************************************************************************
* Shifts data bits out to the PHY
*
* hw - Struct containing variables accessed by shared code
* data - Data to send out to the PHY
* count - Number of bits to shift out
*
* Bits are shifted out in MSB to LSB order.
******************************************************************************/
static void
{
/* We need to shift "count" number of bits out to the PHY. So, the value
* in the "data" parameter will be shifted out to the PHY one bit at a
* time. In order to do this, "data" must be broken down into bits.
*/
mask = 0x01;
/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
while(mask) {
/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
* then raising and lowering the Management Data Clock. A "0" is
* shifted out to the PHY by setting the MDIO bit to "0" and then
* raising and lowering the clock.
*/
else ctrl &= ~E1000_CTRL_MDIO;
udelay(10);
}
}
/******************************************************************************
* Shifts data bits in from the PHY
*
* hw - Struct containing variables accessed by shared code
*
* Bits are shifted in in MSB to LSB order.
******************************************************************************/
static uint16_t
{
uint8_t i;
/* In order to read a register from the PHY, we need to shift in a total
* of 18 bits from the PHY. The first two bit (turnaround) times are used
* to avoid contention on the MDIO pin when a read operation is performed.
* These two bits are ignored by us and thrown away. Bits are "shifted in"
* by raising the input to the Management Data Clock (setting the MDC bit),
* and then reading the value of the MDIO bit.
*/
/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
ctrl &= ~E1000_CTRL_MDIO_DIR;
ctrl &= ~E1000_CTRL_MDIO;
/* Raise and Lower the clock before reading in the data. This accounts for
* the turnaround bits. The first clock occurred when we clocked out the
* last bit of the Register Address.
*/
for(data = 0, i = 0; i < 16; i++) {
/* Check to see if we shifted in a "1". */
}
return data;
}
/*****************************************************************************
* Reads the value from a PHY register, if the value is on a specific non zero
* page, sets the page first.
*
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to read
******************************************************************************/
static int
{
DEBUGFUNC("e1000_read_phy_reg");
(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
return ret_val;
}
phy_data);
return ret_val;
}
static int
{
uint32_t i;
DEBUGFUNC("e1000_read_phy_reg_ex");
if(reg_addr > MAX_PHY_REG_ADDRESS) {
return -E1000_ERR_PARAM;
}
/* Set up Op-code, Phy Address, and register address in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
(phy_addr << E1000_MDIC_PHY_SHIFT) |
/* Poll the ready bit to see if the MDI read completed */
for(i = 0; i < 64; i++) {
udelay(50);
if(mdic & E1000_MDIC_READY) break;
}
if(!(mdic & E1000_MDIC_READY)) {
DEBUGOUT("MDI Read did not complete\n");
return -E1000_ERR_PHY;
}
if(mdic & E1000_MDIC_ERROR) {
DEBUGOUT("MDI Error\n");
return -E1000_ERR_PHY;
}
} else {
/* We must first send a preamble through the MDIO pin to signal the
* beginning of an MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
/* Now combine the next few fields that are required for a read
* operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine five different times. The format of
* a MII read instruction consists of a shift out of 14 bits and is
* defined as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
* followed by a shift in of 18 bits. This first two bits shifted in
* are TurnAround bits used to avoid contention on the MDIO pin when a
* READ operation is performed. These two bits are thrown away
* followed by a shift in of 16 bits which contains the desired data.
*/
/* Now that we've shifted out the read command to the MII, we need to
* "shift in" the 16-bit value (18 total bits) of the requested PHY
* register address.
*/
}
return E1000_SUCCESS;
}
/******************************************************************************
* Writes a value to a PHY register
*
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to write
* data - data to write to the PHY
******************************************************************************/
static int
{
DEBUGFUNC("e1000_write_phy_reg");
(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
return ret_val;
}
phy_data);
return ret_val;
}
static int
{
uint32_t i;
DEBUGFUNC("e1000_write_phy_reg_ex");
if(reg_addr > MAX_PHY_REG_ADDRESS) {
return -E1000_ERR_PARAM;
}
/* Set up Op-code, Phy Address, register address, and data intended
* for the PHY register in the MDI Control register. The MAC will take
* care of interfacing with the PHY to send the desired data.
*/
(reg_addr << E1000_MDIC_REG_SHIFT) |
(phy_addr << E1000_MDIC_PHY_SHIFT) |
/* Poll the ready bit to see if the MDI read completed */
for(i = 0; i < 640; i++) {
udelay(5);
if(mdic & E1000_MDIC_READY) break;
}
if(!(mdic & E1000_MDIC_READY)) {
DEBUGOUT("MDI Write did not complete\n");
return -E1000_ERR_PHY;
}
} else {
/* We'll need to use the SW defined pins to shift the write command
* out to the PHY. We first send a preamble to the PHY to signal the
* beginning of the MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
/* Now combine the remaining required fields that will indicate a
* write operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine for each field in the command. The
* format of a MII write instruction is as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
*/
mdic <<= 16;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Returns the PHY to the power-on reset state
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static void
{
DEBUGFUNC("e1000_phy_hw_reset");
DEBUGOUT("Resetting Phy...\n");
/* Read the device control register and assert the E1000_CTRL_PHY_RST
* bit. Then, take it out of reset.
*/
mdelay(10);
} else {
/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
* bit to put the PHY into reset. Then, take it out of reset.
*/
mdelay(10);
}
udelay(150);
}
/******************************************************************************
* Resets the PHY
*
* hw - Struct containing variables accessed by shared code
*
* Sets bit 15 of the MII Control regiser
******************************************************************************/
static int
{
DEBUGFUNC("e1000_phy_reset");
return ret_val;
phy_data |= MII_CR_RESET;
return ret_val;
udelay(1);
} else e1000_phy_hw_reset(hw);
return E1000_SUCCESS;
}
/******************************************************************************
* Probes the expected PHY address for known PHY IDs
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int
{
DEBUGFUNC("e1000_detect_gig_phy");
/* Read the PHY ID Registers to identify which PHY is onboard. */
return ret_val;
udelay(20);
return ret_val;
#ifdef LINUX_DRIVER
#endif
case e1000_82543:
break;
case e1000_82544:
break;
case e1000_82540:
case e1000_82545:
case e1000_82545_rev_3:
case e1000_82546:
case e1000_82546_rev_3:
break;
case e1000_82541:
case e1000_82541_rev_2:
case e1000_82547:
case e1000_82547_rev_2:
break;
default:
return -E1000_ERR_CONFIG;
}
return E1000_SUCCESS;
}
return -E1000_ERR_PHY;
}
/******************************************************************************
* Sets up eeprom variables in the hw struct. Must be called after mac_type
* is configured.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
{
DEBUGFUNC("e1000_init_eeprom_params");
case e1000_82542_rev2_0:
case e1000_82542_rev2_1:
case e1000_82543:
case e1000_82544:
break;
case e1000_82540:
case e1000_82545:
case e1000_82545_rev_3:
case e1000_82546:
case e1000_82546_rev_3:
if(eecd & E1000_EECD_SIZE) {
} else {
}
break;
case e1000_82541:
case e1000_82541_rev_2:
case e1000_82547:
case e1000_82547_rev_2:
if (eecd & E1000_EECD_TYPE) {
if (eecd & E1000_EECD_ADDR_BITS) {
} else {
}
} else {
if (eecd & E1000_EECD_ADDR_BITS) {
} else {
}
}
break;
default:
if (eecd & E1000_EECD_ADDR_BITS) {
} else {
}
break;
}
switch (eeprom_size) {
case EEPROM_SIZE_16KB:
break;
case EEPROM_SIZE_8KB:
break;
case EEPROM_SIZE_4KB:
break;
case EEPROM_SIZE_2KB:
break;
case EEPROM_SIZE_1KB:
break;
case EEPROM_SIZE_512B:
break;
case EEPROM_SIZE_128B:
default:
break;
}
}
}
}
/**
* e1000_reset - Reset the adapter
*/
static int
{
/* Repartition Pba for greater than 9k mtu
* To take effect CTRL.RST is required.
*/
pba = E1000_PBA_48K;
} else {
pba = E1000_PBA_30K;
}
/* flow control settings */
#if 0
#endif
return e1000_init_hw(hw);
}
/**
* e1000_sw_init - Initialize general software structures (struct e1000_adapter)
* @adapter: board private structure to initialize
*
* e1000_sw_init initializes the Adapter private data structure.
* Fields are initialized based on PCI device information and
* OS network device settings (MTU size).
**/
static int
{
int result;
/* PCI config space info */
#if 0
#endif
/* identify the MAC */
if (result) {
E1000_ERR("Unknown MAC Type\n");
return result;
}
/* initialize eeprom parameters */
#if 0
#endif
#if 0
hw->report_tx_early = 0;
else
#endif
#if 0
/* Copper options */
}
#endif
return E1000_SUCCESS;
}
static void fill_rx (void)
{
}
static void init_descriptor (void)
{
unsigned long ptr;
unsigned long tctl;
if (ptr & 0xf)
/* Setup the HW Tx Head and Tail descriptor pointers */
tx_tail = 0;
/* Program the Transmit Control Register */
#ifdef LINUX_DRIVER_TCTL
tctl &= ~E1000_TCTL_CT;
#else
#endif
rx_tail = 0;
/* disable receive */
if (ptr & 0xf)
/* Setup the Base and Length of the Rx Descriptor Ring */
/* Setup the HW Rx Head and Tail Descriptor Pointers */
fill_rx();
}
/**************************************************************************
POLL - Wait for a frame
***************************************************************************/
static int
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
/* nic->packetlen should contain length of data */
return 0;
if ( ! retrieve ) return 1;
// printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length);
fill_rx ();
return 1;
}
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
static void
unsigned int type, /* Type */
unsigned int size, /* size */
const char *p) /* Packet */
{
/* send the packet to destination */
struct eth_hdr {
unsigned short type;
} hdr;
DEBUGFUNC("send");
}
DEBUGFUNC("send end");
}
/**************************************************************************
DISABLE - Turn off ethernet interface
***************************************************************************/
{
/* Clear the transmit ring */
/* Clear the receive ring */
/* put the card in its initial state */
/* Turn off the ethernet interface */
mdelay (10);
/* Unmap my window to the device */
}
/**************************************************************************
IRQ - Enable, Disable, or Force interrupts
***************************************************************************/
{
switch ( action ) {
case DISABLE :
break;
case ENABLE :
break;
case FORCE :
break;
}
}
#define BAR_0 0
/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
You should omit the last argument struct pci_device * for a non-PCI NIC
***************************************************************************/
{
int ret_val, i;
if (p == 0)
return 0;
/* Initialize hw with default values */
#if 1
/* Are these variables needed? */
#if 0
#endif
hw.autoneg_failed = 0;
#if 0
#endif
#endif
if(pci_bar_size(p, i) == 0)
continue;
if(pci_find_capability(p, i) & IORESOURCE_IO) {
break;
}
}
/* From Matt Hortman <mbhortman@acpthinclient.com> */
/* MAC and Phy settings */
/* setup the private structure */
if (e1000_sw_init(p, &hw) < 0) {
return 0;
}
/* make sure the EEPROM is good */
if (e1000_validate_eeprom_checksum(&hw) < 0) {
printf ("The EEPROM Checksum Is Not Valid\n");
return 0;
}
/* copy the MAC address out of the EEPROM */
/* reset the hardware with the new settings */
if (ret_val < 0) {
if ((ret_val == -E1000_ERR_NOLINK) ||
(ret_val == -E1000_ERR_TIMEOUT)) {
E1000_ERR("Valid Link not detected\n");
} else {
E1000_ERR("Hardware Initialization Failed\n");
}
return 0;
}
/* point to NIC specific routines */
return 1;
}
PCI_ROM(0x8086, 0x101d, "e1000-82546eb-quad-copper", "Intel EtherExpressPro1000 82546EB Quad Copper"),
};
.type = NIC_DRIVER,
.name = "E1000",
.probe = e1000_probe,
.ids = e1000_nics,
.class = 0,
};