machnode.hpp revision 1203
647N/A/*
4609N/A * Copyright 1997-2010 Sun Microsystems, Inc. All Rights Reserved.
647N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
647N/A *
647N/A * This code is free software; you can redistribute it and/or modify it
647N/A * under the terms of the GNU General Public License version 2 only, as
647N/A * published by the Free Software Foundation.
647N/A *
647N/A * This code is distributed in the hope that it will be useful, but WITHOUT
647N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
647N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
647N/A * version 2 for more details (a copy is included in the LICENSE file that
647N/A * accompanied this code).
647N/A *
647N/A * You should have received a copy of the GNU General Public License version
647N/A * 2 along with this work; if not, write to the Free Software Foundation,
647N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
647N/A *
2362N/A * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
2362N/A * CA 95054 USA or visit www.sun.com if you need additional information or
2362N/A * have any questions.
647N/A *
647N/A */
5270N/A
5270N/Aclass BufferBlob;
5270N/Aclass CodeBuffer;
5270N/Aclass JVMState;
5270N/Aclass MachCallDynamicJavaNode;
5270N/Aclass MachCallJavaNode;
5270N/Aclass MachCallLeafNode;
5270N/Aclass MachCallNode;
4954N/Aclass MachCallRuntimeNode;
647N/Aclass MachCallStaticJavaNode;
647N/Aclass MachEpilogNode;
4609N/Aclass MachIfNode;
647N/Aclass MachNullCheckNode;
647N/Aclass MachOper;
3986N/Aclass MachProjNode;
647N/Aclass MachPrologNode;
647N/Aclass MachReturnNode;
4854N/Aclass MachSafePointNode;
4609N/Aclass MachSpillCopyNode;
3986N/Aclass Matcher;
4609N/Aclass PhaseRegAlloc;
4609N/Aclass RegMask;
3986N/Aclass State;
647N/A
647N/A//---------------------------MachOper------------------------------------------
4854N/Aclass MachOper : public ResourceObj {
647N/Apublic:
647N/A // Allocate right next to the MachNodes in the same arena
4609N/A void *operator new( size_t x, Compile* C ) { return C->node_arena()->Amalloc_D(x); }
647N/A
3986N/A // Opcode
4854N/A virtual uint opcode() const = 0;
3986N/A
647N/A // Number of input edges.
3986N/A // Generally at least 1
647N/A virtual uint num_edges() const { return 1; }
4854N/A // Array of Register masks
4854N/A virtual const RegMask *in_RegMask(int index) const;
4854N/A
4854N/A // Methods to output the encoding of the operand
4854N/A
1945N/A // Negate conditional branches. Error for non-branch Nodes
5270N/A virtual void negate();
647N/A
647N/A // Return the value requested
4854N/A // result register lookup, corresponding to int_format
1945N/A virtual int reg(PhaseRegAlloc *ra_, const Node *node) const;
647N/A // input register lookup, corresponding to ext_format
5270N/A virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const;
5270N/A
647N/A // helpers for MacroAssembler generation from ADLC
647N/A Register as_Register(PhaseRegAlloc *ra_, const Node *node) const {
1945N/A return ::as_Register(reg(ra_, node));
647N/A }
647N/A Register as_Register(PhaseRegAlloc *ra_, const Node *node, int idx) const {
4651N/A return ::as_Register(reg(ra_, node, idx));
4944N/A }
1945N/A FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node) const {
1945N/A return ::as_FloatRegister(reg(ra_, node));
1945N/A }
1945N/A FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
1945N/A return ::as_FloatRegister(reg(ra_, node, idx));
1945N/A }
1945N/A
1945N/A#if defined(IA32) || defined(AMD64)
1945N/A XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node) const {
1945N/A return ::as_XMMRegister(reg(ra_, node));
1945N/A }
4854N/A XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
4854N/A return ::as_XMMRegister(reg(ra_, node, idx));
4854N/A }
4609N/A#endif
4609N/A
4609N/A virtual intptr_t constant() const;
5270N/A virtual bool constant_is_oop() const;
4854N/A virtual jdouble constantD() const;
4854N/A virtual jfloat constantF() const;
5270N/A virtual jlong constantL() const;
4609N/A virtual TypeOopPtr *oop() const;
647N/A virtual int ccode() const;
647N/A // A zero, default, indicates this value is not needed.
647N/A // May need to lookup the base register, as done in int_ and ext_format
4854N/A virtual int base (PhaseRegAlloc *ra_, const Node *node, int idx) const;
4854N/A virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const;
4854N/A virtual int scale() const;
4854N/A // Parameters needed to support MEMORY_INTERFACE access to stackSlot
4854N/A virtual int disp (PhaseRegAlloc *ra_, const Node *node, int idx) const;
4854N/A // Check for PC-Relative displacement
4854N/A virtual bool disp_is_oop() const;
4854N/A virtual int constant_disp() const; // usu. 0, may return Type::OffsetBot
4854N/A virtual int base_position() const; // base edge position, or -1
4854N/A virtual int index_position() const; // index edge position, or -1
4854N/A
4854N/A // Access the TypeKlassPtr of operands with a base==RegI and disp==RegP
1945N/A // Only returns non-null value for i486.ad's indOffset32X
1945N/A virtual const TypePtr *disp_as_type() const { return NULL; }
1945N/A
1945N/A // Return the label
1945N/A virtual Label *label() const;
1945N/A
647N/A // Return the method's address
647N/A virtual intptr_t method() const;
647N/A
5270N/A // Hash and compare over operands are currently identical
647N/A virtual uint hash() const;
647N/A virtual uint cmp( const MachOper &oper ) const;
647N/A
647N/A // Virtual clone, since I do not know how big the MachOper is.
647N/A virtual MachOper *clone(Compile* C) const = 0;
4854N/A
4854N/A // Return ideal Type from simple operands. Fail for complex operands.
647N/A virtual const Type *type() const;
647N/A
647N/A // Set an integer offset if we have one, or error otherwise
647N/A virtual void set_con( jint c0 ) { ShouldNotReachHere(); }
647N/A
647N/A#ifndef PRODUCT
4854N/A // Return name of operand
5270N/A virtual const char *Name() const { return "???";}
5270N/A
5270N/A // Methods to output the text version of the operand
5270N/A virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0;
5270N/A virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0;
5270N/A
5270N/A virtual void dump_spec(outputStream *st) const; // Print per-operand info
5270N/A#endif
5270N/A};
4854N/A
4854N/A//------------------------------MachNode---------------------------------------
4854N/A// Base type for all machine specific nodes. All node classes generated by the
4854N/A// ADLC inherit from this class.
4854N/Aclass MachNode : public Node {
4854N/Apublic:
4854N/A MachNode() : Node((uint)0), _num_opnds(0), _opnds(NULL) {
4854N/A init_class_id(Class_Mach);
4854N/A }
4854N/A // Required boilerplate
4854N/A virtual uint size_of() const { return sizeof(MachNode); }
647N/A virtual int Opcode() const; // Always equal to MachNode
4854N/A virtual uint rule() const = 0; // Machine-specific opcode
4854N/A // Number of inputs which come before the first operand.
647N/A // Generally at least 1, to skip the Control input
1945N/A virtual uint oper_input_base() const { return 1; }
1945N/A
1945N/A // Copy inputs and operands to new node of instruction.
1945N/A // Called from cisc_version() and short_branch_version().
1945N/A // !!!! The method's body is defined in ad_<arch>.cpp file.
1945N/A void fill_new_machnode(MachNode *n, Compile* C) const;
1945N/A
1945N/A // Return an equivalent instruction using memory for cisc_operand position
1945N/A virtual MachNode *cisc_version(int offset, Compile* C);
1945N/A // Modify this instruction's register mask to use stack version for cisc_operand
1945N/A virtual void use_cisc_RegMask();
1945N/A
5270N/A // Support for short branches
5270N/A virtual MachNode *short_branch_version(Compile* C) { return NULL; }
5270N/A bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
5270N/A
5270N/A // First index in _in[] corresponding to operand, or -1 if there is none
5270N/A int operand_index(uint operand) const;
5270N/A
5270N/A // Register class input is expected in
5270N/A virtual const RegMask &in_RegMask(uint) const;
5270N/A
5270N/A // cisc-spillable instructions redefine for use by in_RegMask
5270N/A virtual const RegMask *cisc_RegMask() const { return NULL; }
5270N/A
5270N/A // If this instruction is a 2-address instruction, then return the
5272N/A // index of the input which must match the output. Not nessecary
5272N/A // for instructions which bind the input and output register to the
5270N/A // same singleton regiser (e.g., Intel IDIV which binds AX to be
5270N/A // both an input and an output). It is nessecary when the input and
5270N/A // output have choices - but they must use the same choice.
5270N/A virtual uint two_adr( ) const { return 0; }
5270N/A
5270N/A // Array of complex operand pointers. Each corresponds to zero or
5272N/A // more leafs. Must be set by MachNode constructor to point to an
5270N/A // internal array of MachOpers. The MachOper array is sized by
5270N/A // specific MachNodes described in the ADL.
5270N/A uint _num_opnds;
5270N/A MachOper **_opnds;
5270N/A uint num_opnds() const { return _num_opnds; }
5270N/A
5270N/A // Emit bytes into cbuf
5270N/A virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
1945N/A // Size of instruction in bytes
1945N/A virtual uint size(PhaseRegAlloc *ra_) const;
3986N/A // Helper function that computes size by emitting code
3986N/A virtual uint emit_size(PhaseRegAlloc *ra_) const;
3986N/A
3986N/A // Return the alignment required (in units of relocInfo::addr_unit())
3986N/A // for this instruction (must be a power of 2)
3986N/A virtual int alignment_required() const { return 1; }
3986N/A
1945N/A // Return the padding (in bytes) to be emitted before this
1945N/A // instruction to properly align it.
1945N/A virtual int compute_padding(int current_offset) const { return 0; }
1945N/A
1945N/A // Return number of relocatable values contained in this instruction
1945N/A virtual int reloc() const { return 0; }
1945N/A
1945N/A // Return number of words used for double constants in this instruction
3986N/A virtual int const_size() const { return 0; }
3986N/A
3986N/A // Hash and compare over operands. Used to do GVN on machine Nodes.
3986N/A virtual uint hash() const;
3986N/A virtual uint cmp( const Node &n ) const;
3986N/A
3986N/A // Expand method for MachNode, replaces nodes representing pseudo
3986N/A // instructions with a set of nodes which represent real machine
3986N/A // instructions and compute the same value.
3986N/A virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; }
3986N/A
3986N/A // Bottom_type call; value comes from operand0
3986N/A virtual const class Type *bottom_type() const { return _opnds[0]->type(); }
3986N/A virtual uint ideal_reg() const { const Type *t = _opnds[0]->type(); return t == TypeInt::CC ? Op_RegFlags : Matcher::base2reg[t->base()]; }
3986N/A
3986N/A // If this is a memory op, return the base pointer and fixed offset.
3986N/A // If there are no such, return NULL. If there are multiple addresses
3986N/A // or the address is indeterminate (rare cases) then return (Node*)-1,
3986N/A // which serves as node bottom.
3986N/A // If the offset is not statically determined, set it to Type::OffsetBot.
3986N/A // This method is free to ignore stack slots if that helps.
1945N/A #define TYPE_PTR_SENTINAL ((const TypePtr*)-1)
1945N/A // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible
1945N/A const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const;
1945N/A
1945N/A // Helper for get_base_and_disp: find the base and index input nodes.
647N/A // Returns the MachOper as determined by memory_operand(), for use, if
647N/A // needed by the caller. If (MachOper *)-1 is returned, base and index
647N/A // are set to NodeSentinel. If (MachOper *) NULL is returned, base and
653N/A // index are set to NULL.
653N/A const MachOper* memory_inputs(Node* &base, Node* &index) const;
647N/A
647N/A // Helper for memory_inputs: Which operand carries the necessary info?
647N/A // By default, returns NULL, which means there is no such operand.
647N/A // If it returns (MachOper*)-1, this means there are multiple memories.
647N/A virtual const MachOper* memory_operand() const { return NULL; }
647N/A
647N/A // Call "get_base_and_disp" to decide which category of memory is used here.
4854N/A virtual const class TypePtr *adr_type() const;
4854N/A
4854N/A // Negate conditional branches. Error for non-branch Nodes
4854N/A virtual void negate();
4854N/A
4854N/A // Apply peephole rule(s) to this instruction
4854N/A virtual MachNode *peephole( Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted, Compile* C );
4854N/A
4854N/A // Check for PC-Relative addressing
4854N/A bool is_pc_relative() const { return (flags() & Flag_is_pc_relative) != 0; }
4854N/A
4854N/A // Top-level ideal Opcode matched
4854N/A virtual int ideal_Opcode() const { return Op_Node; }
653N/A
653N/A // Set the branch inside jump MachNodes. Error for non-branch Nodes.
653N/A virtual void label_set( Label& label, uint block_num );
653N/A
647N/A // Adds the label for the case
653N/A virtual void add_case_label( int switch_val, Label* blockLabel);
653N/A
647N/A // Set the absolute address for methods
647N/A virtual void method_set( intptr_t addr );
647N/A
4343N/A // Should we clone rather than spill this instruction?
4343N/A bool rematerialize() const;
4343N/A
4343N/A // Get the pipeline info
4343N/A static const Pipeline *pipeline_class();
4343N/A virtual const Pipeline *pipeline() const;
647N/A
4343N/A#ifndef PRODUCT
647N/A virtual const char *Name() const = 0; // Machine-specific name
647N/A virtual void dump_spec(outputStream *st) const; // Print per-node info
647N/A void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
647N/A#endif
647N/A};
647N/A
647N/A//------------------------------MachIdealNode----------------------------
647N/A// Machine specific versions of nodes that must be defined by user.
653N/A// These are not converted by matcher from ideal nodes to machine nodes
647N/A// but are inserted into the code by the compiler.
647N/Aclass MachIdealNode : public MachNode {
647N/Apublic:
647N/A MachIdealNode( ) {}
647N/A
647N/A // Define the following defaults for non-matched machine nodes
647N/A virtual uint oper_input_base() const { return 0; }
647N/A virtual uint rule() const { return 9999999; }
4343N/A virtual const class Type *bottom_type() const { return _opnds == NULL ? Type::CONTROL : MachNode::bottom_type(); }
4343N/A};
4343N/A
4343N/A//------------------------------MachTypeNode----------------------------
647N/A// Machine Nodes that need to retain a known Type.
647N/Aclass MachTypeNode : public MachNode {
4343N/A virtual uint size_of() const { return sizeof(*this); } // Size is bigger
4343N/Apublic:
4343N/A const Type *_bottom_type;
4343N/A
4343N/A virtual const class Type *bottom_type() const { return _bottom_type; }
4343N/A#ifndef PRODUCT
647N/A virtual void dump_spec(outputStream *st) const;
4343N/A#endif
647N/A};
3986N/A
3986N/A//------------------------------MachBreakpointNode----------------------------
3986N/A// Machine breakpoint or interrupt Node
3986N/Aclass MachBreakpointNode : public MachIdealNode {
3986N/Apublic:
3986N/A MachBreakpointNode( ) {}
3986N/A virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
3986N/A virtual uint size(PhaseRegAlloc *ra_) const;
4854N/A
4854N/A#ifndef PRODUCT
4854N/A virtual const char *Name() const { return "Breakpoint"; }
4854N/A virtual void format( PhaseRegAlloc *, outputStream *st ) const;
4854N/A#endif
3986N/A};
3986N/A
3986N/A//------------------------------MachUEPNode-----------------------------------
3986N/A// Machine Unvalidated Entry Point Node
3986N/Aclass MachUEPNode : public MachIdealNode {
3986N/Apublic:
3986N/A MachUEPNode( ) {}
3986N/A virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
3986N/A virtual uint size(PhaseRegAlloc *ra_) const;
3986N/A
3986N/A#ifndef PRODUCT
3986N/A virtual const char *Name() const { return "Unvalidated-Entry-Point"; }
3986N/A virtual void format( PhaseRegAlloc *, outputStream *st ) const;
3986N/A#endif
3986N/A};
3986N/A
3986N/A//------------------------------MachPrologNode--------------------------------
3986N/A// Machine function Prolog Node
3986N/Aclass MachPrologNode : public MachIdealNode {
3986N/Apublic:
3986N/A MachPrologNode( ) {}
3986N/A virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
3986N/A virtual uint size(PhaseRegAlloc *ra_) const;
3986N/A virtual int reloc() const;
3986N/A
3986N/A#ifndef PRODUCT
3986N/A virtual const char *Name() const { return "Prolog"; }
3986N/A virtual void format( PhaseRegAlloc *, outputStream *st ) const;
3986N/A#endif
3986N/A};
1945N/A
4954N/A//------------------------------MachEpilogNode--------------------------------
1945N/A// Machine function Epilog Node
1945N/Aclass MachEpilogNode : public MachIdealNode {
4954N/Apublic:
4954N/A MachEpilogNode(bool do_poll = false) : _do_polling(do_poll) {}
4954N/A virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
647N/A virtual uint size(PhaseRegAlloc *ra_) const;
653N/A virtual int reloc() const;
647N/A virtual const Pipeline *pipeline() const;
4954N/A
4954N/Aprivate:
647N/A bool _do_polling;
647N/A
647N/Apublic:
647N/A bool do_polling() const { return _do_polling; }
647N/A
647N/A // Offset of safepoint from the beginning of the node
4954N/A int safepoint_offset() const;
4954N/A
4954N/A#ifndef PRODUCT
4954N/A virtual const char *Name() const { return "Epilog"; }
4954N/A virtual void format( PhaseRegAlloc *, outputStream *st ) const;
1945N/A#endif
1945N/A};
1945N/A
647N/A//------------------------------MachNopNode-----------------------------------
647N/A// Machine function Nop Node
3986N/Aclass MachNopNode : public MachIdealNode {
647N/Aprivate:
647N/A int _count;
647N/Apublic:
647N/A MachNopNode( ) : _count(1) {}
647N/A MachNopNode( int count ) : _count(count) {}
647N/A virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
647N/A virtual uint size(PhaseRegAlloc *ra_) const;
647N/A
647N/A virtual const class Type *bottom_type() const { return Type::CONTROL; }
647N/A
3986N/A virtual int ideal_Opcode() const { return Op_Con; } // bogus; see output.cpp
3986N/A virtual const Pipeline *pipeline() const;
3986N/A#ifndef PRODUCT
647N/A virtual const char *Name() const { return "Nop"; }
647N/A virtual void format( PhaseRegAlloc *, outputStream *st ) const;
647N/A virtual void dump_spec(outputStream *st) const { } // No per-operand info
647N/A#endif
647N/A};
647N/A
4609N/A//------------------------------MachSpillCopyNode------------------------------
4609N/A// Machine SpillCopy Node. Copies 1 or 2 words from any location to any
4609N/A// location (stack or register).
4609N/Aclass MachSpillCopyNode : public MachIdealNode {
4609N/A const RegMask *_in; // RegMask for input
4609N/A const RegMask *_out; // RegMask for output
4609N/A const Type *_type;
4609N/Apublic:
4609N/A MachSpillCopyNode( Node *n, const RegMask &in, const RegMask &out ) :
4609N/A MachIdealNode(), _in(&in), _out(&out), _type(n->bottom_type()) {
4609N/A init_class_id(Class_MachSpillCopy);
4609N/A init_flags(Flag_is_Copy);
4609N/A add_req(NULL);
4854N/A add_req(n);
4854N/A }
4854N/A virtual uint size_of() const { return sizeof(*this); }
4854N/A void set_out_RegMask(const RegMask &out) { _out = &out; }
647N/A void set_in_RegMask(const RegMask &in) { _in = &in; }
647N/A virtual const RegMask &out_RegMask() const { return *_out; }
647N/A virtual const RegMask &in_RegMask(uint) const { return *_in; }
647N/A virtual const class Type *bottom_type() const { return _type; }
647N/A virtual uint ideal_reg() const { return Matcher::base2reg[_type->base()]; }
5270N/A virtual uint oper_input_base() const { return 1; }
5270N/A uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
647N/A
647N/A virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
3986N/A virtual uint size(PhaseRegAlloc *ra_) const;
3986N/A
5270N/A#ifndef PRODUCT
647N/A virtual const char *Name() const { return "MachSpillCopy"; }
3986N/A virtual void format( PhaseRegAlloc *, outputStream *st ) const;
3986N/A#endif
5270N/A};
5270N/A
5270N/A//------------------------------MachNullChkNode--------------------------------
647N/A// Machine-dependent null-pointer-check Node. Points a real MachNode that is
647N/A// also some kind of memory op. Turns the indicated MachNode into a
3986N/A// conditional branch with good latency on the ptr-not-null path and awful
3986N/A// latency on the pointer-is-null path.
5270N/A
647N/Aclass MachNullCheckNode : public MachIdealNode {
647N/Apublic:
5270N/A const uint _vidx; // Index of memop being tested
5272N/A MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachIdealNode(), _vidx(vidx) {
5272N/A init_class_id(Class_MachNullCheck);
5270N/A init_flags(Flag_is_Branch | Flag_is_pc_relative);
5270N/A add_req(ctrl);
5270N/A add_req(memop);
5270N/A }
5270N/A
1945N/A virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
1945N/A virtual bool pinned() const { return true; };
647N/A virtual void negate() { }
647N/A virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; }
5270N/A virtual uint ideal_reg() const { return NotAMachineReg; }
647N/A virtual const RegMask &in_RegMask(uint) const;
647N/A virtual const RegMask &out_RegMask() const { return RegMask::Empty; }
647N/A#ifndef PRODUCT
647N/A virtual const char *Name() const { return "NullCheck"; }
647N/A virtual void format( PhaseRegAlloc *, outputStream *st ) const;
5270N/A#endif
647N/A};
647N/A
647N/A//------------------------------MachProjNode----------------------------------
647N/A// Machine-dependent Ideal projections (how is that for an oxymoron). Really
647N/A// just MachNodes made by the Ideal world that replicate simple projections
647N/A// but with machine-dependent input & output register masks. Generally
647N/A// produced as part of calling conventions. Normally I make MachNodes as part
647N/A// of the Matcher process, but the Matcher is ill suited to issues involving
647N/A// frame handling, so frame handling is all done in the Ideal world with
5270N/A// occasional callbacks to the machine model for important info.
647N/Aclass MachProjNode : public ProjNode {
647N/Apublic:
647N/A MachProjNode( Node *multi, uint con, const RegMask &out, uint ideal_reg ) : ProjNode(multi,con), _rout(out), _ideal_reg(ideal_reg) {}
647N/A RegMask _rout;
647N/A const uint _ideal_reg;
647N/A enum projType {
647N/A unmatched_proj = 0, // Projs for Control, I/O, memory not matched
5270N/A fat_proj = 999 // Projs killing many regs, defined by _rout
647N/A };
647N/A virtual int Opcode() const;
647N/A virtual const Type *bottom_type() const;
647N/A virtual const TypePtr *adr_type() const;
647N/A virtual const RegMask &in_RegMask(uint) const { return RegMask::Empty; }
1945N/A virtual const RegMask &out_RegMask() const { return _rout; }
647N/A virtual uint ideal_reg() const { return _ideal_reg; }
5270N/A // Need size_of() for virtual ProjNode::clone()
5270N/A virtual uint size_of() const { return sizeof(MachProjNode); }
5270N/A#ifndef PRODUCT
3986N/A virtual void dump_spec(outputStream *st) const;
5270N/A#endif
3986N/A};
5270N/A
1945N/A//------------------------------MachIfNode-------------------------------------
5270N/A// Machine-specific versions of IfNodes
647N/Aclass MachIfNode : public MachNode {
5270N/A virtual uint size_of() const { return sizeof(*this); } // Size is bigger
5270N/Apublic:
3986N/A float _prob; // Probability branch goes either way
5270N/A float _fcnt; // Frequency counter
3986N/A MachIfNode() : MachNode() {
5270N/A init_class_id(Class_MachIf);
5270N/A }
5270N/A#ifndef PRODUCT
5270N/A virtual void dump_spec(outputStream *st) const;
5270N/A#endif
647N/A};
647N/A
647N/A//------------------------------MachFastLockNode-------------------------------------
647N/A// Machine-specific versions of FastLockNodes
647N/Aclass MachFastLockNode : public MachNode {
647N/A virtual uint size_of() const { return sizeof(*this); } // Size is bigger
647N/Apublic:
647N/A BiasedLockingCounters* _counters;
5270N/A
1945N/A MachFastLockNode() : MachNode() {}
1945N/A};
1945N/A
1945N/A//------------------------------MachReturnNode--------------------------------
1945N/A// Machine-specific versions of subroutine returns
1945N/Aclass MachReturnNode : public MachNode {
1945N/A virtual uint size_of() const; // Size is bigger
1945N/Apublic:
1945N/A RegMask *_in_rms; // Input register masks, set during allocation
5270N/A ReallocMark _nesting; // assertion check for reallocations
647N/A const TypePtr* _adr_type; // memory effects of call or return
647N/A MachReturnNode() : MachNode() {
647N/A init_class_id(Class_MachReturn);
5270N/A _adr_type = TypePtr::BOTTOM; // the default: all of memory
5270N/A }
5270N/A
5270N/A void set_adr_type(const TypePtr* atp) { _adr_type = atp; }
5270N/A
5270N/A virtual const RegMask &in_RegMask(uint) const;
647N/A virtual bool pinned() const { return true; };
virtual const TypePtr *adr_type() const;
};
//------------------------------MachSafePointNode-----------------------------
// Machine-specific versions of safepoints
class MachSafePointNode : public MachReturnNode {
public:
OopMap* _oop_map; // Array of OopMap info (8-bit char) for GC
JVMState* _jvms; // Pointer to list of JVM State Objects
uint _jvmadj; // Extra delta to jvms indexes (mach. args)
OopMap* oop_map() const { return _oop_map; }
void set_oop_map(OopMap* om) { _oop_map = om; }
MachSafePointNode() : MachReturnNode(), _oop_map(NULL), _jvms(NULL), _jvmadj(0) {
init_class_id(Class_MachSafePoint);
init_flags(Flag_is_safepoint_node);
}
virtual JVMState* jvms() const { return _jvms; }
void set_jvms(JVMState* s) {
_jvms = s;
}
bool is_safepoint_node() const { return (flags() & Flag_is_safepoint_node) != 0; }
virtual const Type *bottom_type() const;
virtual const RegMask &in_RegMask(uint) const;
// Functionality from old debug nodes
Node *returnadr() const { return in(TypeFunc::ReturnAdr); }
Node *frameptr () const { return in(TypeFunc::FramePtr); }
Node *local(const JVMState* jvms, uint idx) const {
assert(verify_jvms(jvms), "jvms must match");
return in(_jvmadj + jvms->locoff() + idx);
}
Node *stack(const JVMState* jvms, uint idx) const {
assert(verify_jvms(jvms), "jvms must match");
return in(_jvmadj + jvms->stkoff() + idx);
}
Node *monitor_obj(const JVMState* jvms, uint idx) const {
assert(verify_jvms(jvms), "jvms must match");
return in(_jvmadj + jvms->monitor_obj_offset(idx));
}
Node *monitor_box(const JVMState* jvms, uint idx) const {
assert(verify_jvms(jvms), "jvms must match");
return in(_jvmadj + jvms->monitor_box_offset(idx));
}
void set_local(const JVMState* jvms, uint idx, Node *c) {
assert(verify_jvms(jvms), "jvms must match");
set_req(_jvmadj + jvms->locoff() + idx, c);
}
void set_stack(const JVMState* jvms, uint idx, Node *c) {
assert(verify_jvms(jvms), "jvms must match");
set_req(_jvmadj + jvms->stkoff() + idx, c);
}
void set_monitor(const JVMState* jvms, uint idx, Node *c) {
assert(verify_jvms(jvms), "jvms must match");
set_req(_jvmadj + jvms->monoff() + idx, c);
}
};
//------------------------------MachCallNode----------------------------------
// Machine-specific versions of subroutine calls
class MachCallNode : public MachSafePointNode {
protected:
virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
virtual uint cmp( const Node &n ) const;
virtual uint size_of() const = 0; // Size is bigger
public:
const TypeFunc *_tf; // Function type
address _entry_point; // Address of the method being called
float _cnt; // Estimate of number of times called
uint _argsize; // Size of argument block on stack
const TypeFunc* tf() const { return _tf; }
const address entry_point() const { return _entry_point; }
const float cnt() const { return _cnt; }
uint argsize() const { return _argsize; }
void set_tf(const TypeFunc* tf) { _tf = tf; }
void set_entry_point(address p) { _entry_point = p; }
void set_cnt(float c) { _cnt = c; }
void set_argsize(int s) { _argsize = s; }
MachCallNode() : MachSafePointNode() {
init_class_id(Class_MachCall);
init_flags(Flag_is_Call);
}
virtual const Type *bottom_type() const;
virtual bool pinned() const { return false; }
virtual const Type *Value( PhaseTransform *phase ) const;
virtual const RegMask &in_RegMask(uint) const;
virtual int ret_addr_offset() { return 0; }
bool returns_long() const { return tf()->return_type() == T_LONG; }
bool return_value_is_used() const;
#ifndef PRODUCT
virtual void dump_spec(outputStream *st) const;
#endif
};
//------------------------------MachCallJavaNode------------------------------
// "Base" class for machine-specific versions of subroutine calls
class MachCallJavaNode : public MachCallNode {
protected:
virtual uint cmp( const Node &n ) const;
virtual uint size_of() const; // Size is bigger
public:
ciMethod* _method; // Method being direct called
int _bci; // Byte Code index of call byte code
bool _optimized_virtual; // Tells if node is a static call or an optimized virtual
bool _method_handle_invoke; // Tells if the call has to preserve SP
MachCallJavaNode() : MachCallNode() {
init_class_id(Class_MachCallJava);
}
virtual const RegMask &in_RegMask(uint) const;
#ifndef PRODUCT
virtual void dump_spec(outputStream *st) const;
#endif
};
//------------------------------MachCallStaticJavaNode------------------------
// Machine-specific versions of monomorphic subroutine calls
class MachCallStaticJavaNode : public MachCallJavaNode {
virtual uint cmp( const Node &n ) const;
virtual uint size_of() const; // Size is bigger
public:
const char *_name; // Runtime wrapper name
MachCallStaticJavaNode() : MachCallJavaNode() {
init_class_id(Class_MachCallStaticJava);
}
// If this is an uncommon trap, return the request code, else zero.
int uncommon_trap_request() const;
virtual int ret_addr_offset();
#ifndef PRODUCT
virtual void dump_spec(outputStream *st) const;
void dump_trap_args(outputStream *st) const;
#endif
};
//------------------------------MachCallDynamicJavaNode------------------------
// Machine-specific versions of possibly megamorphic subroutine calls
class MachCallDynamicJavaNode : public MachCallJavaNode {
public:
int _vtable_index;
MachCallDynamicJavaNode() : MachCallJavaNode() {
init_class_id(Class_MachCallDynamicJava);
DEBUG_ONLY(_vtable_index = -99); // throw an assert if uninitialized
}
virtual int ret_addr_offset();
#ifndef PRODUCT
virtual void dump_spec(outputStream *st) const;
#endif
};
//------------------------------MachCallRuntimeNode----------------------------
// Machine-specific versions of subroutine calls
class MachCallRuntimeNode : public MachCallNode {
virtual uint cmp( const Node &n ) const;
virtual uint size_of() const; // Size is bigger
public:
const char *_name; // Printable name, if _method is NULL
MachCallRuntimeNode() : MachCallNode() {
init_class_id(Class_MachCallRuntime);
}
virtual int ret_addr_offset();
#ifndef PRODUCT
virtual void dump_spec(outputStream *st) const;
#endif
};
class MachCallLeafNode: public MachCallRuntimeNode {
public:
MachCallLeafNode() : MachCallRuntimeNode() {
init_class_id(Class_MachCallLeaf);
}
};
//------------------------------MachHaltNode-----------------------------------
// Machine-specific versions of halt nodes
class MachHaltNode : public MachReturnNode {
public:
virtual JVMState* jvms() const;
};
//------------------------------MachTempNode-----------------------------------
// Node used by the adlc to construct inputs to represent temporary registers
class MachTempNode : public MachNode {
private:
MachOper *_opnd_array[1];
public:
virtual const RegMask &out_RegMask() const { return *_opnds[0]->in_RegMask(0); }
virtual uint rule() const { return 9999999; }
virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {}
MachTempNode(MachOper* oper) {
init_class_id(Class_MachTemp);
_num_opnds = 1;
_opnds = _opnd_array;
add_req(NULL);
_opnds[0] = oper;
}
virtual uint size_of() const { return sizeof(MachTempNode); }
#ifndef PRODUCT
virtual void format(PhaseRegAlloc *, outputStream *st ) const {}
virtual const char *Name() const { return "MachTemp";}
#endif
};
//------------------------------labelOper--------------------------------------
// Machine-independent version of label operand
class labelOper : public MachOper {
private:
virtual uint num_edges() const { return 0; }
public:
// Supported for fixed size branches
Label* _label; // Label for branch(es)
uint _block_num;
labelOper() : _block_num(0), _label(0) {}
labelOper(Label* label, uint block_num) : _label(label), _block_num(block_num) {}
labelOper(labelOper* l) : _label(l->_label) , _block_num(l->_block_num) {}
virtual MachOper *clone(Compile* C) const;
virtual Label *label() const { return _label; }
virtual uint opcode() const;
virtual uint hash() const;
virtual uint cmp( const MachOper &oper ) const;
#ifndef PRODUCT
virtual const char *Name() const { return "Label";}
virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const;
virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); }
#endif
};
//------------------------------methodOper--------------------------------------
// Machine-independent version of method operand
class methodOper : public MachOper {
private:
virtual uint num_edges() const { return 0; }
public:
intptr_t _method; // Address of method
methodOper() : _method(0) {}
methodOper(intptr_t method) : _method(method) {}
virtual MachOper *clone(Compile* C) const;
virtual intptr_t method() const { return _method; }
virtual uint opcode() const;
virtual uint hash() const;
virtual uint cmp( const MachOper &oper ) const;
#ifndef PRODUCT
virtual const char *Name() const { return "Method";}
virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const;
virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); }
#endif
};