c1_LinearScan.cpp revision 1969
1472N/A * or visit www.oracle.com if you need additional information or have any
1879N/A#include "precompiled.hpp"
1879N/A#include "c1/c1_CFGPrinter.hpp"
1879N/A#include "c1/c1_CodeStubs.hpp"
1879N/A#include "c1/c1_Compilation.hpp"
1879N/A#include "c1/c1_FrameMap.hpp"
1879N/A#include "c1/c1_LIRGenerator.hpp"
1879N/A#include "c1/c1_LinearScan.hpp"
1879N/A#include "c1/c1_ValueStack.hpp"
1879N/A#include "utilities/bitMap.inline.hpp"
1879N/A#ifdef TARGET_ARCH_x86
1879N/A# include "vmreg_x86.inline.hpp"
1879N/A#ifdef TARGET_ARCH_sparc
1879N/A# include "vmreg_sparc.inline.hpp"
1879N/A#ifdef TARGET_ARCH_zero
1879N/A# include "vmreg_zero.inline.hpp"
0N/A #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
0N/Astatic int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 1, -1};
0N/Astatic int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1};
0N/A , _has_fpu_registers(false)
0N/A , _max_spills(0)
0N/A , _needs_full_resort(false)
304N/A assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
0N/A return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
0N/A return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
0N/A return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
0N/A int spill_slot;
0N/A if (double_word) {
0N/A _max_spills++;
0N/A _max_spills++;
0N/A case noDefinitionFound:
0N/A case oneDefinitionFound:
0N/A assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
0N/A assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
0N/A case noOptimization:
0N/A case oneDefinitionFound: {
0N/A case oneMoveInserted: {
0N/A case storeAtDefinition:
0N/A case startInMemory:
0N/A case noOptimization:
0N/A case noDefinitionFound:
0N/A assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
0N/A assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
0N/A assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
0N/A for (int i = 0; i < num_blocks; i++) {
0N/A assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
0N/A assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
0N/A assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
304N/A assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
0N/A int num_instructions = 0;
0N/A for (i = 0; i < num_blocks; i++) {
0N/A for (i = 0; i < num_blocks; i++) {
0N/Avoid LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
304N/A assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
304N/A assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
304N/A assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
0N/A bool local_has_fpu_registers = false;
0N/A int local_num_calls = 0;
0N/A for (int i = 0; i < num_blocks; i++) {
304N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id()));
3932N/A // Add uses of live locals from interpreter's point of view for proper debug information generation
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
3932N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen()));
0N/A TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
304N/A bool change_occurred;
0N/A bool change_occurred_in_block;
0N/A int iteration_count = 0;
0N/A change_occurred = false;
0N/A change_occurred_in_block = false;
0N/A change_occurred = true;
0N/A change_occurred_in_block = true;
304N/A tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
304N/A tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
304N/A } while (change_occurred);
304N/A for (int i = 0; i < num_blocks; i++) {
0N/A tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
0N/A tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
0N/A for (int j = 0; j < num_blocks; j++) {
1187N/A assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
304N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
0N/A assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
304N/A TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
0N/Avoid LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
0N/Avoid LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
304N/A bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
0N/A if (result_in_memory) {
0N/A // input operand must have a register instead of output operand (leads to better register allocation)
0N/A return shouldHaveRegister;
0N/A return mustHaveRegister;
0N/A bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
0N/A if (result_in_memory) {
304N/A return mustHaveRegister;
0N/A // input operand must have a register instead of output operand (leads to better register allocation)
0N/A return mustHaveRegister;
0N/A return shouldHaveRegister;
0N/A return shouldHaveRegister;
0N/A assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
0N/A return shouldHaveRegister;
0N/A assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
0N/A return shouldHaveRegister;
304N/A case lir_logic_and:
0N/A case lir_logic_or:
0N/A case lir_logic_xor:
0N/A assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
0N/A return shouldHaveRegister;
3158N/A return mustHaveRegister;
3158N/A if (o->is_single_stack()) {
3158N/A } else if (o->is_double_stack()) {
3158N/A assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
3158N/A TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
3158N/A int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
3158N/A case lir_convert: {
3158N/A TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
3158N/A TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
3158N/A int num_caller_save_registers = 0;
3158N/A assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
3158N/A if (has_fpu_registers()) {
3158N/A assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
3158N/A assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
3158N/A for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
3158N/A assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
3932N/A for (int k = 0; k < num_caller_save_registers; k++) {
3158N/A for (i = 0; i < interval_count(); i++) {
3932N/A for (i = 0; i < interval_count(); i++) {
3158N/Avoid LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
3158N/A assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
3158N/A assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
3158N/A if (_needs_full_resort) {
3158N/A _needs_full_resort = false;
3158N/A int sorted_len = 0;
3158N/A int unsorted_idx;
3158N/A int sorted_idx = 0;
0N/A if (_needs_full_resort) {
0N/A _needs_full_resort = false;
3158N/A if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
3158N/A create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval);
0N/A if (has_fpu_registers()) {
0N/A create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
0N/A create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
0N/A if (has_fpu_registers()) {
0N/AInterval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
0N/A assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
0N/A return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
0N/A assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
0N/A return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
0N/A assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
3158N/Avoid LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
0N/A for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
304N/A assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
0N/A if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
0N/Avoid LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
0N/A assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
0N/A// insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
0N/A for (i = 0; i < num_blocks; i++) {
3158N/A if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
3158N/A assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
0N/A assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
0N/A if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
0N/A TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
0N/A for (i = 0; i < num_blocks; i++) {
3158N/A TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
0N/Avoid LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
3158N/A _needs_full_resort = true;
0N/A for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
0N/A // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
0N/Avoid LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
0N/A Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
610N/A if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
0N/Avoid LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
0N/A TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
0N/A for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
0N/A // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
0N/A resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
0N/A for (i = 0; i < num_blocks; i++) {
0N/A for (i = 0; i < num_blocks; i++) {
304N/A assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
0N/A assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
0N/A#ifdef __SOFTFP__
0N/A assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
0N/A#ifdef __SOFTFP__
0N/A assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
0N/A "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
0N/A assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
0N/A#ifndef __SOFTFP__
3158N/A assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
0N/A assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
0N/A assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
0N/A assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
0N/A assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
0N/A assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
0N/A assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
0N/A LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
0N/A assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
0N/A assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
0N/A assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
0N/A LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
0N/A assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
0N/A assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
0N/A assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
0N/A if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
304N/A assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
0N/A assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
0N/A if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
0N/A assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
116N/AOopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
116N/A bool is_patch_info = false;
116N/A for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
116N/A assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
116N/A assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2062N/A assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
116N/A map->set_oop(frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
116N/A for (int i = 0; i < locks_count; i++) {
116N/Avoid LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
116N/A _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
116N/Aint LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
116N/Aint LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
116N/A DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
116N/A DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
116N/A assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
116N/A if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
116N/A // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
116N/A assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
116N/A assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
116N/A assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
116N/A assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
116N/A assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
0N/Aint LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
0N/A assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
0N/A assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
0N/A // The operand must be live because debug information is considered when building the intervals
0N/A assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
0N/AIRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
0N/A caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
0N/A if (nof_locals > 0) {
0N/A for(int i = 0; i < nof_locals; i++) {
304N/A int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
0N/A return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
0N/A info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
0N/A DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
0N/A if (!use_fpu_stack_allocation()) {
0N/A int insert_point = 0;
0N/A if (insert_point != j) {
0N/A for (int i = 0; i < num_blocks; i++) {
0N/A if (use_fpu_stack_allocation()) {
0N/A for (i = 0; i < interval_count(); i++) {
0N/A for (i = 0; i < block_count(); i++) {
0N/A tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
0N/A if (PrintCFGToFile) {
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
0N/A TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
0N/A tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
0N/A tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
0N/A if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
304N/A tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
512N/A create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
0N/A for (int i = 0; i < block_count(); i++) {
304N/A bool check_live = true;
0N/A check_live = false;
0N/A if (check_live) {