/*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "c1/c1_CFGPrinter.hpp"
#include "c1/c1_CodeStubs.hpp"
#include "c1/c1_Compilation.hpp"
#include "c1/c1_FrameMap.hpp"
#include "c1/c1_LIRGenerator.hpp"
#include "c1/c1_LinearScan.hpp"
#include "c1/c1_ValueStack.hpp"
#include "utilities/bitMap.inline.hpp"
#ifdef TARGET_ARCH_x86
# include "vmreg_x86.inline.hpp"
#endif
#ifdef TARGET_ARCH_sparc
# include "vmreg_sparc.inline.hpp"
#endif
#ifdef TARGET_ARCH_zero
# include "vmreg_zero.inline.hpp"
#endif
#ifdef TARGET_ARCH_arm
# include "vmreg_arm.inline.hpp"
#endif
#ifdef TARGET_ARCH_ppc
# include "vmreg_ppc.inline.hpp"
#endif
#ifndef PRODUCT
// helper macro for short definition of timer
#define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
// helper macro for short definition of trace-output inside code
if (TraceLinearScanLevel >= level) { \
code; \
}
#else
#endif
// Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
#ifdef _LP64
#else
#endif
// Implementation of LinearScan
, _has_fpu_registers(false)
, _num_calls(-1)
, _max_spills(0)
, _unused_spill_slot(-1)
, _intervals(0) // initialized later with correct length
, _needs_full_resort(false)
, _lir_ops(0) // initialized later with correct length
, _block_of_op(0) // initialized later with correct length
, _has_info(0)
, _has_call(0)
, _scope_value_cache(0) // initialized later with correct length
, _interval_in_loop(0, 0) // initialized later with correct length
#ifdef X86
#endif
{
}
// ********** functions for converting LIR-Operands to register numbers
//
// Emulate a flat register file comprising physical integer registers,
// physical floating-point registers and virtual registers, in that order.
// Virtual registers already have appropriate numbers, since V0 is
// the number of physical registers.
// Returns -1 for hi word if opr is a single word operand.
//
// Note: the inverse operation (calculating an operand for register numbers)
// is done in calc_operand_for_interval()
if (opr->is_virtual_register()) {
return opr->vreg_number();
} else if (opr->is_single_cpu()) {
} else if (opr->is_double_cpu()) {
return opr->cpu_regnrLo();
#ifdef X86
} else if (opr->is_single_xmm()) {
} else if (opr->is_double_xmm()) {
#endif
} else if (opr->is_single_fpu()) {
} else if (opr->is_double_fpu()) {
} else {
return -1;
}
}
if (opr->is_virtual_register()) {
return -1;
} else if (opr->is_single_cpu()) {
return -1;
} else if (opr->is_double_cpu()) {
return opr->cpu_regnrHi();
#ifdef X86
} else if (opr->is_single_xmm()) {
return -1;
} else if (opr->is_double_xmm()) {
return -1;
#endif
} else if (opr->is_single_fpu()) {
return -1;
} else if (opr->is_double_fpu()) {
} else {
return -1;
}
}
// ********** functions for classification of intervals
}
}
}
#if defined(__SOFTFP__) || defined(E500V2)
#else
#endif // __SOFTFP__ or E500V2
}
}
#if defined(__SOFTFP__) || defined(E500V2)
return false;
#else
#endif // __SOFTFP__ or E500V2
}
// fixed intervals not needed for FPU stack allocation
return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
}
// fixed intervals never contain oops
}
// ********** General helper functions
// compute next unused stack index that can be used for spilling
int spill_slot;
if (double_word) {
// alignment of double-word values
// the hole because of the alignment is filled with the next single-word value
_max_spills++;
}
_max_spills += 2;
} else if (_unused_spill_slot != -1) {
// re-use hole that was the result of a previous double-word alignment
_unused_spill_slot = -1;
} else {
_max_spills++;
}
// the class OopMapValue uses only 11 bits for storing the name of the
// oop location. So a stack slot bigger than 2^11 leads to an overflow
// that is not reported in product builds. Prevent this by checking the
// spill slot here (altough this value and the later used location name
// are slightly different)
if (result > 2000) {
bailout("too many stack slots used");
}
return result;
}
// assign the canonical spill slot of the parent (if a part of the interval
// is already spilled) or allocate a new spill slot
if (it->canonical_spill_slot() >= 0) {
} else {
}
}
bailout("frame too large");
}
}
// create a new interval with a predefined reg_num
// (only used for parent intervals that are created during the building phase)
// assign register number for precolored intervals
}
return interval;
}
// assign a new reg_num to the interval and append it to the list of intervals
// (only used for child intervals that are created during register allocation)
}
// copy the vreg-flags if an interval is split
}
}
// Note: do not copy the must_start_in_memory flag because it is not necessary for child
// intervals (only the very beginning of the interval must be in memory)
}
// ********** spill move optimization
// eliminate moves from register to stack if stack slot is known to be correct
// called during building of intervals
switch (interval->spill_state()) {
case noDefinitionFound:
break;
case oneDefinitionFound:
assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
// second definition found, so no spill optimization possible for this interval
} else {
// two consecutive definitions (because of two-operand LIR form)
assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
}
break;
case noOptimization:
// nothing to do
break;
default:
assert(false, "other states not allowed at this time");
}
}
// called during register allocation
switch (interval->spill_state()) {
case oneDefinitionFound: {
if (def_loop_depth < spill_loop_depth) {
// the loop depth of the spilling position is higher then the loop depth
// at the definition of the interval -> move write to memory out of loop
// by storing at definitin of the interval
} else {
// the interval is currently spilled only once, so for now there is no
// reason to store the interval at the definition
}
break;
}
case oneMoveInserted: {
// the interval is spilled more then once, so it is better to store it to
// memory at the definition
break;
}
case storeAtDefinition:
case startInMemory:
case noOptimization:
case noDefinitionFound:
// nothing to do
break;
default:
assert(false, "other states not allowed at this time");
}
}
}
// called once before asignment of register numbers
// collect all intervals that must be stored after their definion.
// the list is sorted by Interval::spill_definition_pos
#ifdef ASSERT
assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
}
assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
}
#endif
for (int i = 0; i < num_blocks; i++) {
bool has_new = false;
// iterate all instructions of the block. skip the first because it is always a label
for (int j = 1; j < num_inst; j++) {
if (op_id == -1) {
// remove move from register to stack if the stack slot is guaranteed to be correct.
// only moves that have been inserted by LinearScan can be removed.
assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
// move target is a stack slot that is always correct, so eliminate instruction
TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
}
} else {
// insert move from register to stack just after the beginning of the interval
assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
if (!has_new) {
// prepare insertion buffer (appended when all instructions of the block are processed)
has_new = true;
}
TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
}
}
} // end of instruction iteration
if (has_new) {
}
} // end of block iteration
}
// ********** Phase 1: number all instructions in all blocks
// Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
{
// dummy-timer to measure the cost of the timer itself
// (this time is then subtracted from all other timers to get the real value)
}
// Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
int num_instructions = 0;
int i;
for (i = 0; i < num_blocks; i++) {
}
// initialize with correct length
int op_id = 0;
int idx = 0;
for (i = 0; i < num_blocks; i++) {
for (int j = 0; j < num_inst; j++) {
idx++;
}
}
}
// ********** Phase 2: compute local live sets separately for each block
// (sets live_gen and live_kill for each block)
// check some asumptions about debug information
assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
}
}
}
bool local_has_fpu_registers = false;
int local_num_calls = 0;
// iterate all blocks
for (int i = 0; i < num_blocks; i++) {
// Phi functions at the begin of an exception handler are
// implicitly defined (= killed) at the beginning of the block.
);
}
// iterate all instructions of the block. skip the first because it is always a label
for (int j = 1; j < num_inst; j++) {
// visit operation to collect all operands
}
if (visitor.info_count() > 0) {
}
// iterate input operands of instruction
int k, n, reg;
for (k = 0; k < n; k++) {
if (opr->is_virtual_register()) {
assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id()));
}
if (block->loop_index() >= 0) {
}
}
#ifdef ASSERT
// fixed intervals are never live at block boundaries, so
// they need not be processed in live sets.
// this is checked by these assertions to be sure about it.
// the entry block may have incoming values in registers, which is ok.
if (is_processed_reg_num(reg)) {
}
}
}
#endif
}
// Add uses of live locals from interpreter's point of view for proper debug information generation
n = visitor.info_count();
for (k = 0; k < n; k++) {
);
}
// iterate temp operands of instruction
for (k = 0; k < n; k++) {
if (opr->is_virtual_register()) {
assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
if (block->loop_index() >= 0) {
}
}
#ifdef ASSERT
// fixed intervals are never live at block boundaries, so
// they need not be processed in live sets
// process them only in debug mode so that this can be checked
if (!opr->is_virtual_register()) {
if (is_processed_reg_num(reg)) {
}
}
}
#endif
}
// iterate output operands of instruction
for (k = 0; k < n; k++) {
if (opr->is_virtual_register()) {
assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
if (block->loop_index() >= 0) {
}
}
#ifdef ASSERT
// fixed intervals are never live at block boundaries, so
// they need not be processed in live sets
// process them only in debug mode so that this can be checked
if (!opr->is_virtual_register()) {
if (is_processed_reg_num(reg)) {
}
}
}
#endif
}
} // end of instruction iteration
TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen()));
TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
} // end of block iteration
// propagate local calculated information into LinearScan object
}
// ********** Phase 3: perform a backward dataflow analysis to compute global live sets
// (sets live_in and live_out for each block)
bool change_occurred;
bool change_occurred_in_block;
int iteration_count = 0;
// Perform a backward dataflow analysis to compute live_out and live_in for each block.
// The loop is executed until a fixpoint is reached (no changes in an iteration)
// Exception handlers must be processed because not all live values are
// present in the state array, e.g. because of global value numbering
do {
change_occurred = false;
// iterate all blocks in reverse order
for (int i = num_blocks - 1; i >= 0; i--) {
change_occurred_in_block = false;
// live_out(block) is the union of live_in(sux), for successors sux of block
int n = block->number_of_sux();
int e = block->number_of_exception_handlers();
if (n + e > 0) {
// block has successors
if (n > 0) {
for (int j = 1; j < n; j++) {
}
} else {
}
for (int j = 0; j < e; j++) {
}
// A change occurred. Swap the old and new live out sets to avoid copying.
change_occurred = true;
change_occurred_in_block = true;
}
}
if (iteration_count == 0 || change_occurred_in_block) {
// live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
// note: live_in has to be computed only in first iteration or if live_out has changed!
}
#ifndef PRODUCT
if (TraceLinearScanLevel >= 4) {
char c = ' ';
if (iteration_count == 0 || change_occurred_in_block) {
c = '*';
}
tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
}
#endif
}
BAILOUT("too many iterations in compute_global_live_sets");
}
} while (change_occurred);
#ifdef ASSERT
// check that fixed intervals are not live at block boundaries
// (live set must be empty at fixed intervals)
for (int i = 0; i < num_blocks; i++) {
for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
}
}
#endif
// check that the live_in set of the first block is empty
#ifdef ASSERT
tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
// print some additional information to simplify debugging
tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
for (int j = 0; j < num_blocks; j++) {
}
}
}
}
}
#endif
// when this fails, virtual registers are used before they are defined.
assert(false, "live_in set of first block must be empty");
// bailout of if this occurs in product mode.
bailout("live_in set of first block not empty");
}
}
// ********** Phase 4: build intervals
// (fills the list _intervals)
assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
}
}
TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
if (opr->is_virtual_register()) {
assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
} else {
if (is_processed_reg_num(reg)) {
}
}
}
}
TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
if (opr->is_virtual_register()) {
assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
} else {
if (is_processed_reg_num(reg)) {
}
}
}
}
TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
if (opr->is_virtual_register()) {
assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
} else {
if (is_processed_reg_num(reg)) {
}
}
}
}
}
// Update the starting point (when a range is first created for a use, its
// start is the beginning of the current block until a def is encountered.)
} else {
// Dead value - make vacuous interval
// also add use_kind for dead intervals
TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
}
} else {
// Dead value - make vacuous interval
// also add use_kind for dead intervals
}
TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
}
// detection of method-parameters and roundfp-results
// TODO: move this directly to position where use-kind is computed
}
}
}
}
}
}
}
}
// the results of this functions are used for optimizing spilling and reloading
// if the functions return shouldHaveRegister and the interval is spilled,
// it is not reloaded to a register.
bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
if (result_in_memory) {
// Begin of an interval with must_start_in_memory set.
// This interval will always get a stack slot first, so return noUse.
return noUse;
// method argument (condition must be equal to handle_method_arguments)
return noUse;
// Move from register to register
// special handling of phi-function moves inside osr-entry blocks
// input operand must have a register instead of output operand (leads to better register allocation)
return shouldHaveRegister;
}
}
}
if (opr->is_virtual() &&
// result is a stack-slot, so prevent immediate reloading
return noUse;
}
// all other operands require a register
return mustHaveRegister;
}
bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
if (result_in_memory) {
// Move to an interval with must_start_in_memory set.
// To avoid moves from stack to stack (not allowed) force the input operand to a register
return mustHaveRegister;
// Move from register to register
// special handling of phi-function moves inside osr-entry blocks
// input operand must have a register instead of output operand (leads to better register allocation)
return mustHaveRegister;
}
// The input operand is not forced to a register (moves from stack to register are allowed),
// but it is faster if the input operand is in a register
return shouldHaveRegister;
}
}
#ifdef X86
// conditional moves can handle stack operands
return shouldHaveRegister;
}
// optimizations for second input operand of arithmehtic operations on Intel
// this operand is allowed to be on the stack in some cases
// SSE float instruction (T_DOUBLE only supported with SSE2)
case lir_cmp:
case lir_add:
case lir_sub:
case lir_mul:
case lir_div:
{
assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
return shouldHaveRegister;
}
}
}
} else {
// FPU stack float instruction
case lir_add:
case lir_sub:
case lir_mul:
case lir_div:
{
assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
return shouldHaveRegister;
}
}
}
}
// integer instruction (note: long operands must always be in register)
case lir_cmp:
case lir_add:
case lir_sub:
case lir_logic_and:
case lir_logic_or:
case lir_logic_xor:
{
assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
return shouldHaveRegister;
}
}
}
}
#endif // X86
// all other operands require a register
return mustHaveRegister;
}
// special handling for method arguments (moves from stack to virtual register):
// the interval gets no register assigned, but the stack slot.
// it is split before the first use by the register allocator.
#ifdef ASSERT
if (o->is_single_stack()) {
} else if (o->is_double_stack()) {
} else {
}
assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
#endif
int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
}
}
}
// special handling for doubleword move from memory to register:
// in this case the registers of the input address and the result
// registers must not overlap -> add a temp range for the input registers
}
}
}
}
}
}
case lir_move: // fall through
case lir_convert: {
TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
}
}
break;
}
case lir_cmove: {
TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
}
}
break;
}
}
}
// initialize interval list with expected number of intervals
// (32 is added to have some space for split children without having to resize the list)
// initialize all slots that are used by build_intervals
// create a list with all caller-save registers (cpu, fpu, xmm)
// when an instruction is a call, a temp range is created for all these registers
int num_caller_save_registers = 0;
int i;
for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
}
// temp ranges for fpu registers are only created when the method has
// virtual fpu operands. Otherwise no allocation for fpu registers is
// perfomed and so the temp ranges would be useless
if (has_fpu_registers()) {
#ifdef X86
if (UseSSE < 2) {
#endif
for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
}
#ifdef X86
}
if (UseSSE > 0) {
for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) {
}
}
#endif
}
// iterate all blocks in reverse order
for (i = block_count() - 1; i >= 0; i--) {
// Update intervals for registers live at the end of this block;
for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
// add special use positions for loop-end blocks when the
// interval is used anywhere inside this loop. It's possible
// that the block was part of a non-natural loop, so it might
// have an invalid loop index.
}
}
// iterate all instructions of the block in reverse order.
// skip the first instruction because it is always a label
// definitions of intervals are processed before uses
// visit operation to collect all operands
// add a temp range for each register if operation destroys caller-save registers
for (int k = 0; k < num_caller_save_registers; k++) {
}
}
// Add any platform dependent temps
// visit definitions (output and temp operands)
int k, n;
for (k = 0; k < n; k++) {
}
for (k = 0; k < n; k++) {
}
// visit uses (input operands)
for (k = 0; k < n; k++) {
}
// Add uses of live locals from interpreter's point of view for proper
// debug information generation
// Treat these operands as temp values (if the life range is extended
// to a call site, the value would be in a register at the call otherwise)
n = visitor.info_count();
for (k = 0; k < n; k++) {
);
}
// special steps for some instructions (especially moves)
} // end of instruction iteration
} // end of block iteration
// add the range [0, 1[ to all fixed intervals
// -> the register allocator need not handle unhandled fixed intervals
for (int n = 0; n < LinearScan::nof_regs; n++) {
}
}
}
// ********** Phase 5: actual register allocation
if (*a != NULL) {
if (*b != NULL) {
} else {
return -1;
}
} else {
if (*b != NULL) {
return 1;
} else {
return 0;
}
}
}
#ifndef PRODUCT
int i, j;
assert(false, "");
return false;
}
}
}
// check in both directions if sorted list and unsorted list contain same intervals
for (i = 0; i < interval_count(); i++) {
if (interval_at(i) != NULL) {
int num_found = 0;
num_found++;
}
}
}
}
int num_found = 0;
for (i = 0; i < interval_count(); i++) {
num_found++;
}
}
}
return true;
}
#endif
} else {
}
}
void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
Interval* v;
const int n = _sorted_intervals->length();
for (int i = 0; i < n; i++) {
v = _sorted_intervals->at(i);
if (v == NULL) continue;
if (is_list1(v)) {
}
}
assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
}
if (_needs_full_resort) {
// There is no known reason why this should occur but just in case...
assert(false, "should never occur");
// Re-sort existing interval list because an Interval::from() has changed
_needs_full_resort = false;
}
int sorted_len = 0;
int unsorted_idx;
int sorted_idx = 0;
// calc number of items for sorted list (sorted list must not contain NULL values)
sorted_len++;
}
}
// special sorting algorithm: the original interval-list is almost sorted,
// only some intervals are swapped. So this is much faster than a complete QuickSort
if (cur_interval != NULL) {
if (sorted_from_max <= cur_from) {
} else {
// the asumption that the intervals are already sorted failed,
// so this interval must be sorted in manually
int j;
}
sorted_idx++;
}
}
}
}
if (_needs_full_resort) {
// Re-sort existing interval list because an Interval::from() has changed
_needs_full_resort = false;
}
if (new_len == 0) {
// no intervals have been added during allocation, so sorted list is already up to date
return;
}
// conventional sort-algorithm for new intervals
// merge old and new list (both already sorted) into one combined list
int old_idx = 0;
int new_idx = 0;
if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
old_idx++;
} else {
new_idx++;
}
}
}
create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, is_precolored_cpu_interval, is_virtual_cpu_interval);
if (has_fpu_registers()) {
create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
#ifdef ASSERT
} else {
// fpu register allocation is omitted because no virtual fpu registers are present
// just check this again...
create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, is_precolored_fpu_interval, is_virtual_fpu_interval);
#endif
}
// allocate cpu registers
if (has_fpu_registers()) {
// allocate fpu registers
}
}
// ********** Phase 6: resolve data flow
// (insert moves at edges between blocks if intervals have been split)
// wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
// instead of returning NULL
Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
return result;
}
assert(false, "must find an interval, but do a clean bailout in product mode");
result->assign_reg(0);
}
assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
}
assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
}
assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
}
void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
// visit all registers where the live_at_edge bit is set
for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
// need to insert move instruction
}
}
}
void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
// insert moves before branch
} else {
}
} else {
TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
#ifdef ASSERT
assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
// because the number of predecessor edges matches the number of
// successor edges, blocks which are reached by switch statements
// may have be more than one predecessor but it will be guaranteed
// that all predecessors will be the same.
for (int i = 0; i < to_block->number_of_preds(); i++) {
}
#endif
}
}
// insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
MoveResolver move_resolver(this);
int i;
for (i = 0; i < num_blocks; i++) {
// check if block has only one predecessor and only one successor
if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
// check if block is empty (only label and branch)
// prevent optimization of two consecutive blocks
if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
// directly resolve between pred and sux (without looking at the empty block between)
if (move_resolver.has_mappings()) {
}
}
}
}
}
for (i = 0; i < num_blocks; i++) {
if (!block_completed.at(i)) {
for (int s = 0; s < num_sux; s++) {
// check for duplicate edges between the same blocks (can happen with switch blocks)
TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
// collect all intervals that have been split between from_block and to_block
if (move_resolver.has_mappings()) {
}
}
}
}
}
}
void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
// if a phi function is never used, no interval is created -> ignore this
return;
}
// the interval is split to get a short range that is located on the stack
// in the following two cases:
// * the interval started in memory (e.g. method parameter), but is currently in a register
// this is an optimization for exception handling that reduces the number of moves that
// are necessary for resolving the states when an exception uses this exception handler
// * the interval would be on the fpu stack at the begin of the exception handler
// this is not allowed because of the complicated fpu stack handling on Intel
// range that will be spilled to memory
"no split allowed between exception entry and first instruction");
// the part before from_op_id is unchanged
} else {
_needs_full_resort = true;
}
// the part after to_op_id is unchanged
}
}
}
// visit all registers where the live_in bit is set
for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
}
// the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
);
if (move_resolver.has_mappings()) {
// insert moves after first instruction
}
}
void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
// if a phi function is never used, no interval is created -> ignore this
return;
}
// the computation of to_interval is equal to resolve_collect_mappings,
// but from_interval is more complicated because of phi functions
// phi function of the exception entry block
// no moves are created for this phi function in the LIR_Generator, so the
// interval at the throwing instruction must be searched using the operands
// of the phi function
// with phi functions it can happen that the same from_value is used in
// multiple mappings, so notify move-resolver that this is allowed
// unpinned constants may have no register, so add mapping from constant to interval
} else {
// search split child at the throwing op_id
}
} else {
// no phi function, so use reg_num also for from_interval
// search split child at the throwing op_id
if (from_interval != to_interval) {
// optimization to reduce number of moves: when to_interval is on stack and
// the stack slot is known to be always correct, then no move is necessary
if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
}
}
}
}
void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
// visit all registers where the live_in bit is set
for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
}
// the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
);
if (move_resolver.has_mappings()) {
}
}
MoveResolver move_resolver(this);
int i;
for (i = 0; i < num_blocks; i++) {
}
}
for (i = 0; i < num_blocks; i++) {
// iterate all instructions of the block. skip the first because it is always a label
for (int j = 1; j < num_ops; j++) {
// visit operation to collect all operands
for (int k = 0; k < n; k++) {
}
#ifdef ASSERT
} else {
#endif
}
}
}
}
// ********** Phase 7: assign register numbers back to LIR
// (includes computation of debug information and oop maps)
}
return reg;
}
}
if (opr->is_illegal()) {
}
return opr;
}
if (assigned_reg >= nof_regs) {
// stack slot
} else {
// register
switch (type) {
case T_OBJECT: {
}
case T_ADDRESS: {
}
#ifdef __SOFTFP__
case T_FLOAT: // fall through
#endif // __SOFTFP__
case T_INT: {
}
#ifdef __SOFTFP__
case T_DOUBLE: // fall through
#endif // __SOFTFP__
case T_LONG: {
"register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
if (requires_adjacent_regs(T_LONG)) {
}
#ifdef _LP64
#else
#else
#endif // SPARC
#endif // LP64
}
#ifndef __SOFTFP__
case T_FLOAT: {
#ifdef X86
if (UseSSE >= 1) {
}
#endif
}
case T_DOUBLE: {
#ifdef X86
if (UseSSE >= 2) {
assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
}
#endif
#ifdef SPARC
assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
#else
assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
#endif
return result;
}
#endif // __SOFTFP__
default: {
return LIR_OprFact::illegalOpr;
}
}
}
}
}
if (op_id != -1) {
#ifdef ASSERT
// check if spill moves could have been appended at the end of this block, but
// before the branch instruction. So the split child information for this branch would
// be incorrect.
assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
}
}
}
#endif
// operands are not changed when an interval is split during allocation,
// so search the right interval here
}
#ifdef X86
// new semantic for is_last_use: not only set on definite end of interval,
// but also before hole
// This may still miss some cases (e.g. for dead values), but it is not necessary that the
// last use information is completely correct
// information is only needed for fpu stack allocation
if (res->is_fpu_register()) {
if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
}
}
#endif
assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
return res;
}
#ifdef ASSERT
// some methods used to check correctness of debug information
return;
}
if (value->is_location()) {
}
}
}
return;
}
}
}
}
}
if (v1->is_location()) {
} else if (v1->is_constant_int()) {
} else if (v1->is_constant_double()) {
} else if (v1->is_constant_long()) {
} else if (v1->is_constant_oop()) {
} else {
}
}
}
}
} else {
}
}
} else {
}
}
} else {
}
} else {
}
}
switch (code) {
case Bytecodes::_if_acmpne :
assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
break;
}
}
}
#endif // ASSERT
// setup lists of potential oops for walking
// intervals that have no oops inside need not to be processed
// to ensure a walking until the last instruction id, add a dummy interval
// with a high operation id
}
OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
// walk before the current operation -> intervals that start at
// the operation (= output operands of the operation) are not
// included in the oop map
// Check if this is a patch site.
bool is_patch_info = false;
}
// Iterate through active intervals
for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
// Check if this range covers the instruction. Intervals that
// start or end at the current operation are not included in the
// oop map, except in the case of patching moves. For patching
// moves, any intervals which end at this instruction are included
// in the oop map since we may safepoint while doing the patch
// before we've consumed the inputs.
// caller-save registers must not be included into oop-maps at calls
assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
// Spill optimization: when the stack value is guaranteed to be always correct,
// then it must be added to the oop map even if the interval is currently in a register
if (interval->always_in_memory() &&
assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
}
}
}
// add oops from lock stack
for (int i = 0; i < locks_count; i++) {
}
return map;
}
// compute oop_map only for first CodeEmitInfo
// because it is (in most cases) equal for all other infos of the same operation
for (int i = 0; i < visitor.info_count(); i++) {
// this info has a different number of locks then the precomputed oop map
// (possible for lock and unlock instructions) -> compute oop map with
// correct lock information
}
} else {
// a CodeEmitInfo can not be shared between different LIR-instructions
// because interval splitting can occur anywhere between two instructions
// and so the oop maps must be different
// -> check if the already set oop_map is exactly the one calculated for this operation
}
}
}
// frequently used constants
// Allocate them with new so they are never destroyed (otherwise, a
// forced exit could destroy these objects while they are still in
// use).
ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
ConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
ConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0);
ConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
ConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
// cache for frequently used scope values
// (cpu registers and stack slots)
_scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
}
bailout("too large frame");
}
bailout("too large frame");
}
}
bailout("too large frame");
}
return new LocationValue(loc);
}
int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
switch (t) {
case T_OBJECT: {
} else {
}
return 1;
}
case T_INT: // fall through
case T_FLOAT: {
switch (value) {
}
return 1;
}
case T_LONG: // fall through
case T_DOUBLE: {
#ifdef _LP64
#else
} else {
}
#endif
return 2;
}
case T_ADDRESS: {
#ifdef _LP64
#else
#endif
return 1;
}
default:
return -1;
}
}
int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
if (opr->is_single_stack()) {
}
// check if cached value is correct
DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
return 1;
} else if (opr->is_single_cpu()) {
}
// check if cached value is correct
DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
return 1;
#ifdef X86
} else if (opr->is_single_xmm()) {
return 1;
#endif
} else if (opr->is_single_fpu()) {
#ifdef X86
// the exact location of fpu stack values is only known
// during fpu stack allocation, so the stack allocator object
// must be present
assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
#endif
#ifndef __SOFTFP__
#ifndef VM_LITTLE_ENDIAN
if (! float_saved_as_double) {
// On big endian system, we may have an issue if float registers use only
// the low half of the (same) double registers.
// Both the float and the double could have the same regnr but would correspond
// to two different addresses once saved.
// get next safely (no assertion checks)
// the back-end does use the same numbering for the double and the float
}
}
#endif
#endif
return 1;
} else {
// double-size operands
if (opr->is_double_stack()) {
#ifdef _LP64
bailout("too large frame");
}
// Does this reverse on x86 vs. sparc?
#else
bailout("too large frame");
}
#endif // _LP64
} else if (opr->is_double_cpu()) {
#ifdef _LP64
#else
rname_second = tmp;
}
#endif //_LP64
#ifdef X86
} else if (opr->is_double_xmm()) {
# ifdef _LP64
# else
// %%% This is probably a waste but we'll keep things as they were for now
if (true) {
}
# endif
#endif
} else if (opr->is_double_fpu()) {
// On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
// the double as float registers in the native ordering. On X86,
// fpu_regnrLo is a FPU stack slot whose VMReg represents
// the low-order word of the double and fpu_regnrLo + 1 is the
// name for the other half. *first and *second must represent the
// least and most significant words, respectively.
#ifdef X86
// the exact location of fpu stack values is only known
// during fpu stack allocation, so the stack allocator object
// must be present
assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
#endif
#ifdef SPARC
assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
#endif
#ifdef ARM
assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
#endif
#ifdef PPC
assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
#endif
#ifdef VM_LITTLE_ENDIAN
#else
#endif
#ifdef _LP64
#else
// %%% This is probably a waste but we'll keep things as they were for now
if (true) {
}
#endif
} else {
}
// The convention the interpreter uses is that the second local
// holds the first raw word of the native double representation.
// This is actually reasonable, since locals and stack arrays
// grow downwards in all implementations.
// (If, on some machine, the interpreter's Java locals or stack
// were to grow upwards, the embedded doubles would be word-swapped.)
return 2;
}
}
int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
// Unpinned constants may have a virtual operand for a part of the lifetime
// or may be illegal when it was optimized away,
// so always use a constant operand
}
if (opr->is_virtual()) {
// generating debug information for the last instruction of a block.
// if this instruction is a branch, spill moves are inserted before this branch
// and so the wrong operand would be returned (spill moves at block boundaries are not
// considered in the live ranges of intervals)
// Solution: use the first op_id of the branch target block instead.
}
}
}
// Get current location of operand
// The operand must be live because debug information is considered when building the intervals
// if the interval is not live, color_lir_opr will cause an assertion failure
assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
// Append to ScopeValue array
} else {
}
} else {
// append a dummy value because real value not needed
return 1;
}
}
IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
if (caller_state != NULL) {
// process recursively to compute outermost scope first
caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
}
// initialize these to null.
// If we don't need deopt info or there are no locals, expressions or monitors,
// then these get recorded as no information and avoids the allocation of 0 length arrays.
// describe local variable values
if (nof_locals > 0) {
int pos = 0;
while (pos < nof_locals) {
}
for(int i = 0; i < nof_locals; i++) {
}
}
// describe expression stack
if (nof_stack > 0) {
int pos = 0;
}
}
// describe monitors
if (nof_locks > 0) {
int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
for (int i = 0; i < nof_locks; i++) {
}
}
return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
}
// compute debug information
info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
} else {
// debug information already set. Check that it is correct from the current point of view
DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
}
}
bool has_dead = false;
for (int j = 0; j < num_inst; j++) {
has_dead = true;
continue;
}
// visit instruction to get list of operands
// iterate all modes of the visitor and process all virtual operands
for (int k = 0; k < n; k++) {
if (opr->is_virtual_register()) {
}
}
}
if (visitor.info_count() > 0) {
// exception handling
if (compilation()->has_exception_handlers()) {
for (int k = 0; k < n; k++) {
}
}
} else {
}
// compute oop map
// compute debug information
if (!use_fpu_stack_allocation()) {
// compute debug information if fpu stack allocation is not needed.
// when fpu stack allocation is needed, the debug information can not
// be computed here because the exact location of fpu operands is not known
// -> debug information is created inside the fpu stack allocator
int n = visitor.info_count();
for (int k = 0; k < n; k++) {
}
}
}
#ifdef ASSERT
// make sure we haven't made the op invalid.
#endif
// remove useless moves
has_dead = true;
}
}
}
if (has_dead) {
// iterate all instructions of the block and remove all null-values.
int insert_point = 0;
for (int j = 0; j < num_inst; j++) {
if (insert_point != j) {
}
insert_point++;
}
}
}
}
for (int i = 0; i < num_blocks; i++) {
}
}
if (compilation()->has_exception_handlers()) {
}
// fill in number of spill slots into frame_map
DEBUG_ONLY(verify());
if (use_fpu_stack_allocation()) {
allocate_fpu_stack(); // Only has effect on Intel
}
}
// check that cfg is still correct after optimizations
}
}
// ********** Printing functions
#ifndef PRODUCT
}
}
for (unsigned int i = 0; i < b.size(); i++) {
}
}
if (TraceLinearScanLevel >= 1) {
int i;
for (i = 0; i < interval_count(); i++) {
}
}
for (i = 0; i < block_count(); i++) {
tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
}
}
if (PrintCFGToFile) {
}
}
if (TraceLinearScanLevel >= level) {
}
}
}
#endif //PRODUCT
// ********** verification functions for allocation
// (check that all intervals have a correct register and that no registers are overwritten)
#ifdef ASSERT
TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
}
bool has_error = false;
for (int i = 0; i < len; i++) {
has_error = true;
}
has_error = true;
}
has_error = true;
}
has_error = true;
}
has_error = true;
}
has_error = true;
}
has_error = true;
}
}
for (int j = i + 1; j < len; j++) {
// special intervals that are created in MoveResolver
// -> ignore them because the range information has no meaning there
if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
has_error = true;
}
}
}
}
// to ensure a walking until the last instruction id, add a dummy interval
// with a high operation id
for (int i = 0; i < block_count(); i++) {
for (int j = 0; j < instructions->length(); j++) {
if (visitor.info_count() > 0) {
bool check_live = true;
}
// Don't bother checking the stub in this case since the
// exception stub will never return to normal control flow.
check_live = false;
}
// Make sure none of the fixed registers is live across an
// oopmap since we can't handle that correctly.
if (check_live) {
// This interval is live out of this op so make sure
// that this interval represents some value that's
// referenced by this op either as an input or output.
bool ok = false;
for (int k = 0; k < n; k++) {
if (opr->is_fixed_cpu()) {
ok = true;
break;
}
ok = true;
break;
}
}
}
}
}
}
}
}
// oop-maps at calls do not contain registers, so check is not needed
for (int k = 0; k < n; k++) {
// operand is a non-virtual cpu register and contains an oop
"oop input operand live after instruction");
}
"oop input operand live after instruction");
}
}
}
}
}
}
}
}
}
for (int i = 0; i < num_blocks; i++) {
// visit all registers where the live_at_edge bit is set
for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
// TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
}
}
}
private:
// simplified access to methods of LinearScan
// currently, only registers are processed
// accessors
void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
// helper functions
public:
, _work_list(16)
{ }
};
// entry function from LinearScan that starts the verification
RegisterVerifier verifier(this);
}
// setup input registers (method arguments) for first block
if (opr->is_register()) {
}
if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
}
}
}
// main loop for verification
do {
_work_list.remove_at(0);
} while (!_work_list.is_empty());
}
// must copy state because it is modified
if (TraceLinearScanLevel >= 4) {
for (int i = 0; i < state_size(); i++) {
} else {
}
}
}
// process all operations of the block
// iterate all successors
for (int i = 0; i < block->number_of_sux(); i++) {
}
}
// must copy state because it is modified
}
}
if (saved_state != NULL) {
// this block was already processed before.
// check if new input_state is consistent with saved_state
bool saved_state_correct = true;
for (int i = 0; i < state_size(); i++) {
// current input_state and previous saved_state assume a different
// interval in this register -> assume that this register is invalid
// invalidate old calculation only if it assumed that
// register was valid. when the register was already invalid,
// then the old calculation was correct.
saved_state_correct = false;
TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
}
}
}
if (saved_state_correct) {
// already processed block with correct input_state
TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
} else {
// must re-visit this block
TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
}
} else {
// block was not processed before, so set initial input_state
}
}
return copy_state;
}
}
}
}
tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
return true;
}
}
return false;
}
// visit all instructions of the block
bool has_error = false;
// check if input operands are correct
int j;
for (j = 0; j < n; j++) {
}
// When an operand is marked with is_last_use, then the fpu stack allocator
// removes the register from the fpu stack -> the register contains no value
if (opr->is_last_use()) {
}
}
}
// invalidate all caller save registers at calls
for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
}
for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
}
#ifdef X86
for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) {
}
#endif
}
// process xhandler before output and temp operands
for (int k = 0; k < n; k++) {
}
// set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
for (j = 0; j < n; j++) {
}
}
}
// set output operands
for (j = 0; j < n; j++) {
}
}
}
}
}
#endif // ASSERT
// **** Implementation of MoveResolver ******************************
_multiple_reads_allowed(false),
_mapping_from(8),
_mapping_to(8),
_insert_idx(-1),
{
for (int i = 0; i < LinearScan::nof_regs; i++) {
_register_blocked[i] = 0;
}
}
#ifdef ASSERT
assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
for (int i = 0; i < LinearScan::nof_regs; i++) {
}
}
int i, j;
if (!_multiple_reads_allowed) {
for (i = 0; i < _mapping_from.length(); i++) {
assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
}
}
}
for (i = 0; i < _mapping_to.length(); i++) {
}
}
BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
if (!_multiple_reads_allowed) {
for (i = 0; i < _mapping_from.length(); i++) {
}
}
}
}
for (i = 0; i < _mapping_to.length(); i++) {
}
}
for (i = 0; i < _mapping_from.length(); i++) {
}
}
for (i = 0; i < _mapping_to.length(); i++) {
assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
}
}
#endif // ASSERT
// mark assigned_reg and assigned_regHi of the interval as blocked
}
}
}
// mark assigned_reg and assigned_regHi of the interval as unblocked
}
}
}
// check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
}
if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
return false;
}
}
if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
return false;
}
}
return true;
}
}
if (_insertion_buffer.initialized()) {
}
_insert_list = NULL;
_insert_idx = -1;
}
if (!_multiple_reads_allowed) {
// the last_use flag is an optimization for FPU stack allocation. When the same
// input interval is used in more than one move, then it is too difficult to determine
// if this move is really the last use.
}
TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
}
TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
}
TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
// Block all registers that are used as input operands of a move.
// When a register is blocked, no move to this register is emitted.
// This is necessary for detecting cycles in moves.
int i;
if (from_interval != NULL) {
}
}
while (_mapping_from.length() > 0) {
bool processed_interval = false;
// this inverval can be processed because target is free
if (from_interval != NULL) {
} else {
}
_mapping_to.remove_at(i);
processed_interval = true;
// this interval cannot be processed now because target is not free
// it starts in a register, so it is a possible candidate for spilling
spill_candidate = i;
}
}
if (!processed_interval) {
// no move could be processed because there is a cycle in the move list
// (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
// create a new spill interval and assign a stack slot to it
// add a dummy range because real position is difficult to calculate
// Note: this range is a special case when the integrity of the allocation is checked
// do not allocate a new spill slot for temporary interval, but
// use spill slot assigned to from_interval. Otherwise moves from
// one stack slot to another can happen (not allowed by LIR_Assembler
if (spill_slot < 0) {
}
TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
// insert a move from register to stack and update the mapping
}
}
// reset to default value
_multiple_reads_allowed = false;
// check that all intervals have been processed
}
TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
}
TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
// insert position changed -> resolve current mappings
}
if (insert_list != _insert_list) {
// block changed -> append insertion_buffer because it is
// bound to a specific block and create a new insertion_buffer
}
}
TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
}
TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
}
if (has_mappings()) {
}
}
// **** Implementation of Range *************************************
{
}
// initialize sentinel
}
do {
} else {
}
} else {
}
} else { // r1->from() == r2->from()
} else {
}
}
} while (true);
}
#ifndef PRODUCT
}
#endif
// **** Implementation of Interval **********************************
// initialize sentinel
}
_use_pos_and_kinds(12),
_cached_to(-1),
_split_children(0),
_insert_move_when_activated(false),
{
_split_parent = this;
_current_split_child = this;
}
r = r->next();
}
return r->to();
}
#ifdef ASSERT
// consistency check of split-children
if (_split_children.length() > 0) {
for (int i = 0; i < _split_children.length(); i++) {
assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
} else {
}
}
}
}
}
#endif // ASSERT
if (!search_split_child) {
return _register_hint;
}
if (_register_hint != NULL) {
return _register_hint;
// search the first split child that has a register assigned
for (int i = 0; i < len; i++) {
return cur;
}
}
}
}
// no hint interval found that has a register assigned
return NULL;
}
if (_split_children.length() == 0) {
result = this;
} else {
// in outputMode, the end of the interval (op_id == cur->to()) is not valid
int i;
for (i = 0; i < len; i++) {
if (i > 0) {
// exchange current split child to start of list (faster access for next call)
}
// interval found
break;
}
}
#ifdef ASSERT
for (i = 0; i < len; i++) {
tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
assert(false, "two valid result intervals found");
}
}
#endif
}
return result;
}
// returns the last split child that ends before the given op_id
for (int i = len - 1; i >= 0; i--) {
}
}
return result;
}
// checks if op_id is covered by any split child
if (_split_children.length() == 0) {
// simple case if interval was not split
} else {
// extended case: check all split children
for (int i = 0; i < len; i++) {
return true;
}
}
return false;
}
}
// Note: use positions are sorted descending -> first use has highest index
return _use_pos_and_kinds.at(i);
}
}
return max_jint;
}
return _use_pos_and_kinds.at(i);
}
}
return max_jint;
}
return _use_pos_and_kinds.at(i);
}
}
return max_jint;
}
int prev = 0;
return prev;
}
}
}
return prev;
}
// do not add use positions for precolored intervals because
// they are never used
#ifdef ASSERT
assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
if (i > 0) {
}
}
#endif
// Note: add_use is called in descending order, so list gets sorted
// automatically by just appending new use positions
}
}
}
assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
// join intersecting ranges
} else {
// insert new range
}
}
// allocate new interval
// insert new interval in children-list of parent
}
return result;
}
// split this interval at the specified position and return
// the remainder as a new interval.
//
// when an interval is split, a bi-directional link is established between the original interval
// (the split parent) and the intervals that are split off this interval (the split children)
// When a split child is split again, the new created interval is also a direct child
// of the original parent (there is no tree of split children stored, but a flat list)
// All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
//
// Note: The new interval has no valid reg_num
// allocate new interval
// split the ranges
}
} else {
}
// split list of use positions
start_idx -= 2;
}
int i;
}
#ifdef ASSERT
assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
}
assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
}
#endif
return result;
}
// split this interval at the specified position and return
// the head as a new interval (the original interval is the tail)
//
// Currently, only the first range can be split, and the new interval
// must not have split positions
assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
// allocate new interval
// the new created interval has only one range (checked by assertion above),
// so the splitting of the ranges is very simple
} else {
}
return result;
}
// returns true if the op_id is inside the interval
}
} else {
}
}
return false;
}
// returns true if the interval has any hole between hole_from and hole_to
// (even if the hole has only the length 1)
// hole-range starts before this range -> hole
return true;
// hole-range completely inside this range -> no hole
return false;
// overlapping of hole-range with this range -> hole
return true;
}
}
return false;
}
#ifndef PRODUCT
const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
const char* type_name;
type_name = "fixed";
// need a temporary operand for fixed intervals because type() cannot be called
#ifdef X86
#endif
} else {
}
} else {
if (assigned_reg() != -1 &&
}
}
}
out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
// print ranges
}
// print use positions
int prev = 0;
assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
}
}
#endif
// **** Implementation of IntervalWalker ****************************
IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
{
_current_position = -1;
}
// append interval at top of list
}
// append interval in order of current range from()
}
} else {
}
}
assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
}
} else {
}
}
}
return true;
} else {
return false;
}
}
bool deleted;
if (i->state() == activeState) {
} else {
}
}
bool range_has_changed = false;
cur->next_range();
range_has_changed = true;
}
// also handle move from inactive list to active list
if (range_has_changed) {
// remove cur from list
if (cur->current_at_end()) {
// move to handled state (not maintained as a list)
// sort into active list
}
} else {
// sort into inactive list
}
}
} else {
continue;
}
}
}
}
void IntervalWalker::next_interval() {
// intervals may start at same position -> prefer fixed interval
assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
} else {
}
_current->rewind_range();
}
TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
// set _current_position prior to call of walk_to
// call walk_to even if _current_position == id
if (is_active) {
if (activate_current()) {
}
} else {
return;
}
}
}
void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
#ifndef PRODUCT
if (TraceLinearScanLevel >= 4) {
#define print_state(state) \
switch(state) {\
default: ShouldNotReachHere(); \
}
}
#endif
}
// **** Implementation of LinearScanWalker **************************
LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
{
for (int i = 0; i < LinearScan::nof_regs; i++) {
}
}
for (int i = _first_reg; i <= _last_reg; i++) {
if (!only_process_use_pos) {
_block_pos[i] = max_jint;
_spill_intervals[i]->clear();
}
}
}
assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
}
}
exclude_from_use(i->assigned_reg());
exclude_from_use(i->assigned_regHi());
}
inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
}
if (!only_process_use_pos) {
}
}
}
if (use_pos != -1) {
}
}
}
}
}
}
if (block_pos != -1) {
}
}
void LinearScanWalker::free_exclude_active_fixed() {
assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
}
}
void LinearScanWalker::free_exclude_active_any() {
}
}
} else {
}
}
}
}
}
}
}
}
void LinearScanWalker::spill_exclude_active_fixed() {
}
}
}
}
} else {
}
}
}
void LinearScanWalker::spill_collect_active_any() {
}
}
}
}
}
// output all moves here. When source and target are equal, the move is
// optimized away later in assign_reg_nums
assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
// calculate index of instruction inside instruction list of current block
// the minimal index (for a block with no spill moves) can be calculated because the
// numbering of instructions is known.
// When the block already contains spill moves, the index must be increased until the
// correct index is reached.
index++;
}
// insert new instruction before instruction at position index
}
int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
// Try to split at end of max_block. If this would be after
// max_split_pos, then use the begin of max_block
if (optimal_split_pos > max_split_pos) {
}
// block with lower loop-depth found -> split at the end of this block
}
}
assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
return optimal_split_pos;
}
int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
int optimal_split_pos = -1;
if (min_split_pos == max_split_pos) {
// trivial case, no optimization of split position possible
} else {
// reason for using min_split_pos - 1: when the minimal split pos is exactly at the
// beginning of a block, then min_split_pos is also a possible split position.
// Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
// reason for using max_split_pos - 1: otherwise there would be an assertion failure
// when an interval ends at the end of the last block of the method
// (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
// block at this op_id)
// split position cannot be moved to block boundary, so split as late as possible
TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block"));
} else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
// Do not move split position if the interval has a hole before max_split_pos.
// Intervals resulting from Phi-Functions have more than one definition (marked
// as mustHaveRegister) with a hole before each definition. When the register is needed
// for the second definition, an earlier reloading is unnecessary.
TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos"));
} else {
// seach optimal block boundary between min_split_pos and max_split_pos
TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
if (do_loop_optimization) {
// Loop optimization: if a loop-end marker is found between min- and max-position,
// then split before this loop
if (loop_end_pos < max_split_pos) {
// loop-end marker found between min- and max-position
// if it is not the end marker for the same loop as the min-position, then move
// the max-position to this loop block.
// Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
// of the interval (normally, only mustHaveRegister causes a reloading)
TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
optimal_split_pos = -1;
} else {
}
}
}
if (optimal_split_pos == -1) {
// not calculated by loop optimization
}
}
}
return optimal_split_pos;
}
/*
split an interval at the optimal position between min_split_pos and
max_split_pos in two parts:
1) the left part has already a location assigned
2) the right part is sorted into to the unhandled-list
*/
// the split position would be just before the end of the interval
// -> no split at all necessary
TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval"));
return;
}
// must calculate this before the actual split is performed and before split position is moved to odd op_id
bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
// move position before actual instruction (odd op_id)
}
assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary));
}
/*
split an interval at the optimal position between min_split_pos and
max_split_pos in two parts:
1) the left part has already a location assigned
2) the right part is always on the stack and therefore ignored in further processing
*/
// calculate allowed range of splitting position
int max_split_pos = current_position();
// the whole interval is never used, so spill it entirely to memory
TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval"));
assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
// Also kick parent intervals out of register to memory when they have no use
// position. This avoids short interval in register surrounded by intervals in
// memory -> avoid useless moves from memory to register and back
// parent is never used, so kick it out of its assigned register
TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num()));
} else {
// do not go further back because the register is actually used by the interval
}
}
}
} else {
// search optimal split pos, split interval and spill only the right hand part
// move position before actual instruction (odd op_id)
}
assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
}
// the current_split_child is needed later when moves are inserted for reloading
}
}
}
void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
}
int current_pos = current_position();
// the interval is currently inactive, so no spill slot is needed for now.
// when the split part is activated, the interval has a new chance to get a register,
// so in the best case no stack slot is necessary
assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
} else {
// search the position where the interval must have a register and split
// at the optimal position before.
// The new created part is added to the unhandled list and will get a register
// when it is activated
assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
}
}
int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
int min_full_reg = any_reg;
int max_partial_reg = any_reg;
for (int i = _first_reg; i <= _last_reg; i++) {
if (i == ignore_reg) {
// this register must be ignored
} else if (_use_pos[i] >= interval_to) {
// this register is free for the full interval
if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
min_full_reg = i;
}
} else if (_use_pos[i] > reg_needed_until) {
// this register is at least free until reg_needed_until
if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
max_partial_reg = i;
}
}
}
if (min_full_reg != any_reg) {
return min_full_reg;
} else if (max_partial_reg != any_reg) {
*need_split = true;
return max_partial_reg;
} else {
return any_reg;
}
}
int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
int min_full_reg = any_reg;
int max_partial_reg = any_reg;
// this register is free for the full interval
if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
min_full_reg = i;
}
// this register is at least free until reg_needed_until
if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
max_partial_reg = i;
}
}
}
if (min_full_reg != any_reg) {
return min_full_reg;
} else if (max_partial_reg != any_reg) {
*need_split = true;
return max_partial_reg;
} else {
return any_reg;
}
}
init_use_lists(true);
// free_collect_unhandled(fixedKind, cur);
assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
// _use_pos contains the start of the next interval that has this register assigned
// (either as a fixed register or a normal allocated register in the past)
// only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i]));
int hint_reg, hint_regHi;
if (register_hint != NULL) {
}
TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
} else {
}
assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
// the register must be free at least until this position
bool need_split = false;
int split_pos = -1;
if (_adjacent_regs) {
return false;
}
} else {
return false;
}
if (_num_phys_regs == 2) {
// do not split interval if only one register can be assigned until the split pos
// (when one register is found for the whole interval, split&spill is only
// performed for the hi register)
return false;
// sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
}
}
}
}
if (need_split) {
// register not available for full interval, so split it
}
// only return true if interval is completely assigned
}
int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
for (int i = _first_reg; i <= _last_reg; i++) {
if (i == ignore_reg) {
// this register must be ignored
} else if (_use_pos[i] > reg_needed_until) {
if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
max_reg = i;
}
}
}
*need_split = true;
}
return max_reg;
}
int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
max_reg = i;
}
}
}
*need_split = true;
}
return max_reg;
}
}
}
}
}
}
// Split an Interval and spill it to memory so that cur can be placed in a register
// collect current usage of registers
init_use_lists(false);
// spill_block_unhandled_fixed(cur);
assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
#ifndef PRODUCT
if (TraceLinearScanLevel >= 4) {
for (int i = _first_reg; i <= _last_reg; i++) {
for (int j = 0; j < _spill_intervals[i]->length(); j++) {
}
}
}
#endif
// the register must be free at least until this position
int split_pos = 0;
int use_pos = 0;
bool need_split = false;
if (_adjacent_regs) {
}
} else {
if (_num_phys_regs == 2) {
} else {
}
}
// sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
}
}
}
}
if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
// the first use of cur is later than the spilling position -> spill cur
TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
// assign a reasonable register and do a bailout in product mode to avoid errors
BAILOUT("LinearScan: no register found");
}
} else {
if (need_split) {
// register not available for full interval, so split it
}
// perform splitting and spilling for all affected intervalls
}
}
#ifdef X86
// fast calculation of intervals that can never get a register because the
// the next instruction is a call that blocks all registers
// Note: this does not work if callee-saved registers are available (e.g. on Sparc)
// check if this interval is the result of a split operation
// (an interval got a register until this position)
// the current instruction is a call that blocks all registers
TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call"));
// safety check that there is really no register available
return true;
}
}
#endif
return false;
}
if (pd_init_regs_for_alloc(cur)) {
// the appropriate register range was selected.
} else {
}
}
return false;
}
return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
}
// optimization (especially for phi functions of nested loops):
// assign same spill slot to non-intersecting intervals
if (cur->is_split_child()) {
// optimization is only suitable for split parents
return;
}
if (register_hint == NULL) {
// cur is not the target of a move, otherwise register_hint would be set
return;
}
// combining the stack slots for intervals where spill move optimization is applied
// is not benefitial and would cause problems
return;
}
// safety check that lir_op_with_id is allowed
return;
}
if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
// cur and register_hint are not connected with two moves
return;
}
// register_hint must be split, otherwise the re-writing of use positions does not work
return;
}
assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
// register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
return;
}
assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
// modify intervals such that cur gets the same stack slot as register_hint
// delete use positions to prevent the intervals to get a register at beginning
}
// allocate a physical register or memory location to an interval
bool LinearScanWalker::activate_current() {
bool result = true;
TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
// activating an interval that has a stack slot assigned -> split it at first use position
// used for method parameters
TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use"));
result = false;
} else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
// activating an interval that must start in a stack slot, but may get a register later
// used for lir_roundfp: rounding is done by store to stack and reload later
TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use"));
assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
result = false;
// interval has not assigned register -> normal allocation
// (this is the normal case for most intervals)
// assign same spill slot to non-intersecting intervals
// no empty register available.
// split and spill another interval so that this interval gets a register
}
// spilled intervals need not be move to active-list
result = false;
}
}
// load spilled values that become active from stack slot to register
if (cur->insert_move_when_activated()) {
assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
}
return result; // true = interval is moved to active list
}
// Implementation of EdgeMoveOptimizer
{
}
// ignore the first block in the list (index 0 is not processed)
}
}
}
}
// clear all internal data structures
void EdgeMoveOptimizer::init_instructions() {
}
// append a lir-instruction-list and the index of the current operation in to the list
}
// return the current operation of the given edge (predecessor or successor)
} else {
return NULL;
}
}
// removes the current operation of the given edge (predecessor or successor)
if (decrement_index) {
}
}
// at least one block is already empty -> no optimization possible
return true;
}
if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
// these moves are exactly equal and can be optimized
return false;
}
// equal FPU stack operations can be optimized
return false;
}
// equal FPU stack operations can be optimized
return false;
}
// no optimization possible
return true;
}
// currently we can't handle this correctly.
return;
}
// setup a list with the lir-instructions of all predecessors
int i;
for (i = 0; i < num_preds; i++) {
// this can happen with switch-statements where multiple edges are between
// the same blocks.
return;
}
assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
// can not optimize instructions when debug info is needed
return;
}
// ignore the unconditional branch at the end of the block
}
// process lir-instructions while all predecessors end with the same instruction
while (true) {
for (i = 1; i < num_preds; i++) {
// these instructions are different and cannot be optimized ->
// no further optimization possible
return;
}
}
TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
// insert the instruction at the beginning of the current block
// delete the instruction at the end of all predecessors
for (i = 0; i < num_preds; i++) {
remove_cur_instruction(i, true);
}
}
}
assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
// can no optimize instructions when debug info is needed
return;
}
if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
// not a valid case for optimization
// currently, only blocks that end with two branches (conditional branch followed
// by unconditional branch) are optimized
return;
}
// now it is guaranteed that the block ends with two branch instructions.
// the instructions are inserted at the end of the block before these two branches
int i;
#ifdef ASSERT
for (i = insert_idx - 1; i >= 0; i--) {
if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
assert(false, "block with two successors can have only two branch instructions");
}
}
#endif
// setup a list with the lir-instructions of all successors
for (i = 0; i < num_sux; i++) {
// this can happen with switch-statements where multiple edges are between
// the same blocks.
return;
}
// ignore the label at the beginning of the block
}
// process lir-instructions while all successors begin with the same instruction
while (true) {
for (i = 1; i < num_sux; i++) {
// these instructions are different and cannot be optimized ->
// no further optimization possible
return;
}
}
TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
// insert instruction at end of current block
insert_idx++;
// delete the instructions at the beginning of all successors
for (i = 0; i < num_sux; i++) {
remove_cur_instruction(i, false);
}
}
}
// Implementation of ControlFlowOptimizer
{
}
// push the OSR entry block to the end so that we're not jumping over it.
if (osr_entry) {
}
}
void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
int i = header_idx + 1;
i++;
}
int end_idx = i - 1;
// short loop from header_idx to end_idx found -> reorder blocks such that
// the header_block is the last block instead of the first block of the loop
for (int j = header_idx; j < end_idx; j++) {
}
// correct the flags so that any loop alignment occurs in the right place.
assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
}
}
}
}
}
}
// only blocks with exactly one successor can be deleted. Such blocks
// must always end with an unconditional branch to this successor
if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
return false;
}
assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
// block must have exactly one successor
return true;
}
return false;
}
// substitute branch targets in all branch-instructions of this blocks
void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
}
}
}
}
}
int old_pos = 0;
int new_pos = 0;
while (old_pos < num_blocks) {
if (can_delete_block(block)) {
// propagate backward branch target flag for correct code alignment
}
// collect a list with all predecessors that contains each predecessor only once
// the predecessors of cur are changed during the substitution, so a copy of the
// predecessor list is necessary
int j;
}
}
}
} else {
// adjust position of this block in the block list if blocks before
// have been deleted
}
new_pos++;
}
old_pos++;
}
}
// skip the last block because there a branch is always necessary
TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
// delete last branch instruction
} else {
}
}
TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
// eliminate a conditional branch to the immediate successor
}
}
}
}
}
}
}
#ifdef ASSERT
#endif
// the block contains only a label and a return
// if a predecessor ends with an unconditional jump to this block, then the jump
// can be replaced with a return instruction
//
// Note: the original block with only a return statement cannot be deleted completely
// because the predecessors might have other (conditional) jumps to this block
// -> this may lead to unnecesary return instructions in the final code
"blocks that end with return must not have successors");
if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
// replace the jump to a return with a direct return
// Note: currently the edge between the blocks is not deleted
#ifdef ASSERT
#endif
}
}
}
}
}
}
#ifdef ASSERT
int j;
for (j = 0; j < instructions->length(); j++) {
assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid");
assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid");
}
}
}
}
}
}
#endif
#ifndef PRODUCT
// Implementation of LinearStatistic
switch (counter_idx) {
case counter_method: return "compiled methods";
case counter_fpu_method: return "methods using fpu";
case counter_loop_method: return "methods with loops";
case counter_exception_method:return "methods with xhandler";
case counter_loop: return "loops";
case counter_block: return "blocks";
case counter_loop_block: return "blocks inside loop";
case counter_exception_block: return "exception handler entries";
case counter_interval: return "intervals";
case counter_fixed_interval: return "fixed intervals";
case counter_range: return "ranges";
case counter_fixed_range: return "fixed ranges";
case counter_use_pos: return "use positions";
case counter_fixed_use_pos: return "fixed use positions";
case counter_spill_slots: return "spill slots";
// counter for classes of lir instructions
case counter_instruction: return "total instructions";
case counter_label: return "labels";
case counter_entry: return "method entries";
case counter_return: return "method returns";
case counter_call: return "method calls";
case counter_move: return "moves";
case counter_cmp: return "compare";
case counter_cond_branch: return "conditional branches";
case counter_uncond_branch: return "unconditional branches";
case counter_stub_branch: return "branches to stub";
case counter_alu: return "artithmetic + logic";
case counter_alloc: return "allocations";
case counter_sync: return "synchronisation";
case counter_throw: return "throw";
case counter_unwind: return "unwind";
case counter_typecheck: return "type+null-checks";
case counter_fpu_stack: return "fpu-stack";
case counter_misc_inst: return "other instructions";
case counter_other_inst: return "misc. instructions";
// counter for different types of moves
case counter_move_total: return "total moves";
case counter_move_reg_reg: return "register->register";
case counter_move_reg_stack: return "register->stack";
case counter_move_stack_reg: return "stack->register";
case counter_move_stack_stack:return "stack->stack";
case counter_move_reg_mem: return "register->memory";
case counter_move_mem_reg: return "memory->register";
case counter_move_const_any: return "constant->any";
case blank_line_1: return "";
case blank_line_2: return "";
default: ShouldNotReachHere(); return "";
}
}
if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
return counter_method;
return counter_block;
return counter_instruction;
return counter_move_total;
}
return invalid_counter;
}
for (int i = 0; i < number_of_counters; i++) {
_counters_sum[i] = 0;
_counters_max[i] = -1;
}
}
// add the method-local numbers to the total sum
for (int i = 0; i < number_of_counters; i++) {
}
}
if (CountLinearScan || TraceLinearScanLevel > 0) {
for (int i = 0; i < number_of_counters; i++) {
if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
if (base_counter(i) != invalid_counter) {
} else {
}
if (_counters_max[i] >= 0) {
}
}
}
}
}
if (allocator->has_fpu_registers()) {
}
}
int i;
for (i = 0; i < allocator->interval_count(); i++) {
}
}
}
}
}
bool has_xhandlers = false;
// Note: only count blocks that are in code-emit order
if (cur->loop_depth() > 0) {
}
has_xhandlers = true;
}
for (int j = 0; j < instructions->length(); j++) {
case lir_std_entry:
case lir_rtcall:
case lir_static_call:
case lir_optvirtual_call:
case lir_move: {
if (in->is_register()) {
if (res->is_register()) {
} else if (res->is_address()) {
} else {
}
if (res->is_register()) {
} else {
}
} else if (in->is_address()) {
} else if (in->is_constant()) {
} else {
}
break;
}
case lir_branch:
case lir_cond_float_branch: {
} else {
}
break;
}
case lir_neg:
case lir_add:
case lir_sub:
case lir_mul:
case lir_mul_strictfp:
case lir_div:
case lir_div_strictfp:
case lir_rem:
case lir_sqrt:
case lir_sin:
case lir_cos:
case lir_abs:
case lir_log10:
case lir_log:
case lir_pow:
case lir_exp:
case lir_logic_and:
case lir_logic_or:
case lir_logic_xor:
case lir_shl:
case lir_shr:
case lir_alloc_object:
case lir_monaddr:
case lir_lock:
case lir_null_check:
case lir_leal:
case lir_instanceof:
case lir_checkcast:
case lir_fpop_raw:
case lir_fxch:
case lir_nop:
case lir_push:
case lir_pop:
case lir_convert:
case lir_roundfp:
default: inc_counter(counter_other_inst); break;
}
}
}
if (has_xhandlers) {
}
}
if (CountLinearScan || TraceLinearScanLevel > 0) {
if (TraceLinearScanLevel > 2) {
}
}
}
// Implementation of LinearTimers
for (int i = 0; i < number_of_timers; i++) {
}
}
switch (idx) {
case timer_do_nothing: return "Nothing (Time Check)";
case timer_number_instructions: return "Number Instructions";
case timer_compute_local_live_sets: return "Local Live Sets";
case timer_compute_global_live_sets: return "Global Live Sets";
case timer_build_intervals: return "Build Intervals";
case timer_sort_intervals_before: return "Sort Intervals Before";
case timer_allocate_registers: return "Allocate Registers";
case timer_resolve_data_flow: return "Resolve Data Flow";
case timer_sort_intervals_after: return "Sort Intervals After";
case timer_eliminate_spill_moves: return "Spill optimization";
case timer_assign_reg_num: return "Assign Reg Num";
case timer_allocate_fpu_stack: return "Allocate FPU Stack";
case timer_optimize_lir: return "Optimize LIR";
default: ShouldNotReachHere(); return "";
}
}
void LinearScanTimers::begin_method() {
if (TimeEachLinearScan) {
// reset all timers to measure only current method
for (int i = 0; i < number_of_timers; i++) {
}
}
}
if (TimeEachLinearScan) {
double total = 0;
for (int i = 1; i < number_of_timers; i++) {
}
if (total >= 0.0005) {
// print all information in one line for automatic processing
tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
for (int i = 1; i < number_of_timers; i++) {
}
}
}
}
if (TimeLinearScan) {
// correction value: sum of dummy-timer that only measures the time that
// is necesary to start and stop itself
for (int i = 0; i < number_of_timers; i++) {
tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
}
}
}
#endif // #ifndef PRODUCT